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[openwrt/staging/nbd.git] / target / linux / realtek / files-5.15 / drivers / net / phy / rtl83xx-phy.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Realtek RTL838X Ethernet MDIO interface driver
3 *
4 * Copyright (C) 2020 B. Koblitz
5 */
6
7 #include <linux/module.h>
8 #include <linux/delay.h>
9 #include <linux/of.h>
10 #include <linux/phy.h>
11 #include <linux/netdevice.h>
12 #include <linux/firmware.h>
13 #include <linux/crc32.h>
14 #include <linux/sfp.h>
15 #include <linux/mii.h>
16 #include <linux/mdio.h>
17
18 #include <asm/mach-rtl838x/mach-rtl83xx.h>
19 #include "rtl83xx-phy.h"
20
21 extern struct rtl83xx_soc_info soc_info;
22 extern struct mutex smi_lock;
23
24 #define PHY_PAGE_2 2
25 #define PHY_PAGE_4 4
26
27 /* all Clause-22 RealTek MDIO PHYs use register 0x1f for page select */
28 #define RTL8XXX_PAGE_SELECT 0x1f
29
30 #define RTL8XXX_PAGE_MAIN 0x0000
31 #define RTL821X_PAGE_PORT 0x0266
32 #define RTL821X_PAGE_POWER 0x0a40
33 #define RTL821X_PAGE_GPHY 0x0a42
34 #define RTL821X_PAGE_MAC 0x0a43
35 #define RTL821X_PAGE_STATE 0x0b80
36 #define RTL821X_PAGE_PATCH 0x0b82
37
38 /* Using the special page 0xfff with the MDIO controller found in
39 * RealTek SoCs allows to access the PHY in RAW mode, ie. bypassing
40 * the cache and paging engine of the MDIO controller.
41 */
42 #define RTL83XX_PAGE_RAW 0x0fff
43
44 /* internal RTL821X PHY uses register 0x1d to select media page */
45 #define RTL821XINT_MEDIA_PAGE_SELECT 0x1d
46 /* external RTL821X PHY uses register 0x1e to select media page */
47 #define RTL821XEXT_MEDIA_PAGE_SELECT 0x1e
48
49 #define RTL821X_MEDIA_PAGE_AUTO 0
50 #define RTL821X_MEDIA_PAGE_COPPER 1
51 #define RTL821X_MEDIA_PAGE_FIBRE 3
52 #define RTL821X_MEDIA_PAGE_INTERNAL 8
53
54 #define RTL9300_PHY_ID_MASK 0xf0ffffff
55
56 /* This lock protects the state of the SoC automatically polling the PHYs over the SMI
57 * bus to detect e.g. link and media changes. For operations on the PHYs such as
58 * patching or other configuration changes such as EEE, polling needs to be disabled
59 * since otherwise these operations may fails or lead to unpredictable results.
60 */
61 DEFINE_MUTEX(poll_lock);
62
63 static const struct firmware rtl838x_8380_fw;
64 static const struct firmware rtl838x_8214fc_fw;
65 static const struct firmware rtl838x_8218b_fw;
66
67 static u64 disable_polling(int port)
68 {
69 u64 saved_state;
70
71 mutex_lock(&poll_lock);
72
73 switch (soc_info.family) {
74 case RTL8380_FAMILY_ID:
75 saved_state = sw_r32(RTL838X_SMI_POLL_CTRL);
76 sw_w32_mask(BIT(port), 0, RTL838X_SMI_POLL_CTRL);
77 break;
78 case RTL8390_FAMILY_ID:
79 saved_state = sw_r32(RTL839X_SMI_PORT_POLLING_CTRL + 4);
80 saved_state <<= 32;
81 saved_state |= sw_r32(RTL839X_SMI_PORT_POLLING_CTRL);
82 sw_w32_mask(BIT(port % 32), 0,
83 RTL839X_SMI_PORT_POLLING_CTRL + ((port >> 5) << 2));
84 break;
85 case RTL9300_FAMILY_ID:
86 saved_state = sw_r32(RTL930X_SMI_POLL_CTRL);
87 sw_w32_mask(BIT(port), 0, RTL930X_SMI_POLL_CTRL);
88 break;
89 case RTL9310_FAMILY_ID:
90 pr_warn("%s not implemented for RTL931X\n", __func__);
91 break;
92 }
93
94 mutex_unlock(&poll_lock);
95
96 return saved_state;
97 }
98
99 static int resume_polling(u64 saved_state)
100 {
101 mutex_lock(&poll_lock);
102
103 switch (soc_info.family) {
104 case RTL8380_FAMILY_ID:
105 sw_w32(saved_state, RTL838X_SMI_POLL_CTRL);
106 break;
107 case RTL8390_FAMILY_ID:
108 sw_w32(saved_state >> 32, RTL839X_SMI_PORT_POLLING_CTRL + 4);
109 sw_w32(saved_state, RTL839X_SMI_PORT_POLLING_CTRL);
110 break;
111 case RTL9300_FAMILY_ID:
112 sw_w32(saved_state, RTL930X_SMI_POLL_CTRL);
113 break;
114 case RTL9310_FAMILY_ID:
115 pr_warn("%s not implemented for RTL931X\n", __func__);
116 break;
117 }
118
119 mutex_unlock(&poll_lock);
120
121 return 0;
122 }
123
124 static void rtl8380_int_phy_on_off(struct phy_device *phydev, bool on)
125 {
126 phy_modify(phydev, 0, BMCR_PDOWN, on ? 0 : BMCR_PDOWN);
127 }
128
129 static void rtl8380_rtl8214fc_on_off(struct phy_device *phydev, bool on)
130 {
131 /* fiber ports */
132 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_FIBRE);
133 phy_modify(phydev, 0x10, BMCR_PDOWN, on ? 0 : BMCR_PDOWN);
134
135 /* copper ports */
136 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
137 phy_modify_paged(phydev, RTL821X_PAGE_POWER, 0x10, BMCR_PDOWN, on ? 0 : BMCR_PDOWN);
138 }
139
140 static void rtl8380_phy_reset(struct phy_device *phydev)
141 {
142 phy_modify(phydev, 0, BMCR_RESET, BMCR_RESET);
143 }
144
145 /* The access registers for SDS_MODE_SEL and the LSB for each SDS within */
146 u16 rtl9300_sds_regs[] = { 0x0194, 0x0194, 0x0194, 0x0194, 0x02a0, 0x02a0, 0x02a0, 0x02a0,
147 0x02A4, 0x02A4, 0x0198, 0x0198 };
148 u8 rtl9300_sds_lsb[] = { 0, 6, 12, 18, 0, 6, 12, 18, 0, 6, 0, 6};
149
150 /* Reset the SerDes by powering it off and set a new operations mode
151 * of the SerDes. 0x1f is off. Other modes are
152 * 0x02: SGMII 0x04: 1000BX_FIBER 0x05: FIBER100
153 * 0x06: QSGMII 0x09: RSGMII 0x0d: USXGMII
154 * 0x10: XSGMII 0x12: HISGMII 0x16: 2500Base_X
155 * 0x17: RXAUI_LITE 0x19: RXAUI_PLUS 0x1a: 10G Base-R
156 * 0x1b: 10GR1000BX_AUTO 0x1f: OFF
157 */
158 void rtl9300_sds_rst(int sds_num, u32 mode)
159 {
160 pr_info("%s %d\n", __func__, mode);
161 if (sds_num < 0 || sds_num > 11) {
162 pr_err("Wrong SerDes number: %d\n", sds_num);
163 return;
164 }
165
166 sw_w32_mask(0x1f << rtl9300_sds_lsb[sds_num], 0x1f << rtl9300_sds_lsb[sds_num],
167 rtl9300_sds_regs[sds_num]);
168 mdelay(10);
169
170 sw_w32_mask(0x1f << rtl9300_sds_lsb[sds_num], mode << rtl9300_sds_lsb[sds_num],
171 rtl9300_sds_regs[sds_num]);
172 mdelay(10);
173
174 pr_debug("%s: 194:%08x 198:%08x 2a0:%08x 2a4:%08x\n", __func__,
175 sw_r32(0x194), sw_r32(0x198), sw_r32(0x2a0), sw_r32(0x2a4));
176 }
177
178 void rtl9300_sds_set(int sds_num, u32 mode)
179 {
180 pr_info("%s %d\n", __func__, mode);
181 if (sds_num < 0 || sds_num > 11) {
182 pr_err("Wrong SerDes number: %d\n", sds_num);
183 return;
184 }
185
186 sw_w32_mask(0x1f << rtl9300_sds_lsb[sds_num], mode << rtl9300_sds_lsb[sds_num],
187 rtl9300_sds_regs[sds_num]);
188 mdelay(10);
189
190 pr_debug("%s: 194:%08x 198:%08x 2a0:%08x 2a4:%08x\n", __func__,
191 sw_r32(0x194), sw_r32(0x198), sw_r32(0x2a0), sw_r32(0x2a4));
192 }
193
194 u32 rtl9300_sds_mode_get(int sds_num)
195 {
196 u32 v;
197
198 if (sds_num < 0 || sds_num > 11) {
199 pr_err("Wrong SerDes number: %d\n", sds_num);
200 return 0;
201 }
202
203 v = sw_r32(rtl9300_sds_regs[sds_num]);
204 v >>= rtl9300_sds_lsb[sds_num];
205
206 return v & 0x1f;
207 }
208
209 /* On the RTL839x family of SoCs with inbuilt SerDes, these SerDes are accessed through
210 * a 2048 bit register that holds the contents of the PHY being simulated by the SoC.
211 */
212 int rtl839x_read_sds_phy(int phy_addr, int phy_reg)
213 {
214 int offset = 0;
215 int reg;
216 u32 val;
217
218 if (phy_addr == 49)
219 offset = 0x100;
220
221 /* For the RTL8393 internal SerDes, we simulate a PHY ID in registers 2/3
222 * which would otherwise read as 0.
223 */
224 if (soc_info.id == 0x8393) {
225 if (phy_reg == MII_PHYSID1)
226 return 0x1c;
227 if (phy_reg == MII_PHYSID2)
228 return 0x8393;
229 }
230
231 /* Register RTL839X_SDS12_13_XSG0 is 2048 bit broad, the MSB (bit 15) of the
232 * 0th PHY register is bit 1023 (in byte 0x80). Because PHY-registers are 16
233 * bit broad, we offset by reg << 1. In the SoC 2 registers are stored in
234 * one 32 bit register.
235 */
236 reg = (phy_reg << 1) & 0xfc;
237 val = sw_r32(RTL839X_SDS12_13_XSG0 + offset + 0x80 + reg);
238
239 if (phy_reg & 1)
240 val = (val >> 16) & 0xffff;
241 else
242 val &= 0xffff;
243
244 return val;
245 }
246
247 /* On the RTL930x family of SoCs, the internal SerDes are accessed through an IO
248 * register which simulates commands to an internal MDIO bus.
249 */
250 int rtl930x_read_sds_phy(int phy_addr, int page, int phy_reg)
251 {
252 int i;
253 u32 cmd = phy_addr << 2 | page << 7 | phy_reg << 13 | 1;
254
255 sw_w32(cmd, RTL930X_SDS_INDACS_CMD);
256
257 for (i = 0; i < 100; i++) {
258 if (!(sw_r32(RTL930X_SDS_INDACS_CMD) & 0x1))
259 break;
260 mdelay(1);
261 }
262
263 if (i >= 100)
264 return -EIO;
265
266 return sw_r32(RTL930X_SDS_INDACS_DATA) & 0xffff;
267 }
268
269 int rtl930x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v)
270 {
271 int i;
272 u32 cmd;
273
274 sw_w32(v, RTL930X_SDS_INDACS_DATA);
275 cmd = phy_addr << 2 | page << 7 | phy_reg << 13 | 0x3;
276
277 for (i = 0; i < 100; i++) {
278 if (!(sw_r32(RTL930X_SDS_INDACS_CMD) & 0x1))
279 break;
280 mdelay(1);
281 }
282
283
284 if (i >= 100) {
285 pr_info("%s ERROR !!!!!!!!!!!!!!!!!!!!\n", __func__);
286 return -EIO;
287 }
288
289 return 0;
290 }
291
292 int rtl931x_read_sds_phy(int phy_addr, int page, int phy_reg)
293 {
294 int i;
295 u32 cmd = phy_addr << 2 | page << 7 | phy_reg << 13 | 1;
296
297 pr_debug("%s: phy_addr(SDS-ID) %d, phy_reg: %d\n", __func__, phy_addr, phy_reg);
298 sw_w32(cmd, RTL931X_SERDES_INDRT_ACCESS_CTRL);
299
300 for (i = 0; i < 100; i++) {
301 if (!(sw_r32(RTL931X_SERDES_INDRT_ACCESS_CTRL) & 0x1))
302 break;
303 mdelay(1);
304 }
305
306 if (i >= 100)
307 return -EIO;
308
309 pr_debug("%s: returning %04x\n", __func__, sw_r32(RTL931X_SERDES_INDRT_DATA_CTRL) & 0xffff);
310
311 return sw_r32(RTL931X_SERDES_INDRT_DATA_CTRL) & 0xffff;
312 }
313
314 int rtl931x_write_sds_phy(int phy_addr, int page, int phy_reg, u16 v)
315 {
316 int i;
317 u32 cmd;
318
319 cmd = phy_addr << 2 | page << 7 | phy_reg << 13;
320 sw_w32(cmd, RTL931X_SERDES_INDRT_ACCESS_CTRL);
321
322 sw_w32(v, RTL931X_SERDES_INDRT_DATA_CTRL);
323
324 cmd = sw_r32(RTL931X_SERDES_INDRT_ACCESS_CTRL) | 0x3;
325 sw_w32(cmd, RTL931X_SERDES_INDRT_ACCESS_CTRL);
326
327 for (i = 0; i < 100; i++) {
328 if (!(sw_r32(RTL931X_SERDES_INDRT_ACCESS_CTRL) & 0x1))
329 break;
330 mdelay(1);
331 }
332
333 if (i >= 100)
334 return -EIO;
335
336 return 0;
337 }
338
339 /* On the RTL838x SoCs, the internal SerDes is accessed through direct access to
340 * standard PHY registers, where a 32 bit register holds a 16 bit word as found
341 * in a standard page 0 of a PHY
342 */
343 int rtl838x_read_sds_phy(int phy_addr, int phy_reg)
344 {
345 int offset = 0;
346 u32 val;
347
348 if (phy_addr == 26)
349 offset = 0x100;
350 val = sw_r32(RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2)) & 0xffff;
351
352 return val;
353 }
354
355 int rtl839x_write_sds_phy(int phy_addr, int phy_reg, u16 v)
356 {
357 int offset = 0;
358 int reg;
359 u32 val;
360
361 if (phy_addr == 49)
362 offset = 0x100;
363
364 reg = (phy_reg << 1) & 0xfc;
365 val = v;
366 if (phy_reg & 1) {
367 val = val << 16;
368 sw_w32_mask(0xffff0000, val,
369 RTL839X_SDS12_13_XSG0 + offset + 0x80 + reg);
370 } else {
371 sw_w32_mask(0xffff, val,
372 RTL839X_SDS12_13_XSG0 + offset + 0x80 + reg);
373 }
374
375 return 0;
376 }
377
378 /* Read the link and speed status of the 2 internal SGMII/1000Base-X
379 * ports of the RTL838x SoCs
380 */
381 static int rtl8380_read_status(struct phy_device *phydev)
382 {
383 int err;
384
385 err = genphy_read_status(phydev);
386
387 if (phydev->link) {
388 phydev->speed = SPEED_1000;
389 phydev->duplex = DUPLEX_FULL;
390 }
391
392 return err;
393 }
394
395 /* Read the link and speed status of the 2 internal SGMII/1000Base-X
396 * ports of the RTL8393 SoC
397 */
398 static int rtl8393_read_status(struct phy_device *phydev)
399 {
400 int offset = 0;
401 int err;
402 int phy_addr = phydev->mdio.addr;
403 u32 v;
404
405 err = genphy_read_status(phydev);
406 if (phy_addr == 49)
407 offset = 0x100;
408
409 if (phydev->link) {
410 phydev->speed = SPEED_100;
411 /* Read SPD_RD_00 (bit 13) and SPD_RD_01 (bit 6) out of the internal
412 * PHY registers
413 */
414 v = sw_r32(RTL839X_SDS12_13_XSG0 + offset + 0x80);
415 if (!(v & (1 << 13)) && (v & (1 << 6)))
416 phydev->speed = SPEED_1000;
417 phydev->duplex = DUPLEX_FULL;
418 }
419
420 return err;
421 }
422
423 static int rtl8226_read_page(struct phy_device *phydev)
424 {
425 return __phy_read(phydev, RTL8XXX_PAGE_SELECT);
426 }
427
428 static int rtl8226_write_page(struct phy_device *phydev, int page)
429 {
430 return __phy_write(phydev, RTL8XXX_PAGE_SELECT, page);
431 }
432
433 static int rtl8226_read_status(struct phy_device *phydev)
434 {
435 int ret = 0;
436 u32 val;
437
438 /* TODO: ret = genphy_read_status(phydev);
439 * if (ret < 0) {
440 * pr_info("%s: genphy_read_status failed\n", __func__);
441 * return ret;
442 * }
443 */
444
445 /* Link status must be read twice */
446 for (int i = 0; i < 2; i++)
447 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xA402);
448
449 phydev->link = val & BIT(2) ? 1 : 0;
450 if (!phydev->link)
451 goto out;
452
453 /* Read duplex status */
454 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xA434);
455 if (val < 0)
456 goto out;
457 phydev->duplex = !!(val & BIT(3));
458
459 /* Read speed */
460 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xA434);
461 switch (val & 0x0630) {
462 case 0x0000:
463 phydev->speed = SPEED_10;
464 break;
465 case 0x0010:
466 phydev->speed = SPEED_100;
467 break;
468 case 0x0020:
469 phydev->speed = SPEED_1000;
470 break;
471 case 0x0200:
472 phydev->speed = SPEED_10000;
473 break;
474 case 0x0210:
475 phydev->speed = SPEED_2500;
476 break;
477 case 0x0220:
478 phydev->speed = SPEED_5000;
479 break;
480 default:
481 break;
482 }
483
484 out:
485 return ret;
486 }
487
488 static int rtl8226_advertise_aneg(struct phy_device *phydev)
489 {
490 int ret = 0;
491 u32 v;
492
493 pr_info("In %s\n", __func__);
494
495 v = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
496 if (v < 0)
497 goto out;
498
499 v |= ADVERTISE_10HALF;
500 v |= ADVERTISE_10FULL;
501 v |= ADVERTISE_100HALF;
502 v |= ADVERTISE_100FULL;
503
504 ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE, v);
505
506 /* Allow 1GBit */
507 v = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xA412);
508 if (v < 0)
509 goto out;
510 v |= ADVERTISE_1000FULL;
511
512 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, 0xA412, v);
513 if (ret < 0)
514 goto out;
515
516 /* Allow 2.5G */
517 v = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL);
518 if (v < 0)
519 goto out;
520
521 v |= MDIO_AN_10GBT_CTRL_ADV2_5G;
522 ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, v);
523
524 out:
525 return ret;
526 }
527
528 static int rtl8226_config_aneg(struct phy_device *phydev)
529 {
530 int ret = 0;
531 u32 v;
532
533 pr_debug("In %s\n", __func__);
534 if (phydev->autoneg == AUTONEG_ENABLE) {
535 ret = rtl8226_advertise_aneg(phydev);
536 if (ret)
537 goto out;
538 /* AutoNegotiationEnable */
539 v = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
540 if (v < 0)
541 goto out;
542
543 v |= MDIO_AN_CTRL1_ENABLE; /* Enable AN */
544 ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1, v);
545 if (ret < 0)
546 goto out;
547
548 /* RestartAutoNegotiation */
549 v = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xA400);
550 if (v < 0)
551 goto out;
552 v |= MDIO_AN_CTRL1_RESTART;
553
554 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, 0xA400, v);
555 }
556
557 /* TODO: ret = __genphy_config_aneg(phydev, ret); */
558
559 out:
560 return ret;
561 }
562
563 static int rtl8226_get_eee(struct phy_device *phydev,
564 struct ethtool_eee *e)
565 {
566 u32 val;
567 int addr = phydev->mdio.addr;
568
569 pr_debug("In %s, port %d, was enabled: %d\n", __func__, addr, e->eee_enabled);
570
571 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
572 if (e->eee_enabled) {
573 e->eee_enabled = !!(val & MDIO_EEE_100TX);
574 if (!e->eee_enabled) {
575 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV2);
576 e->eee_enabled = !!(val & MDIO_EEE_2_5GT);
577 }
578 }
579 pr_debug("%s: enabled: %d\n", __func__, e->eee_enabled);
580
581 return 0;
582 }
583
584 static int rtl8226_set_eee(struct phy_device *phydev, struct ethtool_eee *e)
585 {
586 int port = phydev->mdio.addr;
587 u64 poll_state;
588 bool an_enabled;
589 u32 val;
590
591 pr_info("In %s, port %d, enabled %d\n", __func__, port, e->eee_enabled);
592
593 poll_state = disable_polling(port);
594
595 /* Remember aneg state */
596 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
597 an_enabled = !!(val & MDIO_AN_CTRL1_ENABLE);
598
599 /* Setup 100/1000MBit */
600 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
601 if (e->eee_enabled)
602 val |= (MDIO_EEE_100TX | MDIO_EEE_1000T);
603 else
604 val &= (MDIO_EEE_100TX | MDIO_EEE_1000T);
605 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
606
607 /* Setup 2.5GBit */
608 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV2);
609 if (e->eee_enabled)
610 val |= MDIO_EEE_2_5GT;
611 else
612 val &= MDIO_EEE_2_5GT;
613 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV2, val);
614
615 /* RestartAutoNegotiation */
616 val = phy_read_mmd(phydev, MDIO_MMD_VEND2, 0xA400);
617 val |= MDIO_AN_CTRL1_RESTART;
618 phy_write_mmd(phydev, MDIO_MMD_VEND2, 0xA400, val);
619
620 resume_polling(poll_state);
621
622 return 0;
623 }
624
625 static struct fw_header *rtl838x_request_fw(struct phy_device *phydev,
626 const struct firmware *fw,
627 const char *name)
628 {
629 struct device *dev = &phydev->mdio.dev;
630 int err;
631 struct fw_header *h;
632 uint32_t checksum, my_checksum;
633
634 err = request_firmware(&fw, name, dev);
635 if (err < 0)
636 goto out;
637
638 if (fw->size < sizeof(struct fw_header)) {
639 pr_err("Firmware size too small.\n");
640 err = -EINVAL;
641 goto out;
642 }
643
644 h = (struct fw_header *) fw->data;
645 pr_info("Firmware loaded. Size %d, magic: %08x\n", fw->size, h->magic);
646
647 if (h->magic != 0x83808380) {
648 pr_err("Wrong firmware file: MAGIC mismatch.\n");
649 goto out;
650 }
651
652 checksum = h->checksum;
653 h->checksum = 0;
654 my_checksum = ~crc32(0xFFFFFFFFU, fw->data, fw->size);
655 if (checksum != my_checksum) {
656 pr_err("Firmware checksum mismatch.\n");
657 err = -EINVAL;
658 goto out;
659 }
660 h->checksum = checksum;
661
662 return h;
663 out:
664 dev_err(dev, "Unable to load firmware %s (%d)\n", name, err);
665 return NULL;
666 }
667
668 static void rtl821x_phy_setup_package_broadcast(struct phy_device *phydev, bool enable)
669 {
670 int mac = phydev->mdio.addr;
671
672 /* select main page 0 */
673 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
674 /* write to 0x8 to register 0x1d on main page 0 */
675 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_INTERNAL);
676 /* select page 0x266 */
677 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL821X_PAGE_PORT);
678 /* set phy id and target broadcast bitmap in register 0x16 on page 0x266 */
679 phy_write_paged(phydev, RTL83XX_PAGE_RAW, 0x16, (enable?0xff00:0x00) | mac);
680 /* return to main page 0 */
681 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
682 /* write to 0x0 to register 0x1d on main page 0 */
683 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
684 mdelay(1);
685 }
686
687 static int rtl8390_configure_generic(struct phy_device *phydev)
688 {
689 int mac = phydev->mdio.addr;
690 u32 val, phy_id;
691
692 val = phy_read(phydev, 2);
693 phy_id = val << 16;
694 val = phy_read(phydev, 3);
695 phy_id |= val;
696 pr_debug("Phy on MAC %d: %x\n", mac, phy_id);
697
698 /* Read internal PHY ID */
699 phy_write_paged(phydev, 31, 27, 0x0002);
700 val = phy_read_paged(phydev, 31, 28);
701
702 /* Internal RTL8218B, version 2 */
703 phydev_info(phydev, "Detected unknown %x\n", val);
704
705 return 0;
706 }
707
708 static int rtl8380_configure_int_rtl8218b(struct phy_device *phydev)
709 {
710 u32 val, phy_id;
711 int mac = phydev->mdio.addr;
712 struct fw_header *h;
713 u32 *rtl838x_6275B_intPhy_perport;
714 u32 *rtl8218b_6276B_hwEsd_perport;
715
716 val = phy_read(phydev, 2);
717 phy_id = val << 16;
718 val = phy_read(phydev, 3);
719 phy_id |= val;
720 pr_debug("Phy on MAC %d: %x\n", mac, phy_id);
721
722 /* Read internal PHY ID */
723 phy_write_paged(phydev, 31, 27, 0x0002);
724 val = phy_read_paged(phydev, 31, 28);
725 if (val != 0x6275) {
726 phydev_err(phydev, "Expected internal RTL8218B, found PHY-ID %x\n", val);
727 return -1;
728 }
729
730 /* Internal RTL8218B, version 2 */
731 phydev_info(phydev, "Detected internal RTL8218B\n");
732
733 h = rtl838x_request_fw(phydev, &rtl838x_8380_fw, FIRMWARE_838X_8380_1);
734 if (!h)
735 return -1;
736
737 if (h->phy != 0x83800000) {
738 phydev_err(phydev, "Wrong firmware file: PHY mismatch.\n");
739 return -1;
740 }
741
742 rtl838x_6275B_intPhy_perport = (void *)h + sizeof(struct fw_header) + h->parts[8].start;
743 rtl8218b_6276B_hwEsd_perport = (void *)h + sizeof(struct fw_header) + h->parts[9].start;
744
745 // Currently not used
746 // if (sw_r32(RTL838X_DMY_REG31) == 0x1) {
747 // int ipd_flag = 1;
748 // }
749
750 val = phy_read(phydev, MII_BMCR);
751 if (val & BMCR_PDOWN)
752 rtl8380_int_phy_on_off(phydev, true);
753 else
754 rtl8380_phy_reset(phydev);
755 msleep(100);
756
757 /* Ready PHY for patch */
758 for (int p = 0; p < 8; p++) {
759 phy_package_port_write_paged(phydev, p, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL821X_PAGE_PATCH);
760 phy_package_port_write_paged(phydev, p, RTL83XX_PAGE_RAW, 0x10, 0x0010);
761 }
762 msleep(500);
763 for (int p = 0; p < 8; p++) {
764 int i;
765
766 for (i = 0; i < 100 ; i++) {
767 val = phy_package_port_read_paged(phydev, p, RTL821X_PAGE_STATE, 0x10);
768 if (val & 0x40)
769 break;
770 }
771 if (i >= 100) {
772 phydev_err(phydev,
773 "ERROR: Port %d not ready for patch.\n",
774 mac + p);
775 return -1;
776 }
777 }
778 for (int p = 0; p < 8; p++) {
779 int i;
780
781 i = 0;
782 while (rtl838x_6275B_intPhy_perport[i * 2]) {
783 phy_package_port_write_paged(phydev, p, RTL83XX_PAGE_RAW,
784 rtl838x_6275B_intPhy_perport[i * 2],
785 rtl838x_6275B_intPhy_perport[i * 2 + 1]);
786 i++;
787 }
788 i = 0;
789 while (rtl8218b_6276B_hwEsd_perport[i * 2]) {
790 phy_package_port_write_paged(phydev, p, RTL83XX_PAGE_RAW,
791 rtl8218b_6276B_hwEsd_perport[i * 2],
792 rtl8218b_6276B_hwEsd_perport[i * 2 + 1]);
793 i++;
794 }
795 }
796
797 return 0;
798 }
799
800 static int rtl8380_configure_ext_rtl8218b(struct phy_device *phydev)
801 {
802 u32 val, ipd, phy_id;
803 int mac = phydev->mdio.addr;
804 struct fw_header *h;
805 u32 *rtl8380_rtl8218b_perchip;
806 u32 *rtl8218B_6276B_rtl8380_perport;
807 u32 *rtl8380_rtl8218b_perport;
808
809 if (soc_info.family == RTL8380_FAMILY_ID && mac != 0 && mac != 16) {
810 phydev_err(phydev, "External RTL8218B must have PHY-IDs 0 or 16!\n");
811 return -1;
812 }
813 val = phy_read(phydev, 2);
814 phy_id = val << 16;
815 val = phy_read(phydev, 3);
816 phy_id |= val;
817 pr_info("Phy on MAC %d: %x\n", mac, phy_id);
818
819 /* Read internal PHY ID */
820 phy_write_paged(phydev, 31, 27, 0x0002);
821 val = phy_read_paged(phydev, 31, 28);
822 if (val != 0x6276) {
823 phydev_err(phydev, "Expected external RTL8218B, found PHY-ID %x\n", val);
824 return -1;
825 }
826 phydev_info(phydev, "Detected external RTL8218B\n");
827
828 h = rtl838x_request_fw(phydev, &rtl838x_8218b_fw, FIRMWARE_838X_8218b_1);
829 if (!h)
830 return -1;
831
832 if (h->phy != 0x8218b000) {
833 phydev_err(phydev, "Wrong firmware file: PHY mismatch.\n");
834 return -1;
835 }
836
837 rtl8380_rtl8218b_perchip = (void *)h + sizeof(struct fw_header) + h->parts[0].start;
838 rtl8218B_6276B_rtl8380_perport = (void *)h + sizeof(struct fw_header) + h->parts[1].start;
839 rtl8380_rtl8218b_perport = (void *)h + sizeof(struct fw_header) + h->parts[2].start;
840
841 val = phy_read(phydev, MII_BMCR);
842 if (val & BMCR_PDOWN)
843 rtl8380_int_phy_on_off(phydev, true);
844 else
845 rtl8380_phy_reset(phydev);
846
847 msleep(100);
848
849 /* Get Chip revision */
850 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
851 phy_write_paged(phydev, RTL83XX_PAGE_RAW, 0x1b, 0x4);
852 val = phy_read_paged(phydev, RTL83XX_PAGE_RAW, 0x1c);
853
854 phydev_info(phydev, "Detected chip revision %04x\n", val);
855
856 for (int i = 0; rtl8380_rtl8218b_perchip[i * 3] &&
857 rtl8380_rtl8218b_perchip[i * 3 + 1]; i++) {
858 phy_package_port_write_paged(phydev, rtl8380_rtl8218b_perchip[i * 3],
859 RTL83XX_PAGE_RAW, rtl8380_rtl8218b_perchip[i * 3 + 1],
860 rtl8380_rtl8218b_perchip[i * 3 + 2]);
861 }
862
863 /* Enable PHY */
864 for (int i = 0; i < 8; i++) {
865 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
866 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, 0x00, 0x1140);
867 }
868 mdelay(100);
869
870 /* Request patch */
871 for (int i = 0; i < 8; i++) {
872 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL821X_PAGE_PATCH);
873 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, 0x10, 0x0010);
874 }
875
876 mdelay(300);
877
878 /* Verify patch readiness */
879 for (int i = 0; i < 8; i++) {
880 int l;
881
882 for (l = 0; l < 100; l++) {
883 val = phy_package_port_read_paged(phydev, i, RTL821X_PAGE_STATE, 0x10);
884 if (val & 0x40)
885 break;
886 }
887 if (l >= 100) {
888 phydev_err(phydev, "Could not patch PHY\n");
889 return -1;
890 }
891 }
892
893 /* Use Broadcast ID method for patching */
894 rtl821x_phy_setup_package_broadcast(phydev, true);
895
896 phy_write_paged(phydev, RTL83XX_PAGE_RAW, 30, 8);
897 phy_write_paged(phydev, 0x26e, 17, 0xb);
898 phy_write_paged(phydev, 0x26e, 16, 0x2);
899 mdelay(1);
900 ipd = phy_read_paged(phydev, 0x26e, 19);
901 phy_write_paged(phydev, 0, 30, 0);
902 ipd = (ipd >> 4) & 0xf; /* unused ? */
903
904 for (int i = 0; rtl8218B_6276B_rtl8380_perport[i * 2]; i++) {
905 phy_write_paged(phydev, RTL83XX_PAGE_RAW, rtl8218B_6276B_rtl8380_perport[i * 2],
906 rtl8218B_6276B_rtl8380_perport[i * 2 + 1]);
907 }
908
909 /* Disable broadcast ID */
910 rtl821x_phy_setup_package_broadcast(phydev, false);
911
912 return 0;
913 }
914
915 static int rtl8218b_ext_match_phy_device(struct phy_device *phydev)
916 {
917 int addr = phydev->mdio.addr;
918
919 /* Both the RTL8214FC and the external RTL8218B have the same
920 * PHY ID. On the RTL838x, the RTL8218B can only be attached_dev
921 * at PHY IDs 0-7, while the RTL8214FC must be attached via
922 * the pair of SGMII/1000Base-X with higher PHY-IDs
923 */
924 if (soc_info.family == RTL8380_FAMILY_ID)
925 return phydev->phy_id == PHY_ID_RTL8218B_E && addr < 8;
926 else
927 return phydev->phy_id == PHY_ID_RTL8218B_E;
928 }
929
930 static bool rtl8214fc_media_is_fibre(struct phy_device *phydev)
931 {
932 int mac = phydev->mdio.addr;
933
934 static int reg[] = {16, 19, 20, 21};
935 u32 val;
936
937 phy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_INTERNAL);
938 val = phy_package_read_paged(phydev, RTL821X_PAGE_PORT, reg[mac % 4]);
939 phy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
940
941 if (val & BMCR_PDOWN)
942 return false;
943
944 return true;
945 }
946
947 static void rtl8214fc_power_set(struct phy_device *phydev, int port, bool on)
948 {
949 char *state = on ? "on" : "off";
950
951 if (port == PORT_FIBRE) {
952 pr_info("%s: Powering %s FIBRE (port %d)\n", __func__, state, phydev->mdio.addr);
953 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_FIBRE);
954 } else {
955 pr_info("%s: Powering %s COPPER (port %d)\n", __func__, state, phydev->mdio.addr);
956 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
957 }
958
959 if (on) {
960 phy_modify_paged(phydev, RTL821X_PAGE_POWER, 0x10, BMCR_PDOWN, 0);
961 } else {
962 phy_modify_paged(phydev, RTL821X_PAGE_POWER, 0x10, 0, BMCR_PDOWN);
963 }
964
965 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
966 }
967
968 static int rtl8214fc_suspend(struct phy_device *phydev)
969 {
970 rtl8214fc_power_set(phydev, PORT_MII, false);
971 rtl8214fc_power_set(phydev, PORT_FIBRE, false);
972
973 return 0;
974 }
975
976 static int rtl8214fc_resume(struct phy_device *phydev)
977 {
978 if (rtl8214fc_media_is_fibre(phydev)) {
979 rtl8214fc_power_set(phydev, PORT_MII, false);
980 rtl8214fc_power_set(phydev, PORT_FIBRE, true);
981 } else {
982 rtl8214fc_power_set(phydev, PORT_FIBRE, false);
983 rtl8214fc_power_set(phydev, PORT_MII, true);
984 }
985
986 return 0;
987 }
988
989 static void rtl8214fc_media_set(struct phy_device *phydev, bool set_fibre)
990 {
991 int mac = phydev->mdio.addr;
992
993 static int reg[] = {16, 19, 20, 21};
994 int val;
995
996 pr_info("%s: port %d, set_fibre: %d\n", __func__, mac, set_fibre);
997 phy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_INTERNAL);
998 val = phy_package_read_paged(phydev, RTL821X_PAGE_PORT, reg[mac % 4]);
999
1000 val |= BIT(10);
1001 if (set_fibre) {
1002 val &= ~BMCR_PDOWN;
1003 } else {
1004 val |= BMCR_PDOWN;
1005 }
1006
1007 phy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_INTERNAL);
1008 phy_package_write_paged(phydev, RTL821X_PAGE_PORT, reg[mac % 4], val);
1009 phy_package_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1010
1011 if (!phydev->suspended) {
1012 if (set_fibre) {
1013 rtl8214fc_power_set(phydev, PORT_MII, false);
1014 rtl8214fc_power_set(phydev, PORT_FIBRE, true);
1015 } else {
1016 rtl8214fc_power_set(phydev, PORT_FIBRE, false);
1017 rtl8214fc_power_set(phydev, PORT_MII, true);
1018 }
1019 }
1020 }
1021
1022 static int rtl8214fc_set_port(struct phy_device *phydev, int port)
1023 {
1024 bool is_fibre = (port == PORT_FIBRE ? true : false);
1025 int addr = phydev->mdio.addr;
1026
1027 pr_debug("%s port %d to %d\n", __func__, addr, port);
1028
1029 rtl8214fc_media_set(phydev, is_fibre);
1030
1031 return 0;
1032 }
1033
1034 static int rtl8214fc_get_port(struct phy_device *phydev)
1035 {
1036 int addr = phydev->mdio.addr;
1037
1038 pr_debug("%s: port %d\n", __func__, addr);
1039 if (rtl8214fc_media_is_fibre(phydev))
1040 return PORT_FIBRE;
1041
1042 return PORT_MII;
1043 }
1044
1045 /* Enable EEE on the RTL8218B PHYs
1046 * The method used is not the preferred way (which would be based on the MAC-EEE state,
1047 * but the only way that works since the kernel first enables EEE in the MAC
1048 * and then sets up the PHY. The MAC-based approach would require the oppsite.
1049 */
1050 void rtl8218d_eee_set(struct phy_device *phydev, bool enable)
1051 {
1052 u32 val;
1053 bool an_enabled;
1054
1055 pr_debug("In %s %d, enable %d\n", __func__, phydev->mdio.addr, enable);
1056 /* Set GPHY page to copper */
1057 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1058
1059 val = phy_read(phydev, MII_BMCR);
1060 an_enabled = val & BMCR_ANENABLE;
1061
1062 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
1063 val |= MDIO_EEE_1000T | MDIO_EEE_100TX;
1064 phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, enable ? (MDIO_EEE_100TX | MDIO_EEE_1000T) : 0);
1065
1066 /* 500M EEE ability */
1067 val = phy_read_paged(phydev, RTL821X_PAGE_GPHY, 20);
1068 if (enable)
1069 val |= BIT(7);
1070 else
1071 val &= ~BIT(7);
1072 phy_write_paged(phydev, RTL821X_PAGE_GPHY, 20, val);
1073
1074 /* Restart AN if enabled */
1075 if (an_enabled) {
1076 val = phy_read(phydev, MII_BMCR);
1077 val |= BMCR_ANRESTART;
1078 phy_write(phydev, MII_BMCR, val);
1079 }
1080
1081 /* GPHY page back to auto */
1082 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1083 }
1084
1085 static int rtl8218b_get_eee(struct phy_device *phydev,
1086 struct ethtool_eee *e)
1087 {
1088 u32 val;
1089 int addr = phydev->mdio.addr;
1090
1091 pr_debug("In %s, port %d, was enabled: %d\n", __func__, addr, e->eee_enabled);
1092
1093 /* Set GPHY page to copper */
1094 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1095
1096 val = phy_read_paged(phydev, 7, MDIO_AN_EEE_ADV);
1097 if (e->eee_enabled) {
1098 /* Verify vs MAC-based EEE */
1099 e->eee_enabled = !!(val & BIT(7));
1100 if (!e->eee_enabled) {
1101 val = phy_read_paged(phydev, RTL821X_PAGE_MAC, 25);
1102 e->eee_enabled = !!(val & BIT(4));
1103 }
1104 }
1105 pr_debug("%s: enabled: %d\n", __func__, e->eee_enabled);
1106
1107 /* GPHY page to auto */
1108 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1109
1110 return 0;
1111 }
1112
1113 static int rtl8218d_get_eee(struct phy_device *phydev,
1114 struct ethtool_eee *e)
1115 {
1116 u32 val;
1117 int addr = phydev->mdio.addr;
1118
1119 pr_debug("In %s, port %d, was enabled: %d\n", __func__, addr, e->eee_enabled);
1120
1121 /* Set GPHY page to copper */
1122 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1123
1124 val = phy_read_paged(phydev, 7, MDIO_AN_EEE_ADV);
1125 if (e->eee_enabled)
1126 e->eee_enabled = !!(val & BIT(7));
1127 pr_debug("%s: enabled: %d\n", __func__, e->eee_enabled);
1128
1129 /* GPHY page to auto */
1130 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1131
1132 return 0;
1133 }
1134
1135 static int rtl8214fc_set_eee(struct phy_device *phydev,
1136 struct ethtool_eee *e)
1137 {
1138 u32 poll_state;
1139 int port = phydev->mdio.addr;
1140 bool an_enabled;
1141 u32 val;
1142
1143 pr_debug("In %s port %d, enabled %d\n", __func__, port, e->eee_enabled);
1144
1145 if (rtl8214fc_media_is_fibre(phydev)) {
1146 netdev_err(phydev->attached_dev, "Port %d configured for FIBRE", port);
1147 return -ENOTSUPP;
1148 }
1149
1150 poll_state = disable_polling(port);
1151
1152 /* Set GPHY page to copper */
1153 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1154
1155 /* Get auto-negotiation status */
1156 val = phy_read(phydev, MII_BMCR);
1157 an_enabled = val & BMCR_ANENABLE;
1158
1159 pr_info("%s: aneg: %d\n", __func__, an_enabled);
1160 val = phy_read_paged(phydev, RTL821X_PAGE_MAC, 25);
1161 val &= ~BIT(5); /* Use MAC-based EEE */
1162 phy_write_paged(phydev, RTL821X_PAGE_MAC, 25, val);
1163
1164 /* Enable 100M (bit 1) / 1000M (bit 2) EEE */
1165 phy_write_paged(phydev, 7, MDIO_AN_EEE_ADV, e->eee_enabled ? (MDIO_EEE_100TX | MDIO_EEE_1000T) : 0);
1166
1167 /* 500M EEE ability */
1168 val = phy_read_paged(phydev, RTL821X_PAGE_GPHY, 20);
1169 if (e->eee_enabled)
1170 val |= BIT(7);
1171 else
1172 val &= ~BIT(7);
1173
1174 phy_write_paged(phydev, RTL821X_PAGE_GPHY, 20, val);
1175
1176 /* Restart AN if enabled */
1177 if (an_enabled) {
1178 pr_info("%s: doing aneg\n", __func__);
1179 val = phy_read(phydev, MII_BMCR);
1180 val |= BMCR_ANRESTART;
1181 phy_write(phydev, MII_BMCR, val);
1182 }
1183
1184 /* GPHY page back to auto */
1185 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1186
1187 resume_polling(poll_state);
1188
1189 return 0;
1190 }
1191
1192 static int rtl8214fc_get_eee(struct phy_device *phydev,
1193 struct ethtool_eee *e)
1194 {
1195 int addr = phydev->mdio.addr;
1196
1197 pr_debug("In %s port %d, enabled %d\n", __func__, addr, e->eee_enabled);
1198 if (rtl8214fc_media_is_fibre(phydev)) {
1199 netdev_err(phydev->attached_dev, "Port %d configured for FIBRE", addr);
1200 return -ENOTSUPP;
1201 }
1202
1203 return rtl8218b_get_eee(phydev, e);
1204 }
1205
1206 static int rtl8218b_set_eee(struct phy_device *phydev, struct ethtool_eee *e)
1207 {
1208 int port = phydev->mdio.addr;
1209 u64 poll_state;
1210 u32 val;
1211 bool an_enabled;
1212
1213 pr_info("In %s, port %d, enabled %d\n", __func__, port, e->eee_enabled);
1214
1215 poll_state = disable_polling(port);
1216
1217 /* Set GPHY page to copper */
1218 phy_write(phydev, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1219 val = phy_read(phydev, MII_BMCR);
1220 an_enabled = val & BMCR_ANENABLE;
1221
1222 if (e->eee_enabled) {
1223 /* 100/1000M EEE Capability */
1224 phy_write(phydev, 13, 0x0007);
1225 phy_write(phydev, 14, 0x003C);
1226 phy_write(phydev, 13, 0x4007);
1227 phy_write(phydev, 14, 0x0006);
1228
1229 val = phy_read_paged(phydev, RTL821X_PAGE_MAC, 25);
1230 val |= BIT(4);
1231 phy_write_paged(phydev, RTL821X_PAGE_MAC, 25, val);
1232 } else {
1233 /* 100/1000M EEE Capability */
1234 phy_write(phydev, 13, 0x0007);
1235 phy_write(phydev, 14, 0x003C);
1236 phy_write(phydev, 13, 0x0007);
1237 phy_write(phydev, 14, 0x0000);
1238
1239 val = phy_read_paged(phydev, RTL821X_PAGE_MAC, 25);
1240 val &= ~BIT(4);
1241 phy_write_paged(phydev, RTL821X_PAGE_MAC, 25, val);
1242 }
1243
1244 /* Restart AN if enabled */
1245 if (an_enabled) {
1246 val = phy_read(phydev, MII_BMCR);
1247 val |= BMCR_ANRESTART;
1248 phy_write(phydev, MII_BMCR, val);
1249 }
1250
1251 /* GPHY page back to auto */
1252 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1253
1254 pr_info("%s done\n", __func__);
1255 resume_polling(poll_state);
1256
1257 return 0;
1258 }
1259
1260 static int rtl8218d_set_eee(struct phy_device *phydev, struct ethtool_eee *e)
1261 {
1262 int addr = phydev->mdio.addr;
1263 u64 poll_state;
1264
1265 pr_info("In %s, port %d, enabled %d\n", __func__, addr, e->eee_enabled);
1266
1267 poll_state = disable_polling(addr);
1268
1269 rtl8218d_eee_set(phydev, (bool) e->eee_enabled);
1270
1271 resume_polling(poll_state);
1272
1273 return 0;
1274 }
1275
1276 static int rtl8214c_match_phy_device(struct phy_device *phydev)
1277 {
1278 return phydev->phy_id == PHY_ID_RTL8214C;
1279 }
1280
1281 static int rtl8380_configure_rtl8214c(struct phy_device *phydev)
1282 {
1283 u32 phy_id, val;
1284 int mac = phydev->mdio.addr;
1285
1286 val = phy_read(phydev, 2);
1287 phy_id = val << 16;
1288 val = phy_read(phydev, 3);
1289 phy_id |= val;
1290 pr_debug("Phy on MAC %d: %x\n", mac, phy_id);
1291
1292 phydev_info(phydev, "Detected external RTL8214C\n");
1293
1294 /* GPHY auto conf */
1295 phy_write_paged(phydev, RTL821X_PAGE_GPHY, RTL821XINT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1296
1297 return 0;
1298 }
1299
1300 static int rtl8380_configure_rtl8214fc(struct phy_device *phydev)
1301 {
1302 int mac = phydev->mdio.addr;
1303 struct fw_header *h;
1304 u32 *rtl8380_rtl8214fc_perchip;
1305 u32 *rtl8380_rtl8214fc_perport;
1306 u32 phy_id;
1307 u32 val;
1308
1309 val = phy_read(phydev, 2);
1310 phy_id = val << 16;
1311 val = phy_read(phydev, 3);
1312 phy_id |= val;
1313 pr_debug("Phy on MAC %d: %x\n", mac, phy_id);
1314
1315 /* Read internal PHY id */
1316 phy_write_paged(phydev, 0, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1317 phy_write_paged(phydev, 0x1f, 0x1b, 0x0002);
1318 val = phy_read_paged(phydev, 0x1f, 0x1c);
1319 if (val != 0x6276) {
1320 phydev_err(phydev, "Expected external RTL8214FC, found PHY-ID %x\n", val);
1321 return -1;
1322 }
1323 phydev_info(phydev, "Detected external RTL8214FC\n");
1324
1325 h = rtl838x_request_fw(phydev, &rtl838x_8214fc_fw, FIRMWARE_838X_8214FC_1);
1326 if (!h)
1327 return -1;
1328
1329 if (h->phy != 0x8214fc00) {
1330 phydev_err(phydev, "Wrong firmware file: PHY mismatch.\n");
1331 return -1;
1332 }
1333
1334 rtl8380_rtl8214fc_perchip = (void *)h + sizeof(struct fw_header) + h->parts[0].start;
1335
1336 rtl8380_rtl8214fc_perport = (void *)h + sizeof(struct fw_header) + h->parts[1].start;
1337
1338 /* detect phy version */
1339 phy_write_paged(phydev, RTL83XX_PAGE_RAW, 27, 0x0004);
1340 val = phy_read_paged(phydev, RTL83XX_PAGE_RAW, 28);
1341
1342 val = phy_read(phydev, 16);
1343 if (val & BMCR_PDOWN)
1344 rtl8380_rtl8214fc_on_off(phydev, true);
1345 else
1346 rtl8380_phy_reset(phydev);
1347
1348 msleep(100);
1349 phy_write_paged(phydev, 0, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1350
1351 for (int i = 0; rtl8380_rtl8214fc_perchip[i * 3] &&
1352 rtl8380_rtl8214fc_perchip[i * 3 + 1]; i++) {
1353 u32 page = 0;
1354
1355 if (rtl8380_rtl8214fc_perchip[i * 3 + 1] == 0x1f)
1356 page = rtl8380_rtl8214fc_perchip[i * 3 + 2];
1357 if (rtl8380_rtl8214fc_perchip[i * 3 + 1] == 0x13 && page == 0x260) {
1358 val = phy_read_paged(phydev, 0x260, 13);
1359 val = (val & 0x1f00) | (rtl8380_rtl8214fc_perchip[i * 3 + 2] & 0xe0ff);
1360 phy_write_paged(phydev, RTL83XX_PAGE_RAW,
1361 rtl8380_rtl8214fc_perchip[i * 3 + 1], val);
1362 } else {
1363 phy_write_paged(phydev, RTL83XX_PAGE_RAW,
1364 rtl8380_rtl8214fc_perchip[i * 3 + 1],
1365 rtl8380_rtl8214fc_perchip[i * 3 + 2]);
1366 }
1367 }
1368
1369 /* Force copper medium */
1370 for (int i = 0; i < 4; i++) {
1371 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
1372 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_COPPER);
1373 }
1374
1375 /* Enable PHY */
1376 for (int i = 0; i < 4; i++) {
1377 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
1378 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, 0x00, 0x1140);
1379 }
1380 mdelay(100);
1381
1382 /* Disable Autosensing */
1383 for (int i = 0; i < 4; i++) {
1384 int l;
1385
1386 for (l = 0; l < 100; l++) {
1387 val = phy_package_port_read_paged(phydev, i, RTL821X_PAGE_GPHY, 0x10);
1388 if ((val & 0x7) >= 3)
1389 break;
1390 }
1391 if (l >= 100) {
1392 phydev_err(phydev, "Could not disable autosensing\n");
1393 return -1;
1394 }
1395 }
1396
1397 /* Request patch */
1398 for (int i = 0; i < 4; i++) {
1399 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL821X_PAGE_PATCH);
1400 phy_package_port_write_paged(phydev, i, RTL83XX_PAGE_RAW, 0x10, 0x0010);
1401 }
1402 mdelay(300);
1403
1404 /* Verify patch readiness */
1405 for (int i = 0; i < 4; i++) {
1406 int l;
1407
1408 for (l = 0; l < 100; l++) {
1409 val = phy_package_port_read_paged(phydev, i, RTL821X_PAGE_STATE, 0x10);
1410 if (val & 0x40)
1411 break;
1412 }
1413 if (l >= 100) {
1414 phydev_err(phydev, "Could not patch PHY\n");
1415 return -1;
1416 }
1417 }
1418 /* Use Broadcast ID method for patching */
1419 rtl821x_phy_setup_package_broadcast(phydev, true);
1420
1421 for (int i = 0; rtl8380_rtl8214fc_perport[i * 2]; i++) {
1422 phy_write_paged(phydev, RTL83XX_PAGE_RAW, rtl8380_rtl8214fc_perport[i * 2],
1423 rtl8380_rtl8214fc_perport[i * 2 + 1]);
1424 }
1425
1426 /* Disable broadcast ID */
1427 rtl821x_phy_setup_package_broadcast(phydev, false);
1428
1429 /* Auto medium selection */
1430 for (int i = 0; i < 4; i++) {
1431 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL8XXX_PAGE_SELECT, RTL8XXX_PAGE_MAIN);
1432 phy_write_paged(phydev, RTL83XX_PAGE_RAW, RTL821XEXT_MEDIA_PAGE_SELECT, RTL821X_MEDIA_PAGE_AUTO);
1433 }
1434
1435 return 0;
1436 }
1437
1438 static int rtl8214fc_match_phy_device(struct phy_device *phydev)
1439 {
1440 int addr = phydev->mdio.addr;
1441
1442 return phydev->phy_id == PHY_ID_RTL8214FC && addr >= 24;
1443 }
1444
1445 static int rtl8380_configure_serdes(struct phy_device *phydev)
1446 {
1447 u32 v;
1448 u32 sds_conf_value;
1449 int i;
1450 struct fw_header *h;
1451 u32 *rtl8380_sds_take_reset;
1452 u32 *rtl8380_sds_common;
1453 u32 *rtl8380_sds01_qsgmii_6275b;
1454 u32 *rtl8380_sds23_qsgmii_6275b;
1455 u32 *rtl8380_sds4_fiber_6275b;
1456 u32 *rtl8380_sds5_fiber_6275b;
1457 u32 *rtl8380_sds_reset;
1458 u32 *rtl8380_sds_release_reset;
1459
1460 phydev_info(phydev, "Detected internal RTL8380 SERDES\n");
1461
1462 h = rtl838x_request_fw(phydev, &rtl838x_8218b_fw, FIRMWARE_838X_8380_1);
1463 if (!h)
1464 return -1;
1465
1466 if (h->magic != 0x83808380) {
1467 phydev_err(phydev, "Wrong firmware file: magic number mismatch.\n");
1468 return -1;
1469 }
1470
1471 rtl8380_sds_take_reset = (void *)h + sizeof(struct fw_header) + h->parts[0].start;
1472
1473 rtl8380_sds_common = (void *)h + sizeof(struct fw_header) + h->parts[1].start;
1474
1475 rtl8380_sds01_qsgmii_6275b = (void *)h + sizeof(struct fw_header) + h->parts[2].start;
1476
1477 rtl8380_sds23_qsgmii_6275b = (void *)h + sizeof(struct fw_header) + h->parts[3].start;
1478
1479 rtl8380_sds4_fiber_6275b = (void *)h + sizeof(struct fw_header) + h->parts[4].start;
1480
1481 rtl8380_sds5_fiber_6275b = (void *)h + sizeof(struct fw_header) + h->parts[5].start;
1482
1483 rtl8380_sds_reset = (void *)h + sizeof(struct fw_header) + h->parts[6].start;
1484
1485 rtl8380_sds_release_reset = (void *)h + sizeof(struct fw_header) + h->parts[7].start;
1486
1487 /* Back up serdes power off value */
1488 sds_conf_value = sw_r32(RTL838X_SDS_CFG_REG);
1489 pr_info("SDS power down value: %x\n", sds_conf_value);
1490
1491 /* take serdes into reset */
1492 i = 0;
1493 while (rtl8380_sds_take_reset[2 * i]) {
1494 sw_w32(rtl8380_sds_take_reset[2 * i + 1], rtl8380_sds_take_reset[2 * i]);
1495 i++;
1496 udelay(1000);
1497 }
1498
1499 /* apply common serdes patch */
1500 i = 0;
1501 while (rtl8380_sds_common[2 * i]) {
1502 sw_w32(rtl8380_sds_common[2 * i + 1], rtl8380_sds_common[2 * i]);
1503 i++;
1504 udelay(1000);
1505 }
1506
1507 /* internal R/W enable */
1508 sw_w32(3, RTL838X_INT_RW_CTRL);
1509
1510 /* SerDes ports 4 and 5 are FIBRE ports */
1511 sw_w32_mask(0x7 | 0x38, 1 | (1 << 3), RTL838X_INT_MODE_CTRL);
1512
1513 /* SerDes module settings, SerDes 0-3 are QSGMII */
1514 v = 0x6 << 25 | 0x6 << 20 | 0x6 << 15 | 0x6 << 10;
1515 /* SerDes 4 and 5 are 1000BX FIBRE */
1516 v |= 0x4 << 5 | 0x4;
1517 sw_w32(v, RTL838X_SDS_MODE_SEL);
1518
1519 pr_info("PLL control register: %x\n", sw_r32(RTL838X_PLL_CML_CTRL));
1520 sw_w32_mask(0xfffffff0, 0xaaaaaaaf & 0xf, RTL838X_PLL_CML_CTRL);
1521 i = 0;
1522 while (rtl8380_sds01_qsgmii_6275b[2 * i]) {
1523 sw_w32(rtl8380_sds01_qsgmii_6275b[2 * i + 1],
1524 rtl8380_sds01_qsgmii_6275b[2 * i]);
1525 i++;
1526 }
1527
1528 i = 0;
1529 while (rtl8380_sds23_qsgmii_6275b[2 * i]) {
1530 sw_w32(rtl8380_sds23_qsgmii_6275b[2 * i + 1], rtl8380_sds23_qsgmii_6275b[2 * i]);
1531 i++;
1532 }
1533
1534 i = 0;
1535 while (rtl8380_sds4_fiber_6275b[2 * i]) {
1536 sw_w32(rtl8380_sds4_fiber_6275b[2 * i + 1], rtl8380_sds4_fiber_6275b[2 * i]);
1537 i++;
1538 }
1539
1540 i = 0;
1541 while (rtl8380_sds5_fiber_6275b[2 * i]) {
1542 sw_w32(rtl8380_sds5_fiber_6275b[2 * i + 1], rtl8380_sds5_fiber_6275b[2 * i]);
1543 i++;
1544 }
1545
1546 i = 0;
1547 while (rtl8380_sds_reset[2 * i]) {
1548 sw_w32(rtl8380_sds_reset[2 * i + 1], rtl8380_sds_reset[2 * i]);
1549 i++;
1550 }
1551
1552 i = 0;
1553 while (rtl8380_sds_release_reset[2 * i]) {
1554 sw_w32(rtl8380_sds_release_reset[2 * i + 1], rtl8380_sds_release_reset[2 * i]);
1555 i++;
1556 }
1557
1558 pr_info("SDS power down value now: %x\n", sw_r32(RTL838X_SDS_CFG_REG));
1559 sw_w32(sds_conf_value, RTL838X_SDS_CFG_REG);
1560
1561 pr_info("Configuration of SERDES done\n");
1562
1563 return 0;
1564 }
1565
1566 static int rtl8390_configure_serdes(struct phy_device *phydev)
1567 {
1568 phydev_info(phydev, "Detected internal RTL8390 SERDES\n");
1569
1570 /* In autoneg state, force link, set SR4_CFG_EN_LINK_FIB1G */
1571 sw_w32_mask(0, 1 << 18, RTL839X_SDS12_13_XSG0 + 0x0a);
1572
1573 /* Disable EEE: Clear FRE16_EEE_RSG_FIB1G, FRE16_EEE_STD_FIB1G,
1574 * FRE16_C1_PWRSAV_EN_FIB1G, FRE16_C2_PWRSAV_EN_FIB1G
1575 * and FRE16_EEE_QUIET_FIB1G
1576 */
1577 sw_w32_mask(0x1f << 10, 0, RTL839X_SDS12_13_XSG0 + 0xe0);
1578
1579 return 0;
1580 }
1581
1582 void rtl9300_sds_field_w(int sds, u32 page, u32 reg, int end_bit, int start_bit, u32 v)
1583 {
1584 int l = end_bit - start_bit + 1;
1585 u32 data = v;
1586
1587 if (l < 32) {
1588 u32 mask = BIT(l) - 1;
1589
1590 data = rtl930x_read_sds_phy(sds, page, reg);
1591 data &= ~(mask << start_bit);
1592 data |= (v & mask) << start_bit;
1593 }
1594
1595 rtl930x_write_sds_phy(sds, page, reg, data);
1596 }
1597
1598 u32 rtl9300_sds_field_r(int sds, u32 page, u32 reg, int end_bit, int start_bit)
1599 {
1600 int l = end_bit - start_bit + 1;
1601 u32 v = rtl930x_read_sds_phy(sds, page, reg);
1602
1603 if (l >= 32)
1604 return v;
1605
1606 return (v >> start_bit) & (BIT(l) - 1);
1607 }
1608
1609 /* Read the link and speed status of the internal SerDes of the RTL9300
1610 */
1611 static int rtl9300_read_status(struct phy_device *phydev)
1612 {
1613 struct device *dev = &phydev->mdio.dev;
1614 int phy_addr = phydev->mdio.addr;
1615 struct device_node *dn;
1616 u32 sds_num = 0, status, latch_status, mode;
1617
1618 if (dev->of_node) {
1619 dn = dev->of_node;
1620
1621 if (of_property_read_u32(dn, "sds", &sds_num))
1622 sds_num = -1;
1623 pr_info("%s: Port %d, SerDes is %d\n", __func__, phy_addr, sds_num);
1624 } else {
1625 dev_err(dev, "No DT node.\n");
1626 return -EINVAL;
1627 }
1628
1629 if (sds_num < 0)
1630 return 0;
1631
1632 mode = rtl9300_sds_mode_get(sds_num);
1633 pr_info("%s got SDS mode %02x\n", __func__, mode);
1634 if (mode == 0x1a) { /* 10GR mode */
1635 status = rtl9300_sds_field_r(sds_num, 0x5, 0, 12, 12);
1636 latch_status = rtl9300_sds_field_r(sds_num, 0x4, 1, 2, 2);
1637 status |= rtl9300_sds_field_r(sds_num, 0x5, 0, 12, 12);
1638 latch_status |= rtl9300_sds_field_r(sds_num, 0x4, 1, 2, 2);
1639 } else {
1640 status = rtl9300_sds_field_r(sds_num, 0x1, 29, 8, 0);
1641 latch_status = rtl9300_sds_field_r(sds_num, 0x1, 30, 8, 0);
1642 status |= rtl9300_sds_field_r(sds_num, 0x1, 29, 8, 0);
1643 latch_status |= rtl9300_sds_field_r(sds_num, 0x1, 30, 8, 0);
1644 }
1645
1646 pr_info("%s link status: status: %d, latch %d\n", __func__, status, latch_status);
1647
1648 if (latch_status) {
1649 phydev->link = true;
1650 if (mode == 0x1a)
1651 phydev->speed = SPEED_10000;
1652 else
1653 phydev->speed = SPEED_1000;
1654
1655 phydev->duplex = DUPLEX_FULL;
1656 }
1657
1658 return 0;
1659 }
1660
1661 void rtl930x_sds_rx_rst(int sds_num, phy_interface_t phy_if)
1662 {
1663 int page = 0x2e; /* 10GR and USXGMII */
1664
1665 if (phy_if == PHY_INTERFACE_MODE_1000BASEX)
1666 page = 0x24;
1667
1668 rtl9300_sds_field_w(sds_num, page, 0x15, 4, 4, 0x1);
1669 mdelay(5);
1670 rtl9300_sds_field_w(sds_num, page, 0x15, 4, 4, 0x0);
1671 }
1672
1673 /* Force PHY modes on 10GBit Serdes
1674 */
1675 void rtl9300_force_sds_mode(int sds, phy_interface_t phy_if)
1676 {
1677 int lc_value;
1678 int sds_mode;
1679 bool lc_on;
1680 int lane_0 = (sds % 2) ? sds - 1 : sds;
1681 u32 v;
1682
1683 pr_info("%s: SDS: %d, mode %d\n", __func__, sds, phy_if);
1684 switch (phy_if) {
1685 case PHY_INTERFACE_MODE_SGMII:
1686 sds_mode = 0x2;
1687 lc_on = false;
1688 lc_value = 0x1;
1689 break;
1690
1691 case PHY_INTERFACE_MODE_HSGMII:
1692 sds_mode = 0x12;
1693 lc_value = 0x3;
1694 /* Configure LC */
1695 break;
1696
1697 case PHY_INTERFACE_MODE_1000BASEX:
1698 sds_mode = 0x04;
1699 lc_on = false;
1700 break;
1701
1702 case PHY_INTERFACE_MODE_2500BASEX:
1703 sds_mode = 0x16;
1704 lc_value = 0x3;
1705 /* Configure LC */
1706 break;
1707
1708 case PHY_INTERFACE_MODE_10GBASER:
1709 sds_mode = 0x1a;
1710 lc_on = true;
1711 lc_value = 0x5;
1712 break;
1713
1714 case PHY_INTERFACE_MODE_NA:
1715 /* This will disable SerDes */
1716 sds_mode = 0x1f;
1717 break;
1718
1719 default:
1720 pr_err("%s: unknown serdes mode: %s\n",
1721 __func__, phy_modes(phy_if));
1722 return;
1723 }
1724
1725 pr_info("%s --------------------- serdes %d forcing to %x ...\n", __func__, sds, sds_mode);
1726 /* Power down SerDes */
1727 rtl9300_sds_field_w(sds, 0x20, 0, 7, 6, 0x3);
1728 if (sds == 5) pr_info("%s after %x\n", __func__, rtl930x_read_sds_phy(sds, 0x20, 0));
1729
1730 if (sds == 5) pr_info("%s a %x\n", __func__, rtl930x_read_sds_phy(sds, 0x1f, 9));
1731 /* Force mode enable */
1732 rtl9300_sds_field_w(sds, 0x1f, 9, 6, 6, 0x1);
1733 if (sds == 5) pr_info("%s b %x\n", __func__, rtl930x_read_sds_phy(sds, 0x1f, 9));
1734
1735 /* SerDes off */
1736 rtl9300_sds_field_w(sds, 0x1f, 9, 11, 7, 0x1f);
1737
1738 if (phy_if == PHY_INTERFACE_MODE_NA)
1739 return;
1740
1741 if (sds == 5) pr_info("%s c %x\n", __func__, rtl930x_read_sds_phy(sds, 0x20, 18));
1742 /* Enable LC and ring */
1743 rtl9300_sds_field_w(lane_0, 0x20, 18, 3, 0, 0xf);
1744
1745 if (sds == lane_0)
1746 rtl9300_sds_field_w(lane_0, 0x20, 18, 5, 4, 0x1);
1747 else
1748 rtl9300_sds_field_w(lane_0, 0x20, 18, 7, 6, 0x1);
1749
1750 rtl9300_sds_field_w(sds, 0x20, 0, 5, 4, 0x3);
1751
1752 if (lc_on)
1753 rtl9300_sds_field_w(lane_0, 0x20, 18, 11, 8, lc_value);
1754 else
1755 rtl9300_sds_field_w(lane_0, 0x20, 18, 15, 12, lc_value);
1756
1757 /* Force analog LC & ring on */
1758 rtl9300_sds_field_w(lane_0, 0x21, 11, 3, 0, 0xf);
1759
1760 v = lc_on ? 0x3 : 0x1;
1761
1762 if (sds == lane_0)
1763 rtl9300_sds_field_w(lane_0, 0x20, 18, 5, 4, v);
1764 else
1765 rtl9300_sds_field_w(lane_0, 0x20, 18, 7, 6, v);
1766
1767 /* Force SerDes mode */
1768 rtl9300_sds_field_w(sds, 0x1f, 9, 6, 6, 1);
1769 rtl9300_sds_field_w(sds, 0x1f, 9, 11, 7, sds_mode);
1770
1771 /* Toggle LC or Ring */
1772 for (int i = 0; i < 20; i++) {
1773 u32 cr_0, cr_1, cr_2;
1774 u32 m_bit, l_bit;
1775
1776 mdelay(200);
1777
1778 rtl930x_write_sds_phy(lane_0, 0x1f, 2, 53);
1779
1780 m_bit = (lane_0 == sds) ? (4) : (5);
1781 l_bit = (lane_0 == sds) ? (4) : (5);
1782
1783 cr_0 = rtl9300_sds_field_r(lane_0, 0x1f, 20, m_bit, l_bit);
1784 mdelay(10);
1785 cr_1 = rtl9300_sds_field_r(lane_0, 0x1f, 20, m_bit, l_bit);
1786 mdelay(10);
1787 cr_2 = rtl9300_sds_field_r(lane_0, 0x1f, 20, m_bit, l_bit);
1788
1789 if (cr_0 && cr_1 && cr_2) {
1790 u32 t;
1791
1792 if (phy_if != PHY_INTERFACE_MODE_10GBASER)
1793 break;
1794
1795 t = rtl9300_sds_field_r(sds, 0x6, 0x1, 2, 2);
1796 rtl9300_sds_field_w(sds, 0x6, 0x1, 2, 2, 0x1);
1797
1798 /* Reset FSM */
1799 rtl9300_sds_field_w(sds, 0x6, 0x2, 12, 12, 0x1);
1800 mdelay(10);
1801 rtl9300_sds_field_w(sds, 0x6, 0x2, 12, 12, 0x0);
1802 mdelay(10);
1803
1804 /* Need to read this twice */
1805 v = rtl9300_sds_field_r(sds, 0x5, 0, 12, 12);
1806 v = rtl9300_sds_field_r(sds, 0x5, 0, 12, 12);
1807
1808 rtl9300_sds_field_w(sds, 0x6, 0x1, 2, 2, t);
1809
1810 /* Reset FSM again */
1811 rtl9300_sds_field_w(sds, 0x6, 0x2, 12, 12, 0x1);
1812 mdelay(10);
1813 rtl9300_sds_field_w(sds, 0x6, 0x2, 12, 12, 0x0);
1814 mdelay(10);
1815
1816 if (v == 1)
1817 break;
1818 }
1819
1820 m_bit = (phy_if == PHY_INTERFACE_MODE_10GBASER) ? 3 : 1;
1821 l_bit = (phy_if == PHY_INTERFACE_MODE_10GBASER) ? 2 : 0;
1822
1823 rtl9300_sds_field_w(lane_0, 0x21, 11, m_bit, l_bit, 0x2);
1824 mdelay(10);
1825 rtl9300_sds_field_w(lane_0, 0x21, 11, m_bit, l_bit, 0x3);
1826 }
1827
1828 rtl930x_sds_rx_rst(sds, phy_if);
1829
1830 /* Re-enable power */
1831 rtl9300_sds_field_w(sds, 0x20, 0, 7, 6, 0);
1832
1833 pr_info("%s --------------------- serdes %d forced to %x DONE\n", __func__, sds, sds_mode);
1834 }
1835
1836 void rtl9300_sds_tx_config(int sds, phy_interface_t phy_if)
1837 {
1838 /* parameters: rtl9303_80G_txParam_s2 */
1839 int impedance = 0x8;
1840 int pre_amp = 0x2;
1841 int main_amp = 0x9;
1842 int post_amp = 0x2;
1843 int pre_en = 0x1;
1844 int post_en = 0x1;
1845 int page;
1846
1847 switch(phy_if) {
1848 case PHY_INTERFACE_MODE_1000BASEX:
1849 page = 0x25;
1850 break;
1851 case PHY_INTERFACE_MODE_HSGMII:
1852 case PHY_INTERFACE_MODE_2500BASEX:
1853 page = 0x29;
1854 break;
1855 case PHY_INTERFACE_MODE_10GBASER:
1856 page = 0x2f;
1857 break;
1858 default:
1859 pr_err("%s: unsupported PHY mode\n", __func__);
1860 return;
1861 }
1862
1863 rtl9300_sds_field_w(sds, page, 0x01, 15, 11, pre_amp);
1864 rtl9300_sds_field_w(sds, page, 0x06, 4, 0, post_amp);
1865 rtl9300_sds_field_w(sds, page, 0x07, 0, 0, pre_en);
1866 rtl9300_sds_field_w(sds, page, 0x07, 3, 3, post_en);
1867 rtl9300_sds_field_w(sds, page, 0x07, 8, 4, main_amp);
1868 rtl9300_sds_field_w(sds, page, 0x18, 15, 12, impedance);
1869 }
1870
1871 /* Wait for clock ready, this assumes the SerDes is in XGMII mode
1872 * timeout is in ms
1873 */
1874 int rtl9300_sds_clock_wait(int timeout)
1875 {
1876 u32 v;
1877 unsigned long start = jiffies;
1878
1879 do {
1880 rtl9300_sds_field_w(2, 0x1f, 0x2, 15, 0, 53);
1881 v = rtl9300_sds_field_r(2, 0x1f, 20, 5, 4);
1882 if (v == 3)
1883 return 0;
1884 } while (jiffies < start + (HZ / 1000) * timeout);
1885
1886 return 1;
1887 }
1888
1889 void rtl9300_serdes_mac_link_config(int sds, bool tx_normal, bool rx_normal)
1890 {
1891 u32 v10, v1;
1892
1893 v10 = rtl930x_read_sds_phy(sds, 6, 2); /* 10GBit, page 6, reg 2 */
1894 v1 = rtl930x_read_sds_phy(sds, 0, 0); /* 1GBit, page 0, reg 0 */
1895 pr_info("%s: registers before %08x %08x\n", __func__, v10, v1);
1896
1897 v10 &= ~(BIT(13) | BIT(14));
1898 v1 &= ~(BIT(8) | BIT(9));
1899
1900 v10 |= rx_normal ? 0 : BIT(13);
1901 v1 |= rx_normal ? 0 : BIT(9);
1902
1903 v10 |= tx_normal ? 0 : BIT(14);
1904 v1 |= tx_normal ? 0 : BIT(8);
1905
1906 rtl930x_write_sds_phy(sds, 6, 2, v10);
1907 rtl930x_write_sds_phy(sds, 0, 0, v1);
1908
1909 v10 = rtl930x_read_sds_phy(sds, 6, 2);
1910 v1 = rtl930x_read_sds_phy(sds, 0, 0);
1911 pr_info("%s: registers after %08x %08x\n", __func__, v10, v1);
1912 }
1913
1914 void rtl9300_sds_rxcal_dcvs_manual(u32 sds_num, u32 dcvs_id, bool manual, u32 dvcs_list[])
1915 {
1916 if (manual) {
1917 switch(dcvs_id) {
1918 case 0:
1919 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 14, 14, 0x1);
1920 rtl9300_sds_field_w(sds_num, 0x2f, 0x03, 5, 5, dvcs_list[0]);
1921 rtl9300_sds_field_w(sds_num, 0x2f, 0x03, 4, 0, dvcs_list[1]);
1922 break;
1923 case 1:
1924 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 13, 13, 0x1);
1925 rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 15, 15, dvcs_list[0]);
1926 rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 14, 11, dvcs_list[1]);
1927 break;
1928 case 2:
1929 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 12, 12, 0x1);
1930 rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 10, 10, dvcs_list[0]);
1931 rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 9, 6, dvcs_list[1]);
1932 break;
1933 case 3:
1934 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 11, 11, 0x1);
1935 rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 5, 5, dvcs_list[0]);
1936 rtl9300_sds_field_w(sds_num, 0x2e, 0x1d, 4, 1, dvcs_list[1]);
1937 break;
1938 case 4:
1939 rtl9300_sds_field_w(sds_num, 0x2e, 0x01, 15, 15, 0x1);
1940 rtl9300_sds_field_w(sds_num, 0x2e, 0x11, 10, 10, dvcs_list[0]);
1941 rtl9300_sds_field_w(sds_num, 0x2e, 0x11, 9, 6, dvcs_list[1]);
1942 break;
1943 case 5:
1944 rtl9300_sds_field_w(sds_num, 0x2e, 0x02, 11, 11, 0x1);
1945 rtl9300_sds_field_w(sds_num, 0x2e, 0x11, 4, 4, dvcs_list[0]);
1946 rtl9300_sds_field_w(sds_num, 0x2e, 0x11, 3, 0, dvcs_list[1]);
1947 break;
1948 default:
1949 break;
1950 }
1951 } else {
1952 switch(dcvs_id) {
1953 case 0:
1954 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 14, 14, 0x0);
1955 break;
1956 case 1:
1957 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 13, 13, 0x0);
1958 break;
1959 case 2:
1960 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 12, 12, 0x0);
1961 break;
1962 case 3:
1963 rtl9300_sds_field_w(sds_num, 0x2e, 0x1e, 11, 11, 0x0);
1964 break;
1965 case 4:
1966 rtl9300_sds_field_w(sds_num, 0x2e, 0x01, 15, 15, 0x0);
1967 break;
1968 case 5:
1969 rtl9300_sds_field_w(sds_num, 0x2e, 0x02, 11, 11, 0x0);
1970 break;
1971 default:
1972 break;
1973 }
1974 mdelay(1);
1975 }
1976 }
1977
1978 void rtl9300_sds_rxcal_dcvs_get(u32 sds_num, u32 dcvs_id, u32 dcvs_list[])
1979 {
1980 u32 dcvs_sign_out = 0, dcvs_coef_bin = 0;
1981 bool dcvs_manual;
1982
1983 if (!(sds_num % 2))
1984 rtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);
1985 else
1986 rtl930x_write_sds_phy(sds_num - 1, 0x1f, 0x2, 0x31);
1987
1988 /* ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1] */
1989 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1);
1990
1991 /* ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x] */
1992 rtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x20);
1993
1994 switch(dcvs_id) {
1995 case 0:
1996 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x22);
1997 mdelay(1);
1998
1999 /* ##DCVS0 Read Out */
2000 dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);
2001 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);
2002 dcvs_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x1e, 14, 14);
2003 break;
2004
2005 case 1:
2006 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x23);
2007 mdelay(1);
2008
2009 /* ##DCVS0 Read Out */
2010 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);
2011 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);
2012 dcvs_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x1e, 13, 13);
2013 break;
2014
2015 case 2:
2016 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x24);
2017 mdelay(1);
2018
2019 /* ##DCVS0 Read Out */
2020 dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);
2021 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);
2022 dcvs_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x1e, 12, 12);
2023 break;
2024 case 3:
2025 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x25);
2026 mdelay(1);
2027
2028 /* ##DCVS0 Read Out */
2029 dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);
2030 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);
2031 dcvs_manual = rtl9300_sds_field_r(sds_num, 0x2e, 0x1e, 11, 11);
2032 break;
2033
2034 case 4:
2035 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x2c);
2036 mdelay(1);
2037
2038 /* ##DCVS0 Read Out */
2039 dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);
2040 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);
2041 dcvs_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x01, 15, 15);
2042 break;
2043
2044 case 5:
2045 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0x2d);
2046 mdelay(1);
2047
2048 /* ##DCVS0 Read Out */
2049 dcvs_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 4);
2050 dcvs_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 3, 0);
2051 dcvs_manual = rtl9300_sds_field_r(sds_num, 0x2e, 0x02, 11, 11);
2052 break;
2053
2054 default:
2055 break;
2056 }
2057
2058 if (dcvs_sign_out)
2059 pr_info("%s DCVS %u Sign: -", __func__, dcvs_id);
2060 else
2061 pr_info("%s DCVS %u Sign: +", __func__, dcvs_id);
2062
2063 pr_info("DCVS %u even coefficient = %u", dcvs_id, dcvs_coef_bin);
2064 pr_info("DCVS %u manual = %u", dcvs_id, dcvs_manual);
2065
2066 dcvs_list[0] = dcvs_sign_out;
2067 dcvs_list[1] = dcvs_coef_bin;
2068 }
2069
2070 void rtl9300_sds_rxcal_leq_manual(u32 sds_num, bool manual, u32 leq_gray)
2071 {
2072 if (manual) {
2073 rtl9300_sds_field_w(sds_num, 0x2e, 0x18, 15, 15, 0x1);
2074 rtl9300_sds_field_w(sds_num, 0x2e, 0x16, 14, 10, leq_gray);
2075 } else {
2076 rtl9300_sds_field_w(sds_num, 0x2e, 0x18, 15, 15, 0x0);
2077 mdelay(100);
2078 }
2079 }
2080
2081 void rtl9300_sds_rxcal_leq_offset_manual(u32 sds_num, bool manual, u32 offset)
2082 {
2083 if (manual) {
2084 rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 6, 2, offset);
2085 } else {
2086 rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 6, 2, offset);
2087 mdelay(1);
2088 }
2089 }
2090
2091 #define GRAY_BITS 5
2092 u32 rtl9300_sds_rxcal_gray_to_binary(u32 gray_code)
2093 {
2094 int i, j, m;
2095 u32 g[GRAY_BITS];
2096 u32 c[GRAY_BITS];
2097 u32 leq_binary = 0;
2098
2099 for(i = 0; i < GRAY_BITS; i++)
2100 g[i] = (gray_code & BIT(i)) >> i;
2101
2102 m = GRAY_BITS - 1;
2103
2104 c[m] = g[m];
2105
2106 for(i = 0; i < m; i++) {
2107 c[i] = g[i];
2108 for(j = i + 1; j < GRAY_BITS; j++)
2109 c[i] = c[i] ^ g[j];
2110 }
2111
2112 for(i = 0; i < GRAY_BITS; i++)
2113 leq_binary += c[i] << i;
2114
2115 return leq_binary;
2116 }
2117
2118 u32 rtl9300_sds_rxcal_leq_read(int sds_num)
2119 {
2120 u32 leq_gray, leq_bin;
2121 bool leq_manual;
2122
2123 if (!(sds_num % 2))
2124 rtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);
2125 else
2126 rtl930x_write_sds_phy(sds_num - 1, 0x1f, 0x2, 0x31);
2127
2128 /* ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1] */
2129 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1);
2130
2131 /* ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[0 1 x x x x] */
2132 rtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x10);
2133 mdelay(1);
2134
2135 /* ##LEQ Read Out */
2136 leq_gray = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 7, 3);
2137 leq_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x18, 15, 15);
2138 leq_bin = rtl9300_sds_rxcal_gray_to_binary(leq_gray);
2139
2140 pr_info("LEQ_gray: %u, LEQ_bin: %u", leq_gray, leq_bin);
2141 pr_info("LEQ manual: %u", leq_manual);
2142
2143 return leq_bin;
2144 }
2145
2146 void rtl9300_sds_rxcal_vth_manual(u32 sds_num, bool manual, u32 vth_list[])
2147 {
2148 if (manual) {
2149 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, 13, 13, 0x1);
2150 rtl9300_sds_field_w(sds_num, 0x2e, 0x13, 5, 3, vth_list[0]);
2151 rtl9300_sds_field_w(sds_num, 0x2e, 0x13, 2, 0, vth_list[1]);
2152 } else {
2153 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, 13, 13, 0x0);
2154 mdelay(10);
2155 }
2156 }
2157
2158 void rtl9300_sds_rxcal_vth_get(u32 sds_num, u32 vth_list[])
2159 {
2160 u32 vth_manual;
2161
2162 /* ##Page0x1F, Reg0x02[15 0], REG_DBGO_SEL=[0x002F]; */ /* Lane0 */
2163 /* ##Page0x1F, Reg0x02[15 0], REG_DBGO_SEL=[0x0031]; */ /* Lane1 */
2164 if (!(sds_num % 2))
2165 rtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);
2166 else
2167 rtl930x_write_sds_phy(sds_num - 1, 0x1f, 0x2, 0x31);
2168
2169 /* ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1] */
2170 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1);
2171 /* ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x] */
2172 rtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x20);
2173 /* ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 1 1 0 0] */
2174 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0xc);
2175
2176 mdelay(1);
2177
2178 /* ##VthP & VthN Read Out */
2179 vth_list[0] = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 2, 0); /* v_thp set bin */
2180 vth_list[1] = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 3); /* v_thn set bin */
2181
2182 pr_info("vth_set_bin = %d", vth_list[0]);
2183 pr_info("vth_set_bin = %d", vth_list[1]);
2184
2185 vth_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x0f, 13, 13);
2186 pr_info("Vth Maunal = %d", vth_manual);
2187 }
2188
2189 void rtl9300_sds_rxcal_tap_manual(u32 sds_num, int tap_id, bool manual, u32 tap_list[])
2190 {
2191 if (manual) {
2192 switch(tap_id) {
2193 case 0:
2194 /* ##REG0_LOAD_IN_INIT[0]=1; REG0_TAP0_INIT[5:0]=Tap0_Value */
2195 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1);
2196 rtl9300_sds_field_w(sds_num, 0x2f, 0x03, 5, 5, tap_list[0]);
2197 rtl9300_sds_field_w(sds_num, 0x2f, 0x03, 4, 0, tap_list[1]);
2198 break;
2199 case 1:
2200 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1);
2201 rtl9300_sds_field_w(sds_num, 0x21, 0x07, 6, 6, tap_list[0]);
2202 rtl9300_sds_field_w(sds_num, 0x2e, 0x09, 11, 6, tap_list[1]);
2203 rtl9300_sds_field_w(sds_num, 0x21, 0x07, 5, 5, tap_list[2]);
2204 rtl9300_sds_field_w(sds_num, 0x2f, 0x12, 5, 0, tap_list[3]);
2205 break;
2206 case 2:
2207 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1);
2208 rtl9300_sds_field_w(sds_num, 0x2e, 0x09, 5, 5, tap_list[0]);
2209 rtl9300_sds_field_w(sds_num, 0x2e, 0x09, 4, 0, tap_list[1]);
2210 rtl9300_sds_field_w(sds_num, 0x2e, 0x0a, 11, 11, tap_list[2]);
2211 rtl9300_sds_field_w(sds_num, 0x2e, 0x0a, 10, 6, tap_list[3]);
2212 break;
2213 case 3:
2214 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1);
2215 rtl9300_sds_field_w(sds_num, 0x2e, 0x0a, 5, 5, tap_list[0]);
2216 rtl9300_sds_field_w(sds_num, 0x2e, 0x0a, 4, 0, tap_list[1]);
2217 rtl9300_sds_field_w(sds_num, 0x2e, 0x06, 5, 5, tap_list[2]);
2218 rtl9300_sds_field_w(sds_num, 0x2e, 0x06, 4, 0, tap_list[3]);
2219 break;
2220 case 4:
2221 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x1);
2222 rtl9300_sds_field_w(sds_num, 0x2f, 0x01, 5, 5, tap_list[0]);
2223 rtl9300_sds_field_w(sds_num, 0x2f, 0x01, 4, 0, tap_list[1]);
2224 rtl9300_sds_field_w(sds_num, 0x2e, 0x06, 11, 11, tap_list[2]);
2225 rtl9300_sds_field_w(sds_num, 0x2e, 0x06, 10, 6, tap_list[3]);
2226 break;
2227 default:
2228 break;
2229 }
2230 } else {
2231 rtl9300_sds_field_w(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7, 0x0);
2232 mdelay(10);
2233 }
2234 }
2235
2236 void rtl9300_sds_rxcal_tap_get(u32 sds_num, u32 tap_id, u32 tap_list[])
2237 {
2238 u32 tap0_sign_out;
2239 u32 tap0_coef_bin;
2240 u32 tap_sign_out_even;
2241 u32 tap_coef_bin_even;
2242 u32 tap_sign_out_odd;
2243 u32 tap_coef_bin_odd;
2244 bool tap_manual;
2245
2246 if (!(sds_num % 2))
2247 rtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);
2248 else
2249 rtl930x_write_sds_phy(sds_num - 1, 0x1f, 0x2, 0x31);
2250
2251 /* ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1] */
2252 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1);
2253 /* ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x] */
2254 rtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x20);
2255
2256 if (!tap_id) {
2257 /* ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 0 0 0 1] */
2258 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0);
2259 /* ##Tap1 Even Read Out */
2260 mdelay(1);
2261 tap0_sign_out = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 5);
2262 tap0_coef_bin = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 0);
2263
2264 if (tap0_sign_out == 1)
2265 pr_info("Tap0 Sign : -");
2266 else
2267 pr_info("Tap0 Sign : +");
2268
2269 pr_info("tap0_coef_bin = %d", tap0_coef_bin);
2270
2271 tap_list[0] = tap0_sign_out;
2272 tap_list[1] = tap0_coef_bin;
2273
2274 tap_manual = !!rtl9300_sds_field_r(sds_num, 0x2e, 0x0f, 7, 7);
2275 pr_info("tap0 manual = %u",tap_manual);
2276 } else {
2277 /* ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 0 0 0 1] */
2278 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, tap_id);
2279 mdelay(1);
2280 /* ##Tap1 Even Read Out */
2281 tap_sign_out_even = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 5);
2282 tap_coef_bin_even = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 0);
2283
2284 /* ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 0 1 1 0] */
2285 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, (tap_id + 5));
2286 /* ##Tap1 Odd Read Out */
2287 tap_sign_out_odd = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 5);
2288 tap_coef_bin_odd = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 4, 0);
2289
2290 if (tap_sign_out_even == 1)
2291 pr_info("Tap %u even sign: -", tap_id);
2292 else
2293 pr_info("Tap %u even sign: +", tap_id);
2294
2295 pr_info("Tap %u even coefficient = %u", tap_id, tap_coef_bin_even);
2296
2297 if (tap_sign_out_odd == 1)
2298 pr_info("Tap %u odd sign: -", tap_id);
2299 else
2300 pr_info("Tap %u odd sign: +", tap_id);
2301
2302 pr_info("Tap %u odd coefficient = %u", tap_id,tap_coef_bin_odd);
2303
2304 tap_list[0] = tap_sign_out_even;
2305 tap_list[1] = tap_coef_bin_even;
2306 tap_list[2] = tap_sign_out_odd;
2307 tap_list[3] = tap_coef_bin_odd;
2308
2309 tap_manual = rtl9300_sds_field_r(sds_num, 0x2e, 0x0f, tap_id + 7, tap_id + 7);
2310 pr_info("tap %u manual = %d",tap_id, tap_manual);
2311 }
2312 }
2313
2314 void rtl9300_do_rx_calibration_1(int sds, phy_interface_t phy_mode)
2315 {
2316 /* From both rtl9300_rxCaliConf_serdes_myParam and rtl9300_rxCaliConf_phy_myParam */
2317 int tap0_init_val = 0x1f; /* Initial Decision Fed Equalizer 0 tap */
2318 int vth_min = 0x0;
2319
2320 pr_info("start_1.1.1 initial value for sds %d\n", sds);
2321 rtl930x_write_sds_phy(sds, 6, 0, 0);
2322
2323 /* FGCAL */
2324 rtl9300_sds_field_w(sds, 0x2e, 0x01, 14, 14, 0x00);
2325 rtl9300_sds_field_w(sds, 0x2e, 0x1c, 10, 5, 0x20);
2326 rtl9300_sds_field_w(sds, 0x2f, 0x02, 0, 0, 0x01);
2327
2328 /* DCVS */
2329 rtl9300_sds_field_w(sds, 0x2e, 0x1e, 14, 11, 0x00);
2330 rtl9300_sds_field_w(sds, 0x2e, 0x01, 15, 15, 0x00);
2331 rtl9300_sds_field_w(sds, 0x2e, 0x02, 11, 11, 0x00);
2332 rtl9300_sds_field_w(sds, 0x2e, 0x1c, 4, 0, 0x00);
2333 rtl9300_sds_field_w(sds, 0x2e, 0x1d, 15, 11, 0x00);
2334 rtl9300_sds_field_w(sds, 0x2e, 0x1d, 10, 6, 0x00);
2335 rtl9300_sds_field_w(sds, 0x2e, 0x1d, 5, 1, 0x00);
2336 rtl9300_sds_field_w(sds, 0x2e, 0x02, 10, 6, 0x00);
2337 rtl9300_sds_field_w(sds, 0x2e, 0x11, 4, 0, 0x00);
2338 rtl9300_sds_field_w(sds, 0x2f, 0x00, 3, 0, 0x0f);
2339 rtl9300_sds_field_w(sds, 0x2e, 0x04, 6, 6, 0x01);
2340 rtl9300_sds_field_w(sds, 0x2e, 0x04, 7, 7, 0x01);
2341
2342 /* LEQ (Long Term Equivalent signal level) */
2343 rtl9300_sds_field_w(sds, 0x2e, 0x16, 14, 8, 0x00);
2344
2345 /* DFE (Decision Fed Equalizer) */
2346 rtl9300_sds_field_w(sds, 0x2f, 0x03, 5, 0, tap0_init_val);
2347 rtl9300_sds_field_w(sds, 0x2e, 0x09, 11, 6, 0x00);
2348 rtl9300_sds_field_w(sds, 0x2e, 0x09, 5, 0, 0x00);
2349 rtl9300_sds_field_w(sds, 0x2e, 0x0a, 5, 0, 0x00);
2350 rtl9300_sds_field_w(sds, 0x2f, 0x01, 5, 0, 0x00);
2351 rtl9300_sds_field_w(sds, 0x2f, 0x12, 5, 0, 0x00);
2352 rtl9300_sds_field_w(sds, 0x2e, 0x0a, 11, 6, 0x00);
2353 rtl9300_sds_field_w(sds, 0x2e, 0x06, 5, 0, 0x00);
2354 rtl9300_sds_field_w(sds, 0x2f, 0x01, 5, 0, 0x00);
2355
2356 /* Vth */
2357 rtl9300_sds_field_w(sds, 0x2e, 0x13, 5, 3, 0x07);
2358 rtl9300_sds_field_w(sds, 0x2e, 0x13, 2, 0, 0x07);
2359 rtl9300_sds_field_w(sds, 0x2f, 0x0b, 5, 3, vth_min);
2360
2361 pr_info("end_1.1.1 --\n");
2362
2363 pr_info("start_1.1.2 Load DFE init. value\n");
2364
2365 rtl9300_sds_field_w(sds, 0x2e, 0x0f, 13, 7, 0x7f);
2366
2367 pr_info("end_1.1.2\n");
2368
2369 pr_info("start_1.1.3 disable LEQ training,enable DFE clock\n");
2370
2371 rtl9300_sds_field_w(sds, 0x2e, 0x17, 7, 7, 0x00);
2372 rtl9300_sds_field_w(sds, 0x2e, 0x17, 6, 2, 0x00);
2373 rtl9300_sds_field_w(sds, 0x2e, 0x0c, 8, 8, 0x00);
2374 rtl9300_sds_field_w(sds, 0x2e, 0x0b, 4, 4, 0x01);
2375 rtl9300_sds_field_w(sds, 0x2e, 0x12, 14, 14, 0x00);
2376 rtl9300_sds_field_w(sds, 0x2f, 0x02, 15, 15, 0x00);
2377
2378 pr_info("end_1.1.3 --\n");
2379
2380 pr_info("start_1.1.4 offset cali setting\n");
2381
2382 rtl9300_sds_field_w(sds, 0x2e, 0x0f, 15, 14, 0x03);
2383
2384 pr_info("end_1.1.4\n");
2385
2386 pr_info("start_1.1.5 LEQ and DFE setting\n");
2387
2388 /* TODO: make this work for DAC cables of different lengths */
2389 /* For a 10GBit serdes wit Fibre, SDS 8 or 9 */
2390 if (phy_mode == PHY_INTERFACE_MODE_10GBASER || PHY_INTERFACE_MODE_1000BASEX)
2391 rtl9300_sds_field_w(sds, 0x2e, 0x16, 3, 2, 0x02);
2392 else
2393 pr_err("%s not PHY-based or SerDes, implement DAC!\n", __func__);
2394
2395 /* No serdes, check for Aquantia PHYs */
2396 rtl9300_sds_field_w(sds, 0x2e, 0x16, 3, 2, 0x02);
2397
2398 rtl9300_sds_field_w(sds, 0x2e, 0x0f, 6, 0, 0x5f);
2399 rtl9300_sds_field_w(sds, 0x2f, 0x05, 7, 2, 0x1f);
2400 rtl9300_sds_field_w(sds, 0x2e, 0x19, 9, 5, 0x1f);
2401 rtl9300_sds_field_w(sds, 0x2f, 0x0b, 15, 9, 0x3c);
2402 rtl9300_sds_field_w(sds, 0x2e, 0x0b, 1, 0, 0x03);
2403
2404 pr_info("end_1.1.5\n");
2405 }
2406
2407 void rtl9300_do_rx_calibration_2_1(u32 sds_num)
2408 {
2409 pr_info("start_1.2.1 ForegroundOffsetCal_Manual\n");
2410
2411 /* Gray config endis to 1 */
2412 rtl9300_sds_field_w(sds_num, 0x2f, 0x02, 2, 2, 0x01);
2413
2414 /* ForegroundOffsetCal_Manual(auto mode) */
2415 rtl9300_sds_field_w(sds_num, 0x2e, 0x01, 14, 14, 0x00);
2416
2417 pr_info("end_1.2.1");
2418 }
2419
2420 void rtl9300_do_rx_calibration_2_2(int sds_num)
2421 {
2422 /* Force Rx-Run = 0 */
2423 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 8, 8, 0x0);
2424
2425 rtl930x_sds_rx_rst(sds_num, PHY_INTERFACE_MODE_10GBASER);
2426 }
2427
2428 void rtl9300_do_rx_calibration_2_3(int sds_num)
2429 {
2430 u32 fgcal_binary, fgcal_gray;
2431 u32 offset_range;
2432
2433 pr_info("start_1.2.3 Foreground Calibration\n");
2434
2435 while(1) {
2436 if (!(sds_num % 2))
2437 rtl930x_write_sds_phy(sds_num, 0x1f, 0x2, 0x2f);
2438 else
2439 rtl930x_write_sds_phy(sds_num -1 , 0x1f, 0x2, 0x31);
2440
2441 /* ##Page0x2E, Reg0x15[9], REG0_RX_EN_TEST=[1] */
2442 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 9, 9, 0x1);
2443 /* ##Page0x21, Reg0x06[11 6], REG0_RX_DEBUG_SEL=[1 0 x x x x] */
2444 rtl9300_sds_field_w(sds_num, 0x21, 0x06, 11, 6, 0x20);
2445 /* ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 1 1 1 1] */
2446 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0xf);
2447 /* ##FGCAL read gray */
2448 fgcal_gray = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 0);
2449 /* ##Page0x2F, Reg0x0C[5 0], REG0_COEF_SEL=[0 0 1 1 1 0] */
2450 rtl9300_sds_field_w(sds_num, 0x2f, 0x0c, 5, 0, 0xe);
2451 /* ##FGCAL read binary */
2452 fgcal_binary = rtl9300_sds_field_r(sds_num, 0x1f, 0x14, 5, 0);
2453
2454 pr_info("%s: fgcal_gray: %d, fgcal_binary %d\n",
2455 __func__, fgcal_gray, fgcal_binary);
2456
2457 offset_range = rtl9300_sds_field_r(sds_num, 0x2e, 0x15, 15, 14);
2458
2459 if (fgcal_binary > 60 || fgcal_binary < 3) {
2460 if (offset_range == 3) {
2461 pr_info("%s: Foreground Calibration result marginal!", __func__);
2462 break;
2463 } else {
2464 offset_range++;
2465 rtl9300_sds_field_w(sds_num, 0x2e, 0x15, 15, 14, offset_range);
2466 rtl9300_do_rx_calibration_2_2(sds_num);
2467 }
2468 } else {
2469 break;
2470 }
2471 }
2472 pr_info("%s: end_1.2.3\n", __func__);
2473 }
2474
2475 void rtl9300_do_rx_calibration_2(int sds)
2476 {
2477 rtl930x_sds_rx_rst(sds, PHY_INTERFACE_MODE_10GBASER);
2478 rtl9300_do_rx_calibration_2_1(sds);
2479 rtl9300_do_rx_calibration_2_2(sds);
2480 rtl9300_do_rx_calibration_2_3(sds);
2481 }
2482
2483 void rtl9300_sds_rxcal_3_1(int sds_num, phy_interface_t phy_mode)
2484 {
2485 pr_info("start_1.3.1");
2486
2487 /* ##1.3.1 */
2488 if (phy_mode != PHY_INTERFACE_MODE_10GBASER && phy_mode != PHY_INTERFACE_MODE_1000BASEX)
2489 rtl9300_sds_field_w(sds_num, 0x2e, 0xc, 8, 8, 0);
2490
2491 rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 7, 7, 0x0);
2492 rtl9300_sds_rxcal_leq_manual(sds_num, false, 0);
2493
2494 pr_info("end_1.3.1");
2495 }
2496
2497 void rtl9300_sds_rxcal_3_2(int sds_num, phy_interface_t phy_mode)
2498 {
2499 u32 sum10 = 0, avg10, int10;
2500 int dac_long_cable_offset;
2501 bool eq_hold_enabled;
2502 int i;
2503
2504 if (phy_mode == PHY_INTERFACE_MODE_10GBASER || phy_mode == PHY_INTERFACE_MODE_1000BASEX) {
2505 /* rtl9300_rxCaliConf_serdes_myParam */
2506 dac_long_cable_offset = 3;
2507 eq_hold_enabled = true;
2508 } else {
2509 /* rtl9300_rxCaliConf_phy_myParam */
2510 dac_long_cable_offset = 0;
2511 eq_hold_enabled = false;
2512 }
2513
2514 if (phy_mode == PHY_INTERFACE_MODE_1000BASEX)
2515 pr_warn("%s: LEQ only valid for 10GR!\n", __func__);
2516
2517 pr_info("start_1.3.2");
2518
2519 for(i = 0; i < 10; i++) {
2520 sum10 += rtl9300_sds_rxcal_leq_read(sds_num);
2521 mdelay(10);
2522 }
2523
2524 avg10 = (sum10 / 10) + (((sum10 % 10) >= 5) ? 1 : 0);
2525 int10 = sum10 / 10;
2526
2527 pr_info("sum10:%u, avg10:%u, int10:%u", sum10, avg10, int10);
2528
2529 if (phy_mode == PHY_INTERFACE_MODE_10GBASER || phy_mode == PHY_INTERFACE_MODE_1000BASEX) {
2530 if (dac_long_cable_offset) {
2531 rtl9300_sds_rxcal_leq_offset_manual(sds_num, 1, dac_long_cable_offset);
2532 rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 7, 7, eq_hold_enabled);
2533 if (phy_mode == PHY_INTERFACE_MODE_10GBASER)
2534 rtl9300_sds_rxcal_leq_manual(sds_num, true, avg10);
2535 } else {
2536 if (sum10 >= 5) {
2537 rtl9300_sds_rxcal_leq_offset_manual(sds_num, 1, 3);
2538 rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 7, 7, 0x1);
2539 if (phy_mode == PHY_INTERFACE_MODE_10GBASER)
2540 rtl9300_sds_rxcal_leq_manual(sds_num, true, avg10);
2541 } else {
2542 rtl9300_sds_rxcal_leq_offset_manual(sds_num, 1, 0);
2543 rtl9300_sds_field_w(sds_num, 0x2e, 0x17, 7, 7, 0x1);
2544 if (phy_mode == PHY_INTERFACE_MODE_10GBASER)
2545 rtl9300_sds_rxcal_leq_manual(sds_num, true, avg10);
2546 }
2547 }
2548 }
2549
2550 pr_info("Sds:%u LEQ = %u",sds_num, rtl9300_sds_rxcal_leq_read(sds_num));
2551
2552 pr_info("end_1.3.2");
2553 }
2554
2555 void rtl9300_do_rx_calibration_3(int sds_num, phy_interface_t phy_mode)
2556 {
2557 rtl9300_sds_rxcal_3_1(sds_num, phy_mode);
2558
2559 if (phy_mode == PHY_INTERFACE_MODE_10GBASER || phy_mode == PHY_INTERFACE_MODE_1000BASEX)
2560 rtl9300_sds_rxcal_3_2(sds_num, phy_mode);
2561 }
2562
2563 void rtl9300_do_rx_calibration_4_1(int sds_num)
2564 {
2565 u32 vth_list[2] = {0, 0};
2566 u32 tap0_list[4] = {0, 0, 0, 0};
2567
2568 pr_info("start_1.4.1");
2569
2570 /* ##1.4.1 */
2571 rtl9300_sds_rxcal_vth_manual(sds_num, false, vth_list);
2572 rtl9300_sds_rxcal_tap_manual(sds_num, 0, false, tap0_list);
2573 mdelay(200);
2574
2575 pr_info("end_1.4.1");
2576 }
2577
2578 void rtl9300_do_rx_calibration_4_2(u32 sds_num)
2579 {
2580 u32 vth_list[2];
2581 u32 tap_list[4];
2582
2583 pr_info("start_1.4.2");
2584
2585 rtl9300_sds_rxcal_vth_get(sds_num, vth_list);
2586 rtl9300_sds_rxcal_vth_manual(sds_num, true, vth_list);
2587
2588 mdelay(100);
2589
2590 rtl9300_sds_rxcal_tap_get(sds_num, 0, tap_list);
2591 rtl9300_sds_rxcal_tap_manual(sds_num, 0, true, tap_list);
2592
2593 pr_info("end_1.4.2");
2594 }
2595
2596 void rtl9300_do_rx_calibration_4(u32 sds_num)
2597 {
2598 rtl9300_do_rx_calibration_4_1(sds_num);
2599 rtl9300_do_rx_calibration_4_2(sds_num);
2600 }
2601
2602 void rtl9300_do_rx_calibration_5_2(u32 sds_num)
2603 {
2604 u32 tap1_list[4] = {0};
2605 u32 tap2_list[4] = {0};
2606 u32 tap3_list[4] = {0};
2607 u32 tap4_list[4] = {0};
2608
2609 pr_info("start_1.5.2");
2610
2611 rtl9300_sds_rxcal_tap_manual(sds_num, 1, false, tap1_list);
2612 rtl9300_sds_rxcal_tap_manual(sds_num, 2, false, tap2_list);
2613 rtl9300_sds_rxcal_tap_manual(sds_num, 3, false, tap3_list);
2614 rtl9300_sds_rxcal_tap_manual(sds_num, 4, false, tap4_list);
2615
2616 mdelay(30);
2617
2618 pr_info("end_1.5.2");
2619 }
2620
2621 void rtl9300_do_rx_calibration_5(u32 sds_num, phy_interface_t phy_mode)
2622 {
2623 if (phy_mode == PHY_INTERFACE_MODE_10GBASER) /* dfeTap1_4Enable true */
2624 rtl9300_do_rx_calibration_5_2(sds_num);
2625 }
2626
2627
2628 void rtl9300_do_rx_calibration_dfe_disable(u32 sds_num)
2629 {
2630 u32 tap1_list[4] = {0};
2631 u32 tap2_list[4] = {0};
2632 u32 tap3_list[4] = {0};
2633 u32 tap4_list[4] = {0};
2634
2635 rtl9300_sds_rxcal_tap_manual(sds_num, 1, true, tap1_list);
2636 rtl9300_sds_rxcal_tap_manual(sds_num, 2, true, tap2_list);
2637 rtl9300_sds_rxcal_tap_manual(sds_num, 3, true, tap3_list);
2638 rtl9300_sds_rxcal_tap_manual(sds_num, 4, true, tap4_list);
2639
2640 mdelay(10);
2641 }
2642
2643 void rtl9300_do_rx_calibration(int sds, phy_interface_t phy_mode)
2644 {
2645 u32 latch_sts;
2646
2647 rtl9300_do_rx_calibration_1(sds, phy_mode);
2648 rtl9300_do_rx_calibration_2(sds);
2649 rtl9300_do_rx_calibration_4(sds);
2650 rtl9300_do_rx_calibration_5(sds, phy_mode);
2651 mdelay(20);
2652
2653 /* Do this only for 10GR mode, SDS active in mode 0x1a */
2654 if (rtl9300_sds_field_r(sds, 0x1f, 9, 11, 7) == 0x1a) {
2655 pr_info("%s: SDS enabled\n", __func__);
2656 latch_sts = rtl9300_sds_field_r(sds, 0x4, 1, 2, 2);
2657 mdelay(1);
2658 latch_sts = rtl9300_sds_field_r(sds, 0x4, 1, 2, 2);
2659 if (latch_sts) {
2660 rtl9300_do_rx_calibration_dfe_disable(sds);
2661 rtl9300_do_rx_calibration_4(sds);
2662 rtl9300_do_rx_calibration_5(sds, phy_mode);
2663 }
2664 }
2665 }
2666
2667 int rtl9300_sds_sym_err_reset(int sds_num, phy_interface_t phy_mode)
2668 {
2669 switch (phy_mode) {
2670 case PHY_INTERFACE_MODE_XGMII:
2671 break;
2672
2673 case PHY_INTERFACE_MODE_10GBASER:
2674 /* Read twice to clear */
2675 rtl930x_read_sds_phy(sds_num, 5, 1);
2676 rtl930x_read_sds_phy(sds_num, 5, 1);
2677 break;
2678
2679 case PHY_INTERFACE_MODE_1000BASEX:
2680 rtl9300_sds_field_w(sds_num, 0x1, 24, 2, 0, 0);
2681 rtl9300_sds_field_w(sds_num, 0x1, 3, 15, 8, 0);
2682 rtl9300_sds_field_w(sds_num, 0x1, 2, 15, 0, 0);
2683 break;
2684
2685 default:
2686 pr_info("%s unsupported phy mode\n", __func__);
2687 return -1;
2688 }
2689
2690 return 0;
2691 }
2692
2693 u32 rtl9300_sds_sym_err_get(int sds_num, phy_interface_t phy_mode)
2694 {
2695 u32 v = 0;
2696
2697 switch (phy_mode) {
2698 case PHY_INTERFACE_MODE_XGMII:
2699 break;
2700
2701 case PHY_INTERFACE_MODE_10GBASER:
2702 v = rtl930x_read_sds_phy(sds_num, 5, 1);
2703 return v & 0xff;
2704
2705 default:
2706 pr_info("%s unsupported PHY-mode\n", __func__);
2707 }
2708
2709 return v;
2710 }
2711
2712 int rtl9300_sds_check_calibration(int sds_num, phy_interface_t phy_mode)
2713 {
2714 u32 errors1, errors2;
2715
2716 rtl9300_sds_sym_err_reset(sds_num, phy_mode);
2717 rtl9300_sds_sym_err_reset(sds_num, phy_mode);
2718
2719 /* Count errors during 1ms */
2720 errors1 = rtl9300_sds_sym_err_get(sds_num, phy_mode);
2721 mdelay(1);
2722 errors2 = rtl9300_sds_sym_err_get(sds_num, phy_mode);
2723
2724 switch (phy_mode) {
2725 case PHY_INTERFACE_MODE_XGMII:
2726
2727 if ((errors2 - errors1 > 100) ||
2728 (errors1 >= 0xffff00) || (errors2 >= 0xffff00)) {
2729 pr_info("%s XSGMII error rate too high\n", __func__);
2730 return 1;
2731 }
2732 break;
2733 case PHY_INTERFACE_MODE_10GBASER:
2734 if (errors2 > 0) {
2735 pr_info("%s 10GBASER error rate too high\n", __func__);
2736 return 1;
2737 }
2738 break;
2739 default:
2740 return 1;
2741 }
2742
2743 return 0;
2744 }
2745
2746 void rtl9300_phy_enable_10g_1g(int sds_num)
2747 {
2748 u32 v;
2749
2750 /* Enable 1GBit PHY */
2751 v = rtl930x_read_sds_phy(sds_num, PHY_PAGE_2, MII_BMCR);
2752 pr_info("%s 1gbit phy: %08x\n", __func__, v);
2753 v &= ~BMCR_PDOWN;
2754 rtl930x_write_sds_phy(sds_num, PHY_PAGE_2, MII_BMCR, v);
2755 pr_info("%s 1gbit phy enabled: %08x\n", __func__, v);
2756
2757 /* Enable 10GBit PHY */
2758 v = rtl930x_read_sds_phy(sds_num, PHY_PAGE_4, MII_BMCR);
2759 pr_info("%s 10gbit phy: %08x\n", __func__, v);
2760 v &= ~BMCR_PDOWN;
2761 rtl930x_write_sds_phy(sds_num, PHY_PAGE_4, MII_BMCR, v);
2762 pr_info("%s 10gbit phy after: %08x\n", __func__, v);
2763
2764 /* dal_longan_construct_mac_default_10gmedia_fiber */
2765 v = rtl930x_read_sds_phy(sds_num, 0x1f, 11);
2766 pr_info("%s set medium: %08x\n", __func__, v);
2767 v |= BIT(1);
2768 rtl930x_write_sds_phy(sds_num, 0x1f, 11, v);
2769 pr_info("%s set medium after: %08x\n", __func__, v);
2770 }
2771
2772 #define RTL930X_MAC_FORCE_MODE_CTRL (0xCA1C)
2773 /* phy_mode = PHY_INTERFACE_MODE_10GBASER, sds_mode = 0x1a */
2774 int rtl9300_serdes_setup(int sds_num, phy_interface_t phy_mode)
2775 {
2776 int sds_mode;
2777 int calib_tries = 0;
2778
2779 switch (phy_mode) {
2780 case PHY_INTERFACE_MODE_HSGMII:
2781 sds_mode = 0x12;
2782 break;
2783 case PHY_INTERFACE_MODE_1000BASEX:
2784 sds_mode = 0x04;
2785 break;
2786 case PHY_INTERFACE_MODE_XGMII:
2787 sds_mode = 0x10;
2788 break;
2789 case PHY_INTERFACE_MODE_10GBASER:
2790 sds_mode = 0x1a;
2791 break;
2792 case PHY_INTERFACE_MODE_USXGMII:
2793 sds_mode = 0x0d;
2794 break;
2795 default:
2796 pr_err("%s: unknown serdes mode: %s\n", __func__, phy_modes(phy_mode));
2797 return -EINVAL;
2798 }
2799
2800 /* Maybe use dal_longan_sds_init */
2801
2802 /* dal_longan_construct_serdesConfig_init */ /* Serdes Construct */
2803 rtl9300_phy_enable_10g_1g(sds_num);
2804
2805 /* Set Serdes Mode */
2806 rtl9300_sds_set(sds_num, 0x1a); /* 0x1b: RTK_MII_10GR1000BX_AUTO */
2807
2808 /* Do RX calibration */
2809 do {
2810 rtl9300_do_rx_calibration(sds_num, phy_mode);
2811 calib_tries++;
2812 mdelay(50);
2813 } while (rtl9300_sds_check_calibration(sds_num, phy_mode) && calib_tries < 3);
2814
2815
2816 return 0;
2817 }
2818
2819 typedef struct {
2820 u8 page;
2821 u8 reg;
2822 u16 data;
2823 } sds_config;
2824
2825 sds_config rtl9300_a_sds_10gr_lane0[] =
2826 {
2827 /* 1G */
2828 {0x00, 0x0E, 0x3053}, {0x01, 0x14, 0x0100}, {0x21, 0x03, 0x8206},
2829 {0x21, 0x05, 0x40B0}, {0x21, 0x06, 0x0010}, {0x21, 0x07, 0xF09F},
2830 {0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009}, {0x21, 0x0E, 0x0000},
2831 {0x21, 0x0F, 0x0008}, {0x24, 0x00, 0x0668}, {0x24, 0x02, 0xD020},
2832 {0x24, 0x06, 0xC000}, {0x24, 0x0B, 0x1892}, {0x24, 0x0F, 0xFFDF},
2833 {0x24, 0x12, 0x03C4}, {0x24, 0x13, 0x027F}, {0x24, 0x14, 0x1311},
2834 {0x24, 0x16, 0x00C9}, {0x24, 0x17, 0xA100}, {0x24, 0x1A, 0x0001},
2835 {0x24, 0x1C, 0x0400}, {0x25, 0x01, 0x0300}, {0x25, 0x02, 0x1017},
2836 {0x25, 0x03, 0xFFDF}, {0x25, 0x05, 0x7F7C}, {0x25, 0x07, 0x8100},
2837 {0x25, 0x08, 0x0001}, {0x25, 0x09, 0xFFD4}, {0x25, 0x0A, 0x7C2F},
2838 {0x25, 0x0E, 0x003F}, {0x25, 0x0F, 0x0121}, {0x25, 0x10, 0x0020},
2839 {0x25, 0x11, 0x8840}, {0x2B, 0x13, 0x0050}, {0x2B, 0x18, 0x8E88},
2840 {0x2B, 0x19, 0x4902}, {0x2B, 0x1D, 0x2501}, {0x2D, 0x13, 0x0050},
2841 {0x2D, 0x18, 0x8E88}, {0x2D, 0x19, 0x4902}, {0x2D, 0x1D, 0x2641},
2842 {0x2F, 0x13, 0x0050}, {0x2F, 0x18, 0x8E88}, {0x2F, 0x19, 0x4902},
2843 {0x2F, 0x1D, 0x66E1},
2844 /* 3.125G */
2845 {0x28, 0x00, 0x0668}, {0x28, 0x02, 0xD020}, {0x28, 0x06, 0xC000},
2846 {0x28, 0x0B, 0x1892}, {0x28, 0x0F, 0xFFDF}, {0x28, 0x12, 0x01C4},
2847 {0x28, 0x13, 0x027F}, {0x28, 0x14, 0x1311}, {0x28, 0x16, 0x00C9},
2848 {0x28, 0x17, 0xA100}, {0x28, 0x1A, 0x0001}, {0x28, 0x1C, 0x0400},
2849 {0x29, 0x01, 0x0300}, {0x29, 0x02, 0x1017}, {0x29, 0x03, 0xFFDF},
2850 {0x29, 0x05, 0x7F7C}, {0x29, 0x07, 0x8100}, {0x29, 0x08, 0x0001},
2851 {0x29, 0x09, 0xFFD4}, {0x29, 0x0A, 0x7C2F}, {0x29, 0x0E, 0x003F},
2852 {0x29, 0x0F, 0x0121}, {0x29, 0x10, 0x0020}, {0x29, 0x11, 0x8840},
2853 /* 10G */
2854 {0x06, 0x0D, 0x0F00}, {0x06, 0x00, 0x0000}, {0x06, 0x01, 0xC800},
2855 {0x21, 0x03, 0x8206}, {0x21, 0x05, 0x40B0}, {0x21, 0x06, 0x0010},
2856 {0x21, 0x07, 0xF09F}, {0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009},
2857 {0x21, 0x0E, 0x0000}, {0x21, 0x0F, 0x0008}, {0x2E, 0x00, 0xA668},
2858 {0x2E, 0x02, 0xD020}, {0x2E, 0x06, 0xC000}, {0x2E, 0x0B, 0x1892},
2859 {0x2E, 0x0F, 0xFFDF}, {0x2E, 0x11, 0x8280}, {0x2E, 0x12, 0x0044},
2860 {0x2E, 0x13, 0x027F}, {0x2E, 0x14, 0x1311}, {0x2E, 0x17, 0xA100},
2861 {0x2E, 0x1A, 0x0001}, {0x2E, 0x1C, 0x0400}, {0x2F, 0x01, 0x0300},
2862 {0x2F, 0x02, 0x1217}, {0x2F, 0x03, 0xFFDF}, {0x2F, 0x05, 0x7F7C},
2863 {0x2F, 0x07, 0x80C4}, {0x2F, 0x08, 0x0001}, {0x2F, 0x09, 0xFFD4},
2864 {0x2F, 0x0A, 0x7C2F}, {0x2F, 0x0E, 0x003F}, {0x2F, 0x0F, 0x0121},
2865 {0x2F, 0x10, 0x0020}, {0x2F, 0x11, 0x8840}, {0x2F, 0x14, 0xE008},
2866 {0x2B, 0x13, 0x0050}, {0x2B, 0x18, 0x8E88}, {0x2B, 0x19, 0x4902},
2867 {0x2B, 0x1D, 0x2501}, {0x2D, 0x13, 0x0050}, {0x2D, 0x17, 0x4109},
2868 {0x2D, 0x18, 0x8E88}, {0x2D, 0x19, 0x4902}, {0x2D, 0x1C, 0x1109},
2869 {0x2D, 0x1D, 0x2641}, {0x2F, 0x13, 0x0050}, {0x2F, 0x18, 0x8E88},
2870 {0x2F, 0x19, 0x4902}, {0x2F, 0x1D, 0x76E1},
2871 };
2872
2873 sds_config rtl9300_a_sds_10gr_lane1[] =
2874 {
2875 /* 1G */
2876 {0x00, 0x0E, 0x3053}, {0x01, 0x14, 0x0100}, {0x21, 0x03, 0x8206},
2877 {0x21, 0x06, 0x0010}, {0x21, 0x07, 0xF09F}, {0x21, 0x0A, 0x0003},
2878 {0x21, 0x0B, 0x0005}, {0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009},
2879 {0x21, 0x0E, 0x0000}, {0x21, 0x0F, 0x0008}, {0x24, 0x00, 0x0668},
2880 {0x24, 0x02, 0xD020}, {0x24, 0x06, 0xC000}, {0x24, 0x0B, 0x1892},
2881 {0x24, 0x0F, 0xFFDF}, {0x24, 0x12, 0x03C4}, {0x24, 0x13, 0x027F},
2882 {0x24, 0x14, 0x1311}, {0x24, 0x16, 0x00C9}, {0x24, 0x17, 0xA100},
2883 {0x24, 0x1A, 0x0001}, {0x24, 0x1C, 0x0400}, {0x25, 0x00, 0x820F},
2884 {0x25, 0x01, 0x0300}, {0x25, 0x02, 0x1017}, {0x25, 0x03, 0xFFDF},
2885 {0x25, 0x05, 0x7F7C}, {0x25, 0x07, 0x8100}, {0x25, 0x08, 0x0001},
2886 {0x25, 0x09, 0xFFD4}, {0x25, 0x0A, 0x7C2F}, {0x25, 0x0E, 0x003F},
2887 {0x25, 0x0F, 0x0121}, {0x25, 0x10, 0x0020}, {0x25, 0x11, 0x8840},
2888 {0x2B, 0x13, 0x3D87}, {0x2B, 0x14, 0x3108}, {0x2D, 0x13, 0x3C87},
2889 {0x2D, 0x14, 0x1808},
2890 /* 3.125G */
2891 {0x28, 0x00, 0x0668}, {0x28, 0x02, 0xD020}, {0x28, 0x06, 0xC000},
2892 {0x28, 0x0B, 0x1892}, {0x28, 0x0F, 0xFFDF}, {0x28, 0x12, 0x01C4},
2893 {0x28, 0x13, 0x027F}, {0x28, 0x14, 0x1311}, {0x28, 0x16, 0x00C9},
2894 {0x28, 0x17, 0xA100}, {0x28, 0x1A, 0x0001}, {0x28, 0x1C, 0x0400},
2895 {0x29, 0x00, 0x820F}, {0x29, 0x01, 0x0300}, {0x29, 0x02, 0x1017},
2896 {0x29, 0x03, 0xFFDF}, {0x29, 0x05, 0x7F7C}, {0x29, 0x07, 0x8100},
2897 {0x29, 0x08, 0x0001}, {0x29, 0x0A, 0x7C2F}, {0x29, 0x0E, 0x003F},
2898 {0x29, 0x0F, 0x0121}, {0x29, 0x10, 0x0020}, {0x29, 0x11, 0x8840},
2899 /* 10G */
2900 {0x06, 0x0D, 0x0F00}, {0x06, 0x00, 0x0000}, {0x06, 0x01, 0xC800},
2901 {0x21, 0x03, 0x8206}, {0x21, 0x05, 0x40B0}, {0x21, 0x06, 0x0010},
2902 {0x21, 0x07, 0xF09F}, {0x21, 0x0A, 0x0003}, {0x21, 0x0B, 0x0005},
2903 {0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009}, {0x21, 0x0E, 0x0000},
2904 {0x21, 0x0F, 0x0008}, {0x2E, 0x00, 0xA668}, {0x2E, 0x02, 0xD020},
2905 {0x2E, 0x06, 0xC000}, {0x2E, 0x0B, 0x1892}, {0x2E, 0x0F, 0xFFDF},
2906 {0x2E, 0x11, 0x8280}, {0x2E, 0x12, 0x0044}, {0x2E, 0x13, 0x027F},
2907 {0x2E, 0x14, 0x1311}, {0x2E, 0x17, 0xA100}, {0x2E, 0x1A, 0x0001},
2908 {0x2E, 0x1C, 0x0400}, {0x2F, 0x00, 0x820F}, {0x2F, 0x01, 0x0300},
2909 {0x2F, 0x02, 0x1217}, {0x2F, 0x03, 0xFFDF}, {0x2F, 0x05, 0x7F7C},
2910 {0x2F, 0x07, 0x80C4}, {0x2F, 0x08, 0x0001}, {0x2F, 0x09, 0xFFD4},
2911 {0x2F, 0x0A, 0x7C2F}, {0x2F, 0x0E, 0x003F}, {0x2F, 0x0F, 0x0121},
2912 {0x2F, 0x10, 0x0020}, {0x2F, 0x11, 0x8840}, {0x2B, 0x13, 0x3D87},
2913 {0x2B, 0x14, 0x3108}, {0x2D, 0x13, 0x3C87}, {0x2D, 0x14, 0x1808},
2914 };
2915
2916 int rtl9300_sds_cmu_band_get(int sds)
2917 {
2918 u32 page;
2919 u32 en;
2920 u32 cmu_band;
2921
2922 /* page = rtl9300_sds_cmu_page_get(sds); */
2923 page = 0x25; /* 10GR and 1000BX */
2924 sds = (sds % 2) ? (sds - 1) : (sds);
2925
2926 rtl9300_sds_field_w(sds, page, 0x1c, 15, 15, 1);
2927 rtl9300_sds_field_w(sds + 1, page, 0x1c, 15, 15, 1);
2928
2929 en = rtl9300_sds_field_r(sds, page, 27, 1, 1);
2930 if(!en) { /* Auto mode */
2931 rtl930x_write_sds_phy(sds, 0x1f, 0x02, 31);
2932
2933 cmu_band = rtl9300_sds_field_r(sds, 0x1f, 0x15, 5, 1);
2934 } else {
2935 cmu_band = rtl9300_sds_field_r(sds, page, 30, 4, 0);
2936 }
2937
2938 return cmu_band;
2939 }
2940
2941 int rtl9300_configure_serdes(struct phy_device *phydev)
2942 {
2943 int phy_mode = PHY_INTERFACE_MODE_10GBASER;
2944 struct device *dev = &phydev->mdio.dev;
2945 int calib_tries = 0;
2946 u32 sds_num = 0;
2947 int sds_mode;
2948
2949 if (dev->of_node) {
2950 struct device_node *dn = dev->of_node;
2951 int phy_addr = phydev->mdio.addr;
2952
2953 if (of_property_read_u32(dn, "sds", &sds_num))
2954 sds_num = -1;
2955 pr_info("%s: Port %d, SerDes is %d\n", __func__, phy_addr, sds_num);
2956 } else {
2957 dev_err(dev, "No DT node.\n");
2958 return -EINVAL;
2959 }
2960
2961 if (sds_num < 0)
2962 return 0;
2963
2964 if (phy_mode != PHY_INTERFACE_MODE_10GBASER) /* TODO: for now we only patch 10GR SerDes */
2965 return 0;
2966
2967 switch (phy_mode) {
2968 case PHY_INTERFACE_MODE_HSGMII:
2969 sds_mode = 0x12;
2970 break;
2971 case PHY_INTERFACE_MODE_1000BASEX:
2972 sds_mode = 0x04;
2973 break;
2974 case PHY_INTERFACE_MODE_XGMII:
2975 sds_mode = 0x10;
2976 break;
2977 case PHY_INTERFACE_MODE_10GBASER:
2978 sds_mode = 0x1a;
2979 break;
2980 case PHY_INTERFACE_MODE_USXGMII:
2981 sds_mode = 0x0d;
2982 break;
2983 default:
2984 pr_err("%s: unknown serdes mode: %s\n", __func__, phy_modes(phy_mode));
2985 return -EINVAL;
2986 }
2987
2988 pr_info("%s CMU BAND is %d\n", __func__, rtl9300_sds_cmu_band_get(sds_num));
2989
2990 /* Turn Off Serdes */
2991 rtl9300_sds_rst(sds_num, 0x1f);
2992
2993 pr_info("%s PATCHING SerDes %d\n", __func__, sds_num);
2994 if (sds_num % 2) {
2995 for (int i = 0; i < sizeof(rtl9300_a_sds_10gr_lane1) / sizeof(sds_config); ++i) {
2996 rtl930x_write_sds_phy(sds_num, rtl9300_a_sds_10gr_lane1[i].page,
2997 rtl9300_a_sds_10gr_lane1[i].reg,
2998 rtl9300_a_sds_10gr_lane1[i].data);
2999 }
3000 } else {
3001 for (int i = 0; i < sizeof(rtl9300_a_sds_10gr_lane0) / sizeof(sds_config); ++i) {
3002 rtl930x_write_sds_phy(sds_num, rtl9300_a_sds_10gr_lane0[i].page,
3003 rtl9300_a_sds_10gr_lane0[i].reg,
3004 rtl9300_a_sds_10gr_lane0[i].data);
3005 }
3006 }
3007
3008 rtl9300_phy_enable_10g_1g(sds_num);
3009
3010 /* Disable MAC */
3011 sw_w32_mask(0, 1, RTL930X_MAC_FORCE_MODE_CTRL);
3012 mdelay(20);
3013
3014 /* ----> dal_longan_sds_mode_set */
3015 pr_info("%s: Configuring RTL9300 SERDES %d, mode %02x\n", __func__, sds_num, sds_mode);
3016
3017 /* Configure link to MAC */
3018 rtl9300_serdes_mac_link_config(sds_num, true, true); /* MAC Construct */
3019
3020 /* Disable MAC */
3021 sw_w32_mask(0, 1, RTL930X_MAC_FORCE_MODE_CTRL);
3022 mdelay(20);
3023
3024 rtl9300_force_sds_mode(sds_num, PHY_INTERFACE_MODE_NA);
3025
3026 /* Re-Enable MAC */
3027 sw_w32_mask(1, 0, RTL930X_MAC_FORCE_MODE_CTRL);
3028
3029 rtl9300_force_sds_mode(sds_num, phy_mode);
3030
3031 /* Do RX calibration */
3032 do {
3033 rtl9300_do_rx_calibration(sds_num, phy_mode);
3034 calib_tries++;
3035 mdelay(50);
3036 } while (rtl9300_sds_check_calibration(sds_num, phy_mode) && calib_tries < 3);
3037
3038 if (calib_tries >= 3)
3039 pr_err("%s CALIBTRATION FAILED\n", __func__);
3040
3041 rtl9300_sds_tx_config(sds_num, phy_mode);
3042
3043 /* The clock needs only to be configured on the FPGA implementation */
3044
3045 return 0;
3046 }
3047
3048 void rtl9310_sds_field_w(int sds, u32 page, u32 reg, int end_bit, int start_bit, u32 v)
3049 {
3050 int l = end_bit - start_bit + 1;
3051 u32 data = v;
3052
3053 if (l < 32) {
3054 u32 mask = BIT(l) - 1;
3055
3056 data = rtl930x_read_sds_phy(sds, page, reg);
3057 data &= ~(mask << start_bit);
3058 data |= (v & mask) << start_bit;
3059 }
3060
3061 rtl931x_write_sds_phy(sds, page, reg, data);
3062 }
3063
3064 u32 rtl9310_sds_field_r(int sds, u32 page, u32 reg, int end_bit, int start_bit)
3065 {
3066 int l = end_bit - start_bit + 1;
3067 u32 v = rtl931x_read_sds_phy(sds, page, reg);
3068
3069 if (l >= 32)
3070 return v;
3071
3072 return (v >> start_bit) & (BIT(l) - 1);
3073 }
3074
3075 static void rtl931x_sds_rst(u32 sds)
3076 {
3077 u32 o, v, o_mode;
3078 int shift = ((sds & 0x3) << 3);
3079
3080 /* TODO: We need to lock this! */
3081
3082 o = sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
3083 v = o | BIT(sds);
3084 sw_w32(v, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
3085
3086 o_mode = sw_r32(RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
3087 v = BIT(7) | 0x1F;
3088 sw_w32_mask(0xff << shift, v << shift, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
3089 sw_w32(o_mode, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
3090
3091 sw_w32(o, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
3092 }
3093
3094 static void rtl931x_symerr_clear(u32 sds, phy_interface_t mode)
3095 {
3096
3097 switch (mode) {
3098 case PHY_INTERFACE_MODE_NA:
3099 break;
3100 case PHY_INTERFACE_MODE_XGMII:
3101 u32 xsg_sdsid_0, xsg_sdsid_1;
3102
3103 if (sds < 2)
3104 xsg_sdsid_0 = sds;
3105 else
3106 xsg_sdsid_0 = (sds - 1) * 2;
3107 xsg_sdsid_1 = xsg_sdsid_0 + 1;
3108
3109 for (int i = 0; i < 4; ++i) {
3110 rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 24, 2, 0, i);
3111 rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 3, 15, 8, 0x0);
3112 rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 2, 15, 0, 0x0);
3113 }
3114
3115 for (int i = 0; i < 4; ++i) {
3116 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 24, 2, 0, i);
3117 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 3, 15, 8, 0x0);
3118 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 2, 15, 0, 0x0);
3119 }
3120
3121 rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 0, 15, 0, 0x0);
3122 rtl9310_sds_field_w(xsg_sdsid_0, 0x1, 1, 15, 8, 0x0);
3123 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 0, 15, 0, 0x0);
3124 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 1, 15, 8, 0x0);
3125 break;
3126 default:
3127 break;
3128 }
3129
3130 return;
3131 }
3132
3133 static u32 rtl931x_get_analog_sds(u32 sds)
3134 {
3135 u32 sds_map[] = { 0, 1, 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23 };
3136
3137 if (sds < 14)
3138 return sds_map[sds];
3139
3140 return sds;
3141 }
3142
3143 void rtl931x_sds_fiber_disable(u32 sds)
3144 {
3145 u32 v = 0x3F;
3146 u32 asds = rtl931x_get_analog_sds(sds);
3147
3148 rtl9310_sds_field_w(asds, 0x1F, 0x9, 11, 6, v);
3149 }
3150
3151 static void rtl931x_sds_fiber_mode_set(u32 sds, phy_interface_t mode)
3152 {
3153 u32 val, asds = rtl931x_get_analog_sds(sds);
3154
3155 /* clear symbol error count before changing mode */
3156 rtl931x_symerr_clear(sds, mode);
3157
3158 val = 0x9F;
3159 sw_w32(val, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
3160
3161 switch (mode) {
3162 case PHY_INTERFACE_MODE_SGMII:
3163 val = 0x5;
3164 break;
3165
3166 case PHY_INTERFACE_MODE_1000BASEX:
3167 /* serdes mode FIBER1G */
3168 val = 0x9;
3169 break;
3170
3171 case PHY_INTERFACE_MODE_10GBASER:
3172 case PHY_INTERFACE_MODE_10GKR:
3173 val = 0x35;
3174 break;
3175 /* case MII_10GR1000BX_AUTO:
3176 val = 0x39;
3177 break; */
3178
3179
3180 case PHY_INTERFACE_MODE_USXGMII:
3181 val = 0x1B;
3182 break;
3183 default:
3184 val = 0x25;
3185 }
3186
3187 pr_info("%s writing analog SerDes Mode value %02x\n", __func__, val);
3188 rtl9310_sds_field_w(asds, 0x1F, 0x9, 11, 6, val);
3189
3190 return;
3191 }
3192
3193 static int rtl931x_sds_cmu_page_get(phy_interface_t mode)
3194 {
3195 switch (mode) {
3196 case PHY_INTERFACE_MODE_SGMII:
3197 case PHY_INTERFACE_MODE_1000BASEX: /* MII_1000BX_FIBER / 100BX_FIBER / 1000BX100BX_AUTO */
3198 return 0x24;
3199 case PHY_INTERFACE_MODE_HSGMII:
3200 case PHY_INTERFACE_MODE_2500BASEX: /* MII_2500Base_X: */
3201 return 0x28;
3202 /* case MII_HISGMII_5G: */
3203 /* return 0x2a; */
3204 case PHY_INTERFACE_MODE_QSGMII:
3205 return 0x2a; /* Code also has 0x34 */
3206 case PHY_INTERFACE_MODE_XAUI: /* MII_RXAUI_LITE: */
3207 return 0x2c;
3208 case PHY_INTERFACE_MODE_XGMII: /* MII_XSGMII */
3209 case PHY_INTERFACE_MODE_10GKR:
3210 case PHY_INTERFACE_MODE_10GBASER: /* MII_10GR */
3211 return 0x2e;
3212 default:
3213 return -1;
3214 }
3215
3216 return -1;
3217 }
3218
3219 static void rtl931x_cmu_type_set(u32 asds, phy_interface_t mode, int chiptype)
3220 {
3221 int cmu_type = 0; /* Clock Management Unit */
3222 u32 cmu_page = 0;
3223 u32 frc_cmu_spd;
3224 u32 evenSds;
3225 u32 lane, frc_lc_mode_bitnum, frc_lc_mode_val_bitnum;
3226
3227 switch (mode) {
3228 case PHY_INTERFACE_MODE_NA:
3229 case PHY_INTERFACE_MODE_10GKR:
3230 case PHY_INTERFACE_MODE_XGMII:
3231 case PHY_INTERFACE_MODE_10GBASER:
3232 case PHY_INTERFACE_MODE_USXGMII:
3233 return;
3234
3235 /* case MII_10GR1000BX_AUTO:
3236 if (chiptype)
3237 rtl9310_sds_field_w(asds, 0x24, 0xd, 14, 14, 0);
3238 return; */
3239
3240 case PHY_INTERFACE_MODE_QSGMII:
3241 cmu_type = 1;
3242 frc_cmu_spd = 0;
3243 break;
3244
3245 case PHY_INTERFACE_MODE_HSGMII:
3246 cmu_type = 1;
3247 frc_cmu_spd = 1;
3248 break;
3249
3250 case PHY_INTERFACE_MODE_1000BASEX:
3251 cmu_type = 1;
3252 frc_cmu_spd = 0;
3253 break;
3254
3255 /* case MII_1000BX100BX_AUTO:
3256 cmu_type = 1;
3257 frc_cmu_spd = 0;
3258 break; */
3259
3260 case PHY_INTERFACE_MODE_SGMII:
3261 cmu_type = 1;
3262 frc_cmu_spd = 0;
3263 break;
3264
3265 case PHY_INTERFACE_MODE_2500BASEX:
3266 cmu_type = 1;
3267 frc_cmu_spd = 1;
3268 break;
3269
3270 default:
3271 pr_info("SerDes %d mode is invalid\n", asds);
3272 return;
3273 }
3274
3275 if (cmu_type == 1)
3276 cmu_page = rtl931x_sds_cmu_page_get(mode);
3277
3278 lane = asds % 2;
3279
3280 if (!lane) {
3281 frc_lc_mode_bitnum = 4;
3282 frc_lc_mode_val_bitnum = 5;
3283 } else {
3284 frc_lc_mode_bitnum = 6;
3285 frc_lc_mode_val_bitnum = 7;
3286 }
3287
3288 evenSds = asds - lane;
3289
3290 pr_info("%s: cmu_type %0d cmu_page %x frc_cmu_spd %d lane %d asds %d\n",
3291 __func__, cmu_type, cmu_page, frc_cmu_spd, lane, asds);
3292
3293 if (cmu_type == 1) {
3294 pr_info("%s A CMU page 0x28 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x28, 0x7));
3295 rtl9310_sds_field_w(asds, cmu_page, 0x7, 15, 15, 0);
3296 pr_info("%s B CMU page 0x28 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x28, 0x7));
3297 if (chiptype) {
3298 rtl9310_sds_field_w(asds, cmu_page, 0xd, 14, 14, 0);
3299 }
3300
3301 rtl9310_sds_field_w(evenSds, 0x20, 0x12, 3, 2, 0x3);
3302 rtl9310_sds_field_w(evenSds, 0x20, 0x12, frc_lc_mode_bitnum, frc_lc_mode_bitnum, 1);
3303 rtl9310_sds_field_w(evenSds, 0x20, 0x12, frc_lc_mode_val_bitnum, frc_lc_mode_val_bitnum, 0);
3304 rtl9310_sds_field_w(evenSds, 0x20, 0x12, 12, 12, 1);
3305 rtl9310_sds_field_w(evenSds, 0x20, 0x12, 15, 13, frc_cmu_spd);
3306 }
3307
3308 pr_info("%s CMU page 0x28 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x28, 0x7));
3309 return;
3310 }
3311
3312 static void rtl931x_sds_rx_rst(u32 sds)
3313 {
3314 u32 asds = rtl931x_get_analog_sds(sds);
3315
3316 if (sds < 2)
3317 return;
3318
3319 rtl931x_write_sds_phy(asds, 0x2e, 0x12, 0x2740);
3320 rtl931x_write_sds_phy(asds, 0x2f, 0x0, 0x0);
3321 rtl931x_write_sds_phy(asds, 0x2f, 0x2, 0x2010);
3322 rtl931x_write_sds_phy(asds, 0x20, 0x0, 0xc10);
3323
3324 rtl931x_write_sds_phy(asds, 0x2e, 0x12, 0x27c0);
3325 rtl931x_write_sds_phy(asds, 0x2f, 0x0, 0xc000);
3326 rtl931x_write_sds_phy(asds, 0x2f, 0x2, 0x6010);
3327 rtl931x_write_sds_phy(asds, 0x20, 0x0, 0xc30);
3328
3329 mdelay(50);
3330 }
3331
3332 // Currently not used
3333 // static void rtl931x_sds_disable(u32 sds)
3334 // {
3335 // u32 v = 0x1f;
3336
3337 // v |= BIT(7);
3338 // sw_w32(v, RTL931X_SERDES_MODE_CTRL + (sds >> 2) * 4);
3339 // }
3340
3341 static void rtl931x_sds_mii_mode_set(u32 sds, phy_interface_t mode)
3342 {
3343 u32 val;
3344
3345 switch (mode) {
3346 case PHY_INTERFACE_MODE_QSGMII:
3347 val = 0x6;
3348 break;
3349 case PHY_INTERFACE_MODE_XGMII:
3350 val = 0x10; /* serdes mode XSGMII */
3351 break;
3352 case PHY_INTERFACE_MODE_USXGMII:
3353 case PHY_INTERFACE_MODE_2500BASEX:
3354 val = 0xD;
3355 break;
3356 case PHY_INTERFACE_MODE_HSGMII:
3357 val = 0x12;
3358 break;
3359 case PHY_INTERFACE_MODE_SGMII:
3360 val = 0x2;
3361 break;
3362 default:
3363 return;
3364 }
3365
3366 val |= (1 << 7);
3367
3368 sw_w32(val, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
3369 }
3370
3371 static sds_config sds_config_10p3125g_type1[] = {
3372 { 0x2E, 0x00, 0x0107 }, { 0x2E, 0x01, 0x01A3 }, { 0x2E, 0x02, 0x6A24 },
3373 { 0x2E, 0x03, 0xD10D }, { 0x2E, 0x04, 0x8000 }, { 0x2E, 0x05, 0xA17E },
3374 { 0x2E, 0x06, 0xE31D }, { 0x2E, 0x07, 0x800E }, { 0x2E, 0x08, 0x0294 },
3375 { 0x2E, 0x09, 0x0CE4 }, { 0x2E, 0x0A, 0x7FC8 }, { 0x2E, 0x0B, 0xE0E7 },
3376 { 0x2E, 0x0C, 0x0200 }, { 0x2E, 0x0D, 0xDF80 }, { 0x2E, 0x0E, 0x0000 },
3377 { 0x2E, 0x0F, 0x1FC2 }, { 0x2E, 0x10, 0x0C3F }, { 0x2E, 0x11, 0x0000 },
3378 { 0x2E, 0x12, 0x27C0 }, { 0x2E, 0x13, 0x7E1D }, { 0x2E, 0x14, 0x1300 },
3379 { 0x2E, 0x15, 0x003F }, { 0x2E, 0x16, 0xBE7F }, { 0x2E, 0x17, 0x0090 },
3380 { 0x2E, 0x18, 0x0000 }, { 0x2E, 0x19, 0x4000 }, { 0x2E, 0x1A, 0x0000 },
3381 { 0x2E, 0x1B, 0x8000 }, { 0x2E, 0x1C, 0x011F }, { 0x2E, 0x1D, 0x0000 },
3382 { 0x2E, 0x1E, 0xC8FF }, { 0x2E, 0x1F, 0x0000 }, { 0x2F, 0x00, 0xC000 },
3383 { 0x2F, 0x01, 0xF000 }, { 0x2F, 0x02, 0x6010 }, { 0x2F, 0x12, 0x0EE7 },
3384 { 0x2F, 0x13, 0x0000 }
3385 };
3386
3387 static sds_config sds_config_10p3125g_cmu_type1[] = {
3388 { 0x2F, 0x03, 0x4210 }, { 0x2F, 0x04, 0x0000 }, { 0x2F, 0x05, 0x0019 },
3389 { 0x2F, 0x06, 0x18A6 }, { 0x2F, 0x07, 0x2990 }, { 0x2F, 0x08, 0xFFF4 },
3390 { 0x2F, 0x09, 0x1F08 }, { 0x2F, 0x0A, 0x0000 }, { 0x2F, 0x0B, 0x8000 },
3391 { 0x2F, 0x0C, 0x4224 }, { 0x2F, 0x0D, 0x0000 }, { 0x2F, 0x0E, 0x0000 },
3392 { 0x2F, 0x0F, 0xA470 }, { 0x2F, 0x10, 0x8000 }, { 0x2F, 0x11, 0x037B }
3393 };
3394
3395 void rtl931x_sds_init(u32 sds, phy_interface_t mode)
3396 {
3397 u32 board_sds_tx_type1[] = {
3398 0x01c3, 0x01c3, 0x01c3, 0x01a3, 0x01a3, 0x01a3,
3399 0x0143, 0x0143, 0x0143, 0x0143, 0x0163, 0x0163,
3400 };
3401 u32 board_sds_tx[] = {
3402 0x1a00, 0x1a00, 0x0200, 0x0200, 0x0200, 0x0200,
3403 0x01a3, 0x01a3, 0x01a3, 0x01a3, 0x01e3, 0x01e3
3404 };
3405 u32 board_sds_tx2[] = {
3406 0x0dc0, 0x01c0, 0x0200, 0x0180, 0x0160, 0x0123,
3407 0x0123, 0x0163, 0x01a3, 0x01a0, 0x01c3, 0x09c3,
3408 };
3409 u32 asds, dSds, ori, model_info, val;
3410 int chiptype = 0;
3411
3412 asds = rtl931x_get_analog_sds(sds);
3413
3414 if (sds > 13)
3415 return;
3416
3417 pr_info("%s: set sds %d to mode %d\n", __func__, sds, mode);
3418 val = rtl9310_sds_field_r(asds, 0x1F, 0x9, 11, 6);
3419
3420 pr_info("%s: fibermode %08X stored mode 0x%x analog SDS %d", __func__,
3421 rtl931x_read_sds_phy(asds, 0x1f, 0x9), val, asds);
3422 pr_info("%s: SGMII mode %08X in 0x24 0x9 analog SDS %d", __func__,
3423 rtl931x_read_sds_phy(asds, 0x24, 0x9), asds);
3424 pr_info("%s: CMU mode %08X stored even SDS %d", __func__,
3425 rtl931x_read_sds_phy(asds & ~1, 0x20, 0x12), asds & ~1);
3426 pr_info("%s: serdes_mode_ctrl %08X", __func__, RTL931X_SERDES_MODE_CTRL + 4 * (sds >> 2));
3427 pr_info("%s CMU page 0x24 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x24, 0x7));
3428 pr_info("%s CMU page 0x26 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x26, 0x7));
3429 pr_info("%s CMU page 0x28 0x7 %08x\n", __func__, rtl931x_read_sds_phy(asds, 0x28, 0x7));
3430 pr_info("%s XSG page 0x0 0xe %08x\n", __func__, rtl931x_read_sds_phy(dSds, 0x0, 0xe));
3431 pr_info("%s XSG2 page 0x0 0xe %08x\n", __func__, rtl931x_read_sds_phy(dSds + 1, 0x0, 0xe));
3432
3433 model_info = sw_r32(RTL93XX_MODEL_NAME_INFO);
3434 if ((model_info >> 4) & 0x1) {
3435 pr_info("detected chiptype 1\n");
3436 chiptype = 1;
3437 } else {
3438 pr_info("detected chiptype 0\n");
3439 }
3440
3441 if (sds < 2)
3442 dSds = sds;
3443 else
3444 dSds = (sds - 1) * 2;
3445
3446 pr_info("%s: 2.5gbit %08X dsds %d", __func__,
3447 rtl931x_read_sds_phy(dSds, 0x1, 0x14), dSds);
3448
3449 pr_info("%s: RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR 0x%08X\n", __func__, sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR));
3450 ori = sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
3451 val = ori | (1 << sds);
3452 sw_w32(val, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
3453
3454 switch (mode) {
3455 case PHY_INTERFACE_MODE_NA:
3456 break;
3457
3458 case PHY_INTERFACE_MODE_XGMII: /* MII_XSGMII */
3459
3460 if (chiptype) {
3461 u32 xsg_sdsid_1;
3462 xsg_sdsid_1 = dSds + 1;
3463 /* fifo inv clk */
3464 rtl9310_sds_field_w(dSds, 0x1, 0x1, 7, 4, 0xf);
3465 rtl9310_sds_field_w(dSds, 0x1, 0x1, 3, 0, 0xf);
3466
3467 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 0x1, 7, 4, 0xf);
3468 rtl9310_sds_field_w(xsg_sdsid_1, 0x1, 0x1, 3, 0, 0xf);
3469
3470 }
3471
3472 rtl9310_sds_field_w(dSds, 0x0, 0xE, 12, 12, 1);
3473 rtl9310_sds_field_w(dSds + 1, 0x0, 0xE, 12, 12, 1);
3474 break;
3475
3476 case PHY_INTERFACE_MODE_USXGMII: /* MII_USXGMII_10GSXGMII/10GDXGMII/10GQXGMII: */
3477 u32 op_code = 0x6003;
3478 u32 evenSds;
3479
3480 if (chiptype) {
3481 rtl9310_sds_field_w(asds, 0x6, 0x2, 12, 12, 1);
3482
3483 for (int i = 0; i < sizeof(sds_config_10p3125g_type1) / sizeof(sds_config); ++i) {
3484 rtl931x_write_sds_phy(asds, sds_config_10p3125g_type1[i].page - 0x4, sds_config_10p3125g_type1[i].reg, sds_config_10p3125g_type1[i].data);
3485 }
3486
3487 evenSds = asds - (asds % 2);
3488
3489 for (int i = 0; i < sizeof(sds_config_10p3125g_cmu_type1) / sizeof(sds_config); ++i) {
3490 rtl931x_write_sds_phy(evenSds,
3491 sds_config_10p3125g_cmu_type1[i].page - 0x4, sds_config_10p3125g_cmu_type1[i].reg, sds_config_10p3125g_cmu_type1[i].data);
3492 }
3493
3494 rtl9310_sds_field_w(asds, 0x6, 0x2, 12, 12, 0);
3495 } else {
3496
3497 rtl9310_sds_field_w(asds, 0x2e, 0xd, 6, 0, 0x0);
3498 rtl9310_sds_field_w(asds, 0x2e, 0xd, 7, 7, 0x1);
3499
3500 rtl9310_sds_field_w(asds, 0x2e, 0x1c, 5, 0, 0x1E);
3501 rtl9310_sds_field_w(asds, 0x2e, 0x1d, 11, 0, 0x00);
3502 rtl9310_sds_field_w(asds, 0x2e, 0x1f, 11, 0, 0x00);
3503 rtl9310_sds_field_w(asds, 0x2f, 0x0, 11, 0, 0x00);
3504 rtl9310_sds_field_w(asds, 0x2f, 0x1, 11, 0, 0x00);
3505
3506 rtl9310_sds_field_w(asds, 0x2e, 0xf, 12, 6, 0x7F);
3507 rtl931x_write_sds_phy(asds, 0x2f, 0x12, 0xaaa);
3508
3509 rtl931x_sds_rx_rst(sds);
3510
3511 rtl931x_write_sds_phy(asds, 0x7, 0x10, op_code);
3512 rtl931x_write_sds_phy(asds, 0x6, 0x1d, 0x0480);
3513 rtl931x_write_sds_phy(asds, 0x6, 0xe, 0x0400);
3514 }
3515 break;
3516
3517 case PHY_INTERFACE_MODE_10GBASER: /* MII_10GR / MII_10GR1000BX_AUTO: */
3518 /* configure 10GR fiber mode=1 */
3519 rtl9310_sds_field_w(asds, 0x1f, 0xb, 1, 1, 1);
3520
3521 /* init fiber_1g */
3522 rtl9310_sds_field_w(dSds, 0x3, 0x13, 15, 14, 0);
3523
3524 rtl9310_sds_field_w(dSds, 0x2, 0x0, 12, 12, 1);
3525 rtl9310_sds_field_w(dSds, 0x2, 0x0, 6, 6, 1);
3526 rtl9310_sds_field_w(dSds, 0x2, 0x0, 13, 13, 0);
3527
3528 /* init auto */
3529 rtl9310_sds_field_w(asds, 0x1f, 13, 15, 0, 0x109e);
3530 rtl9310_sds_field_w(asds, 0x1f, 0x6, 14, 10, 0x8);
3531 rtl9310_sds_field_w(asds, 0x1f, 0x7, 10, 4, 0x7f);
3532 break;
3533
3534 case PHY_INTERFACE_MODE_HSGMII:
3535 rtl9310_sds_field_w(dSds, 0x1, 0x14, 8, 8, 1);
3536 break;
3537
3538 case PHY_INTERFACE_MODE_1000BASEX: /* MII_1000BX_FIBER */
3539 rtl9310_sds_field_w(dSds, 0x3, 0x13, 15, 14, 0);
3540
3541 rtl9310_sds_field_w(dSds, 0x2, 0x0, 12, 12, 1);
3542 rtl9310_sds_field_w(dSds, 0x2, 0x0, 6, 6, 1);
3543 rtl9310_sds_field_w(dSds, 0x2, 0x0, 13, 13, 0);
3544 break;
3545
3546 case PHY_INTERFACE_MODE_SGMII:
3547 rtl9310_sds_field_w(asds, 0x24, 0x9, 15, 15, 0);
3548 break;
3549
3550 case PHY_INTERFACE_MODE_2500BASEX:
3551 rtl9310_sds_field_w(dSds, 0x1, 0x14, 8, 8, 1);
3552 break;
3553
3554 case PHY_INTERFACE_MODE_QSGMII:
3555 default:
3556 pr_info("%s: PHY mode %s not supported by SerDes %d\n",
3557 __func__, phy_modes(mode), sds);
3558 return;
3559 }
3560
3561 rtl931x_cmu_type_set(asds, mode, chiptype);
3562
3563 if (sds >= 2 && sds <= 13) {
3564 if (chiptype)
3565 rtl931x_write_sds_phy(asds, 0x2E, 0x1, board_sds_tx_type1[sds - 2]);
3566 else {
3567 val = 0xa0000;
3568 sw_w32(val, RTL931X_CHIP_INFO_ADDR);
3569 val = sw_r32(RTL931X_CHIP_INFO_ADDR);
3570 if (val & BIT(28)) /* consider 9311 etc. RTL9313_CHIP_ID == HWP_CHIP_ID(unit)) */
3571 {
3572 rtl931x_write_sds_phy(asds, 0x2E, 0x1, board_sds_tx2[sds - 2]);
3573 } else {
3574 rtl931x_write_sds_phy(asds, 0x2E, 0x1, board_sds_tx[sds - 2]);
3575 }
3576 val = 0;
3577 sw_w32(val, RTL931X_CHIP_INFO_ADDR);
3578 }
3579 }
3580
3581 val = ori & ~BIT(sds);
3582 sw_w32(val, RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR);
3583 pr_debug("%s: RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR 0x%08X\n", __func__, sw_r32(RTL931X_PS_SERDES_OFF_MODE_CTRL_ADDR));
3584
3585 if (mode == PHY_INTERFACE_MODE_XGMII ||
3586 mode == PHY_INTERFACE_MODE_QSGMII ||
3587 mode == PHY_INTERFACE_MODE_HSGMII ||
3588 mode == PHY_INTERFACE_MODE_SGMII ||
3589 mode == PHY_INTERFACE_MODE_USXGMII) {
3590 if (mode == PHY_INTERFACE_MODE_XGMII)
3591 rtl931x_sds_mii_mode_set(sds, mode);
3592 else
3593 rtl931x_sds_fiber_mode_set(sds, mode);
3594 }
3595 }
3596
3597 int rtl931x_sds_cmu_band_set(int sds, bool enable, u32 band, phy_interface_t mode)
3598 {
3599 u32 asds;
3600 int page = rtl931x_sds_cmu_page_get(mode);
3601
3602 sds -= (sds % 2);
3603 sds = sds & ~1;
3604 asds = rtl931x_get_analog_sds(sds);
3605 page += 1;
3606
3607 if (enable) {
3608 rtl9310_sds_field_w(asds, page, 0x7, 13, 13, 0);
3609 rtl9310_sds_field_w(asds, page, 0x7, 11, 11, 0);
3610 } else {
3611 rtl9310_sds_field_w(asds, page, 0x7, 13, 13, 0);
3612 rtl9310_sds_field_w(asds, page, 0x7, 11, 11, 0);
3613 }
3614
3615 rtl9310_sds_field_w(asds, page, 0x7, 4, 0, band);
3616
3617 rtl931x_sds_rst(sds);
3618
3619 return 0;
3620 }
3621
3622 int rtl931x_sds_cmu_band_get(int sds, phy_interface_t mode)
3623 {
3624 int page = rtl931x_sds_cmu_page_get(mode);
3625 u32 asds, band;
3626
3627 sds -= (sds % 2);
3628 asds = rtl931x_get_analog_sds(sds);
3629 page += 1;
3630 rtl931x_write_sds_phy(asds, 0x1f, 0x02, 73);
3631
3632 rtl9310_sds_field_w(asds, page, 0x5, 15, 15, 1);
3633 band = rtl9310_sds_field_r(asds, 0x1f, 0x15, 8, 3);
3634 pr_info("%s band is: %d\n", __func__, band);
3635
3636 return band;
3637 }
3638
3639
3640 int rtl931x_link_sts_get(u32 sds)
3641 {
3642 u32 sts, sts1, latch_sts, latch_sts1;
3643 if (0){
3644 u32 xsg_sdsid_0, xsg_sdsid_1;
3645
3646 xsg_sdsid_0 = sds < 2 ? sds : (sds - 1) * 2;
3647 xsg_sdsid_1 = xsg_sdsid_0 + 1;
3648
3649 sts = rtl9310_sds_field_r(xsg_sdsid_0, 0x1, 29, 8, 0);
3650 sts1 = rtl9310_sds_field_r(xsg_sdsid_1, 0x1, 29, 8, 0);
3651 latch_sts = rtl9310_sds_field_r(xsg_sdsid_0, 0x1, 30, 8, 0);
3652 latch_sts1 = rtl9310_sds_field_r(xsg_sdsid_1, 0x1, 30, 8, 0);
3653 } else {
3654 u32 asds, dsds;
3655
3656 asds = rtl931x_get_analog_sds(sds);
3657 sts = rtl9310_sds_field_r(asds, 0x5, 0, 12, 12);
3658 latch_sts = rtl9310_sds_field_r(asds, 0x4, 1, 2, 2);
3659
3660 dsds = sds < 2 ? sds : (sds - 1) * 2;
3661 latch_sts1 = rtl9310_sds_field_r(dsds, 0x2, 1, 2, 2);
3662 sts1 = rtl9310_sds_field_r(dsds, 0x2, 1, 2, 2);
3663 }
3664
3665 pr_info("%s: serdes %d sts %d, sts1 %d, latch_sts %d, latch_sts1 %d\n", __func__,
3666 sds, sts, sts1, latch_sts, latch_sts1);
3667
3668 return sts1;
3669 }
3670
3671 static int rtl8214fc_sfp_insert(void *upstream, const struct sfp_eeprom_id *id)
3672 {
3673 struct phy_device *phydev = upstream;
3674
3675 rtl8214fc_media_set(phydev, true);
3676
3677 return 0;
3678 }
3679
3680 static void rtl8214fc_sfp_remove(void *upstream)
3681 {
3682 struct phy_device *phydev = upstream;
3683
3684 rtl8214fc_media_set(phydev, false);
3685 }
3686
3687 static const struct sfp_upstream_ops rtl8214fc_sfp_ops = {
3688 .attach = phy_sfp_attach,
3689 .detach = phy_sfp_detach,
3690 .module_insert = rtl8214fc_sfp_insert,
3691 .module_remove = rtl8214fc_sfp_remove,
3692 };
3693
3694 static int rtl8214fc_phy_probe(struct phy_device *phydev)
3695 {
3696 struct device *dev = &phydev->mdio.dev;
3697 int addr = phydev->mdio.addr;
3698 int ret = 0;
3699
3700 /* 839x has internal SerDes */
3701 if (soc_info.id == 0x8393)
3702 return -ENODEV;
3703
3704 /* All base addresses of the PHYs start at multiples of 8 */
3705 devm_phy_package_join(dev, phydev, addr & (~7),
3706 sizeof(struct rtl83xx_shared_private));
3707
3708 if (!(addr % 8)) {
3709 struct rtl83xx_shared_private *shared = phydev->shared->priv;
3710 shared->name = "RTL8214FC";
3711 /* Configuration must be done while patching still possible */
3712 ret = rtl8380_configure_rtl8214fc(phydev);
3713 if (ret)
3714 return ret;
3715 }
3716
3717 return phy_sfp_probe(phydev, &rtl8214fc_sfp_ops);
3718 }
3719
3720 static int rtl8214c_phy_probe(struct phy_device *phydev)
3721 {
3722 struct device *dev = &phydev->mdio.dev;
3723 int addr = phydev->mdio.addr;
3724
3725 /* All base addresses of the PHYs start at multiples of 8 */
3726 devm_phy_package_join(dev, phydev, addr & (~7),
3727 sizeof(struct rtl83xx_shared_private));
3728
3729 if (!(addr % 8)) {
3730 struct rtl83xx_shared_private *shared = phydev->shared->priv;
3731 shared->name = "RTL8214C";
3732 /* Configuration must be done whil patching still possible */
3733 return rtl8380_configure_rtl8214c(phydev);
3734 }
3735
3736 return 0;
3737 }
3738
3739 static int rtl8218b_ext_phy_probe(struct phy_device *phydev)
3740 {
3741 struct device *dev = &phydev->mdio.dev;
3742 int addr = phydev->mdio.addr;
3743
3744 /* All base addresses of the PHYs start at multiples of 8 */
3745 devm_phy_package_join(dev, phydev, addr & (~7),
3746 sizeof(struct rtl83xx_shared_private));
3747
3748 if (!(addr % 8)) {
3749 struct rtl83xx_shared_private *shared = phydev->shared->priv;
3750 shared->name = "RTL8218B (external)";
3751 if (soc_info.family == RTL8380_FAMILY_ID) {
3752 /* Configuration must be done while patching still possible */
3753 return rtl8380_configure_ext_rtl8218b(phydev);
3754 }
3755 }
3756
3757 return 0;
3758 }
3759
3760 static int rtl8218b_int_phy_probe(struct phy_device *phydev)
3761 {
3762 struct device *dev = &phydev->mdio.dev;
3763 int addr = phydev->mdio.addr;
3764
3765 if (soc_info.family != RTL8380_FAMILY_ID)
3766 return -ENODEV;
3767 if (addr >= 24)
3768 return -ENODEV;
3769
3770 pr_debug("%s: id: %d\n", __func__, addr);
3771 /* All base addresses of the PHYs start at multiples of 8 */
3772 devm_phy_package_join(dev, phydev, addr & (~7),
3773 sizeof(struct rtl83xx_shared_private));
3774
3775 if (!(addr % 8)) {
3776 struct rtl83xx_shared_private *shared = phydev->shared->priv;
3777 shared->name = "RTL8218B (internal)";
3778 /* Configuration must be done while patching still possible */
3779 return rtl8380_configure_int_rtl8218b(phydev);
3780 }
3781
3782 return 0;
3783 }
3784
3785 static int rtl8218d_phy_probe(struct phy_device *phydev)
3786 {
3787 struct device *dev = &phydev->mdio.dev;
3788 int addr = phydev->mdio.addr;
3789
3790 pr_debug("%s: id: %d\n", __func__, addr);
3791 /* All base addresses of the PHYs start at multiples of 8 */
3792 devm_phy_package_join(dev, phydev, addr & (~7),
3793 sizeof(struct rtl83xx_shared_private));
3794
3795 /* All base addresses of the PHYs start at multiples of 8 */
3796 if (!(addr % 8)) {
3797 struct rtl83xx_shared_private *shared = phydev->shared->priv;
3798 shared->name = "RTL8218D";
3799 /* Configuration must be done while patching still possible */
3800 /* TODO: return configure_rtl8218d(phydev); */
3801 }
3802
3803 return 0;
3804 }
3805
3806 static int rtl838x_serdes_probe(struct phy_device *phydev)
3807 {
3808 int addr = phydev->mdio.addr;
3809
3810 if (soc_info.family != RTL8380_FAMILY_ID)
3811 return -ENODEV;
3812 if (addr < 24)
3813 return -ENODEV;
3814
3815 /* On the RTL8380M, PHYs 24-27 connect to the internal SerDes */
3816 if (soc_info.id == 0x8380) {
3817 if (addr == 24)
3818 return rtl8380_configure_serdes(phydev);
3819 return 0;
3820 }
3821
3822 return -ENODEV;
3823 }
3824
3825 static int rtl8393_serdes_probe(struct phy_device *phydev)
3826 {
3827 int addr = phydev->mdio.addr;
3828
3829 pr_info("%s: id: %d\n", __func__, addr);
3830 if (soc_info.family != RTL8390_FAMILY_ID)
3831 return -ENODEV;
3832
3833 if (addr < 24)
3834 return -ENODEV;
3835
3836 return rtl8390_configure_serdes(phydev);
3837 }
3838
3839 static int rtl8390_serdes_probe(struct phy_device *phydev)
3840 {
3841 int addr = phydev->mdio.addr;
3842
3843 if (soc_info.family != RTL8390_FAMILY_ID)
3844 return -ENODEV;
3845
3846 if (addr < 24)
3847 return -ENODEV;
3848
3849 return rtl8390_configure_generic(phydev);
3850 }
3851
3852 static int rtl9300_serdes_probe(struct phy_device *phydev)
3853 {
3854 if (soc_info.family != RTL9300_FAMILY_ID)
3855 return -ENODEV;
3856
3857 phydev_info(phydev, "Detected internal RTL9300 Serdes\n");
3858
3859 return rtl9300_configure_serdes(phydev);
3860 }
3861
3862 static struct phy_driver rtl83xx_phy_driver[] = {
3863 {
3864 PHY_ID_MATCH_MODEL(PHY_ID_RTL8214C),
3865 .name = "Realtek RTL8214C",
3866 .features = PHY_GBIT_FEATURES,
3867 .flags = PHY_HAS_REALTEK_PAGES,
3868 .match_phy_device = rtl8214c_match_phy_device,
3869 .probe = rtl8214c_phy_probe,
3870 .suspend = genphy_suspend,
3871 .resume = genphy_resume,
3872 .set_loopback = genphy_loopback,
3873 },
3874 {
3875 PHY_ID_MATCH_MODEL(PHY_ID_RTL8214FC),
3876 .name = "Realtek RTL8214FC",
3877 .features = PHY_GBIT_FIBRE_FEATURES,
3878 .flags = PHY_HAS_REALTEK_PAGES,
3879 .match_phy_device = rtl8214fc_match_phy_device,
3880 .probe = rtl8214fc_phy_probe,
3881 .suspend = rtl8214fc_suspend,
3882 .resume = rtl8214fc_resume,
3883 .set_loopback = genphy_loopback,
3884 .set_port = rtl8214fc_set_port,
3885 .get_port = rtl8214fc_get_port,
3886 .set_eee = rtl8214fc_set_eee,
3887 .get_eee = rtl8214fc_get_eee,
3888 },
3889 {
3890 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_E),
3891 .name = "Realtek RTL8218B (external)",
3892 .features = PHY_GBIT_FEATURES,
3893 .flags = PHY_HAS_REALTEK_PAGES,
3894 .match_phy_device = rtl8218b_ext_match_phy_device,
3895 .probe = rtl8218b_ext_phy_probe,
3896 .suspend = genphy_suspend,
3897 .resume = genphy_resume,
3898 .set_loopback = genphy_loopback,
3899 .set_eee = rtl8218b_set_eee,
3900 .get_eee = rtl8218b_get_eee,
3901 },
3902 {
3903 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218D),
3904 .name = "REALTEK RTL8218D",
3905 .features = PHY_GBIT_FEATURES,
3906 .flags = PHY_HAS_REALTEK_PAGES,
3907 .probe = rtl8218d_phy_probe,
3908 .suspend = genphy_suspend,
3909 .resume = genphy_resume,
3910 .set_loopback = genphy_loopback,
3911 .set_eee = rtl8218d_set_eee,
3912 .get_eee = rtl8218d_get_eee,
3913 },
3914 {
3915 PHY_ID_MATCH_MODEL(PHY_ID_RTL8221B),
3916 .name = "REALTEK RTL8221B",
3917 .features = PHY_GBIT_FEATURES,
3918 .flags = PHY_HAS_REALTEK_PAGES,
3919 .suspend = genphy_suspend,
3920 .resume = genphy_resume,
3921 .set_loopback = genphy_loopback,
3922 .read_page = rtl8226_read_page,
3923 .write_page = rtl8226_write_page,
3924 .read_status = rtl8226_read_status,
3925 .config_aneg = rtl8226_config_aneg,
3926 .set_eee = rtl8226_set_eee,
3927 .get_eee = rtl8226_get_eee,
3928 },
3929 {
3930 PHY_ID_MATCH_MODEL(PHY_ID_RTL8226),
3931 .name = "REALTEK RTL8226",
3932 .features = PHY_GBIT_FEATURES,
3933 .flags = PHY_HAS_REALTEK_PAGES,
3934 .suspend = genphy_suspend,
3935 .resume = genphy_resume,
3936 .set_loopback = genphy_loopback,
3937 .read_page = rtl8226_read_page,
3938 .write_page = rtl8226_write_page,
3939 .read_status = rtl8226_read_status,
3940 .config_aneg = rtl8226_config_aneg,
3941 .set_eee = rtl8226_set_eee,
3942 .get_eee = rtl8226_get_eee,
3943 },
3944 {
3945 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_I),
3946 .name = "Realtek RTL8218B (internal)",
3947 .features = PHY_GBIT_FEATURES,
3948 .flags = PHY_HAS_REALTEK_PAGES,
3949 .probe = rtl8218b_int_phy_probe,
3950 .suspend = genphy_suspend,
3951 .resume = genphy_resume,
3952 .set_loopback = genphy_loopback,
3953 .set_eee = rtl8218b_set_eee,
3954 .get_eee = rtl8218b_get_eee,
3955 },
3956 {
3957 PHY_ID_MATCH_MODEL(PHY_ID_RTL8218B_I),
3958 .name = "Realtek RTL8380 SERDES",
3959 .features = PHY_GBIT_FIBRE_FEATURES,
3960 .flags = PHY_HAS_REALTEK_PAGES,
3961 .probe = rtl838x_serdes_probe,
3962 .suspend = genphy_suspend,
3963 .resume = genphy_resume,
3964 .set_loopback = genphy_loopback,
3965 .read_status = rtl8380_read_status,
3966 },
3967 {
3968 PHY_ID_MATCH_MODEL(PHY_ID_RTL8393_I),
3969 .name = "Realtek RTL8393 SERDES",
3970 .features = PHY_GBIT_FIBRE_FEATURES,
3971 .flags = PHY_HAS_REALTEK_PAGES,
3972 .probe = rtl8393_serdes_probe,
3973 .suspend = genphy_suspend,
3974 .resume = genphy_resume,
3975 .set_loopback = genphy_loopback,
3976 .read_status = rtl8393_read_status,
3977 },
3978 {
3979 PHY_ID_MATCH_MODEL(PHY_ID_RTL8390_GENERIC),
3980 .name = "Realtek RTL8390 Generic",
3981 .features = PHY_GBIT_FIBRE_FEATURES,
3982 .flags = PHY_HAS_REALTEK_PAGES,
3983 .probe = rtl8390_serdes_probe,
3984 .suspend = genphy_suspend,
3985 .resume = genphy_resume,
3986 .set_loopback = genphy_loopback,
3987 },
3988 {
3989 PHY_ID_MATCH_MODEL(PHY_ID_RTL9300_I),
3990 .name = "REALTEK RTL9300 SERDES",
3991 .features = PHY_GBIT_FIBRE_FEATURES,
3992 .flags = PHY_HAS_REALTEK_PAGES,
3993 .probe = rtl9300_serdes_probe,
3994 .suspend = genphy_suspend,
3995 .resume = genphy_resume,
3996 .set_loopback = genphy_loopback,
3997 .read_status = rtl9300_read_status,
3998 },
3999 };
4000
4001 module_phy_driver(rtl83xx_phy_driver);
4002
4003 static struct mdio_device_id __maybe_unused rtl83xx_tbl[] = {
4004 { PHY_ID_MATCH_MODEL(PHY_ID_RTL8214FC) },
4005 { }
4006 };
4007
4008 MODULE_DEVICE_TABLE(mdio, rtl83xx_tbl);
4009
4010 MODULE_AUTHOR("B. Koblitz");
4011 MODULE_DESCRIPTION("RTL83xx PHY driver");
4012 MODULE_LICENSE("GPL");
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