target/linux/realtek/files-5.4/arch/mips/rtl838x/setup.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Setup for the Realtek RTL838X SoC:
   4  *      Memory, Timer and Serial
   5  *
   6  * Copyright (C) 2020 B. Koblitz
   7  * based on the original BSP by
   8  * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com)
   9  *
  10  */
  11
  12 #include <linux/console.h>
  13 #include <linux/init.h>
  14 #include <linux/clk.h>
  15 #include <linux/clkdev.h>
  16 #include <linux/clk-provider.h>
  17
  18 #include <asm/addrspace.h>
  19 #include <asm/io.h>
  20
  21 #include <asm/bootinfo.h>
  22 #include <linux/of_fdt.h>
  23 #include <asm/reboot.h>
  24 #include <asm/time.h>           /* for mips_hpt_frequency */
  25 #include <asm/prom.h>
  26 #include <asm/smp-ops.h>
  27
  28 #include "mach-rtl83xx.h"
  29
  30 extern int rtl838x_serial_init(void);
  31 extern struct rtl83xx_soc_info soc_info;
  32
  33 u32 pll_reset_value;
  34
  35 static void rtl838x_restart(char *command)
  36 {
  37         u32 pll = sw_r32(RTL838X_PLL_CML_CTRL);
  38          /* SoC reset vector (in flash memory): on RTL839x platform preferred way to reset */
  39         void (*f)(void) = (void *) 0xbfc00000;
  40
  41         pr_info("System restart.\n");
  42         if (soc_info.family == RTL8390_FAMILY_ID) {
  43                 f();
  44                 /* If calling reset vector fails, reset entire chip */
  45                 sw_w32(0xFFFFFFFF, RTL839X_RST_GLB_CTRL);
  46                 /* If this fails, halt the CPU */
  47                 while
  48                         (1);
  49         }
  50
  51         pr_info("PLL control register: %x, applying reset value %x\n",
  52                 pll, pll_reset_value);
  53         sw_w32(3, RTL838X_INT_RW_CTRL);
  54         sw_w32(pll_reset_value, RTL838X_PLL_CML_CTRL);
  55         sw_w32(0, RTL838X_INT_RW_CTRL);
  56
  57         pr_info("Resetting RTL838X SoC\n");
  58         /* Reset Global Control1 Register */
  59         sw_w32(1, RTL838X_RST_GLB_CTRL_1);
  60 }
  61
  62 static void rtl838x_halt(void)
  63 {
  64         pr_info("System halted.\n");
  65         while(1);
  66 }
  67
  68 void __init plat_mem_setup(void)
  69 {
  70         void *dtb;
  71
  72         set_io_port_base(KSEG1);
  73         _machine_restart = rtl838x_restart;
  74         _machine_halt = rtl838x_halt;
  75
  76         if (fw_passed_dtb) /* UHI interface */
  77                 dtb = (void *)fw_passed_dtb;
  78         else if (__dtb_start != __dtb_end)
  79                 dtb = (void *)__dtb_start;
  80         else
  81                 panic("no dtb found");
  82
  83         /*
  84          * Load the devicetree. This causes the chosen node to be
  85          * parsed resulting in our memory appearing
  86          */
  87         __dt_setup_arch(dtb);
  88 }
  89
  90 void __init plat_time_init(void)
  91 {
  92         struct device_node *np;
  93         u32 freq = 500000000;
  94
  95         np = of_find_node_by_name(NULL, "cpus");
  96         if (!np) {
  97                 pr_err("Missing 'cpus' DT node, using default frequency.");
  98         } else {
  99                 if (of_property_read_u32(np, "frequency", &freq) < 0)
 100                         pr_err("No 'frequency' property in DT, using default.");
 101                 else
 102                         pr_info("CPU frequency from device tree: %d", freq);
 103                 of_node_put(np);
 104         }
 105
 106         mips_hpt_frequency = freq / 2;
 107
 108         pll_reset_value = sw_r32(RTL838X_PLL_CML_CTRL);
 109 }