1 // SPDX-License-Identifier: GPL-2.0-only
3 #include <linux/of_mdio.h>
4 #include <linux/of_platform.h>
6 #include <asm/mach-rtl838x/mach-rtl83xx.h>
9 extern struct rtl83xx_soc_info soc_info
;
11 extern const struct rtl838x_reg rtl838x_reg
;
12 extern const struct rtl838x_reg rtl839x_reg
;
13 extern const struct rtl838x_reg rtl930x_reg
;
14 extern const struct rtl838x_reg rtl931x_reg
;
16 extern const struct dsa_switch_ops rtl83xx_switch_ops
;
17 extern const struct dsa_switch_ops rtl930x_switch_ops
;
19 DEFINE_MUTEX(smi_lock
);
22 static void dump_fdb(struct rtl838x_switch_priv
*priv
)
24 struct rtl838x_l2_entry e
;
27 mutex_lock(&priv
->reg_mutex
);
29 for (i
= 0; i
< priv
->fib_entries
; i
++) {
30 priv
->r
->read_l2_entry_using_hash(i
>> 2, i
& 0x3, &e
);
32 if (!e
.valid
) /* Check for invalid entry */
35 pr_debug("-> port %02d: mac %pM, vid: %d, rvid: %d, MC: %d, %d\n",
36 e
.port
, &e
.mac
[0], e
.vid
, e
.rvid
, e
.is_ip_mc
, e
.is_ipv6_mc
);
39 mutex_unlock(&priv
->reg_mutex
);
42 int rtl83xx_port_get_stp_state(struct rtl838x_switch_priv
*priv
, int port
)
48 int n
= priv
->port_width
<< 1;
50 /* Ports above or equal CPU port can never be configured */
51 if (port
>= priv
->cpu_port
)
54 mutex_lock(&priv
->reg_mutex
);
56 /* For the RTL839x and following, the bits are left-aligned in the 64/128 bit field */
57 if (priv
->family_id
== RTL8390_FAMILY_ID
)
59 if (priv
->family_id
== RTL9300_FAMILY_ID
)
61 if (priv
->family_id
== RTL9310_FAMILY_ID
)
64 index
= n
- (pos
>> 4) - 1;
65 bit
= (pos
<< 1) % 32;
67 priv
->r
->stp_get(priv
, msti
, port_state
);
69 mutex_unlock(&priv
->reg_mutex
);
71 return (port_state
[index
] >> bit
) & 3;
74 static struct table_reg rtl838x_tbl_regs
[] = {
75 TBL_DESC(0x6900, 0x6908, 3, 15, 13, 1), // RTL8380_TBL_L2
76 TBL_DESC(0x6914, 0x6918, 18, 14, 12, 1), // RTL8380_TBL_0
77 TBL_DESC(0xA4C8, 0xA4CC, 6, 14, 12, 1), // RTL8380_TBL_1
79 TBL_DESC(0x1180, 0x1184, 3, 16, 14, 0), // RTL8390_TBL_L2
80 TBL_DESC(0x1190, 0x1194, 17, 15, 12, 0), // RTL8390_TBL_0
81 TBL_DESC(0x6B80, 0x6B84, 4, 14, 12, 0), // RTL8390_TBL_1
82 TBL_DESC(0x611C, 0x6120, 9, 8, 6, 0), // RTL8390_TBL_2
84 TBL_DESC(0xB320, 0xB334, 3, 18, 16, 0), // RTL9300_TBL_L2
85 TBL_DESC(0xB340, 0xB344, 19, 16, 12, 0), // RTL9300_TBL_0
86 TBL_DESC(0xB3A0, 0xB3A4, 20, 16, 13, 0), // RTL9300_TBL_1
87 TBL_DESC(0xCE04, 0xCE08, 6, 14, 12, 0), // RTL9300_TBL_2
88 TBL_DESC(0xD600, 0xD604, 30, 7, 6, 0), // RTL9300_TBL_HSB
89 TBL_DESC(0x7880, 0x7884, 22, 9, 8, 0), // RTL9300_TBL_HSA
91 TBL_DESC(0x8500, 0x8508, 8, 19, 15, 0), // RTL9310_TBL_0
92 TBL_DESC(0x40C0, 0x40C4, 22, 16, 14, 0), // RTL9310_TBL_1
93 TBL_DESC(0x8528, 0x852C, 6, 18, 14, 0), // RTL9310_TBL_2
94 TBL_DESC(0x0200, 0x0204, 9, 15, 12, 0), // RTL9310_TBL_3
95 TBL_DESC(0x20dc, 0x20e0, 29, 7, 6, 0), // RTL9310_TBL_4
96 TBL_DESC(0x7e1c, 0x7e20, 53, 8, 6, 0), // RTL9310_TBL_5
99 void rtl_table_init(void)
103 for (i
= 0; i
< RTL_TBL_END
; i
++)
104 mutex_init(&rtl838x_tbl_regs
[i
].lock
);
108 * Request access to table t in table access register r
109 * Returns a handle to a lock for that table
111 struct table_reg
*rtl_table_get(rtl838x_tbl_reg_t r
, int t
)
113 if (r
>= RTL_TBL_END
)
116 if (t
>= BIT(rtl838x_tbl_regs
[r
].c_bit
-rtl838x_tbl_regs
[r
].t_bit
))
119 mutex_lock(&rtl838x_tbl_regs
[r
].lock
);
120 rtl838x_tbl_regs
[r
].tbl
= t
;
122 return &rtl838x_tbl_regs
[r
];
126 * Release a table r, unlock the corresponding lock
128 void rtl_table_release(struct table_reg
*r
)
133 // pr_info("Unlocking %08x\n", (u32)r);
134 mutex_unlock(&r
->lock
);
135 // pr_info("Unlock done\n");
139 * Reads table index idx into the data registers of the table
141 void rtl_table_read(struct table_reg
*r
, int idx
)
143 u32 cmd
= r
->rmode
? BIT(r
->c_bit
) : 0;
145 cmd
|= BIT(r
->c_bit
+ 1) | (r
->tbl
<< r
->t_bit
) | (idx
& (BIT(r
->t_bit
) - 1));
146 sw_w32(cmd
, r
->addr
);
147 pr_debug("Writing %08x to %x for read\n", cmd
, r
->addr
);
148 do { } while (sw_r32(r
->addr
) & BIT(r
->c_bit
+ 1));
152 * Writes the content of the table data registers into the table at index idx
154 void rtl_table_write(struct table_reg
*r
, int idx
)
156 u32 cmd
= r
->rmode
? 0 : BIT(r
->c_bit
);
158 cmd
|= BIT(r
->c_bit
+ 1) | (r
->tbl
<< r
->t_bit
) | (idx
& (BIT(r
->t_bit
) - 1));
159 pr_debug("Writing %08x to %x for write, value %08x\n",
160 cmd
, r
->addr
, sw_r32(0xb344));
161 sw_w32(cmd
, r
->addr
);
162 do { } while (sw_r32(r
->addr
) & BIT(r
->c_bit
+ 1));
166 * Returns the address of the ith data register of table register r
167 * the address is relative to the beginning of the Switch-IO block at 0xbb000000
169 inline u16
rtl_table_data(struct table_reg
*r
, int i
)
171 if (i
>= r
->max_data
)
173 return r
->data
+ i
* 4;
176 inline u32
rtl_table_data_r(struct table_reg
*r
, int i
)
178 return sw_r32(rtl_table_data(r
, i
));
181 inline void rtl_table_data_w(struct table_reg
*r
, u32 v
, int i
)
183 sw_w32(v
, rtl_table_data(r
, i
));
186 /* Port register accessor functions for the RTL838x and RTL930X SoCs */
187 void rtl838x_mask_port_reg(u64 clear
, u64 set
, int reg
)
189 sw_w32_mask((u32
)clear
, (u32
)set
, reg
);
192 void rtl838x_set_port_reg(u64 set
, int reg
)
194 sw_w32((u32
)set
, reg
);
197 u64
rtl838x_get_port_reg(int reg
)
199 return ((u64
) sw_r32(reg
));
202 /* Port register accessor functions for the RTL839x and RTL931X SoCs */
203 void rtl839x_mask_port_reg_be(u64 clear
, u64 set
, int reg
)
205 sw_w32_mask((u32
)(clear
>> 32), (u32
)(set
>> 32), reg
);
206 sw_w32_mask((u32
)(clear
& 0xffffffff), (u32
)(set
& 0xffffffff), reg
+ 4);
209 u64
rtl839x_get_port_reg_be(int reg
)
214 v
|= sw_r32(reg
+ 4);
218 void rtl839x_set_port_reg_be(u64 set
, int reg
)
220 sw_w32(set
>> 32, reg
);
221 sw_w32(set
& 0xffffffff, reg
+ 4);
224 void rtl839x_mask_port_reg_le(u64 clear
, u64 set
, int reg
)
226 sw_w32_mask((u32
)clear
, (u32
)set
, reg
);
227 sw_w32_mask((u32
)(clear
>> 32), (u32
)(set
>> 32), reg
+ 4);
230 void rtl839x_set_port_reg_le(u64 set
, int reg
)
233 sw_w32(set
>> 32, reg
+ 4);
236 u64
rtl839x_get_port_reg_le(int reg
)
238 u64 v
= sw_r32(reg
+ 4);
245 int read_phy(u32 port
, u32 page
, u32 reg
, u32
*val
)
247 switch (soc_info
.family
) {
248 case RTL8380_FAMILY_ID
:
249 return rtl838x_read_phy(port
, page
, reg
, val
);
250 case RTL8390_FAMILY_ID
:
251 return rtl839x_read_phy(port
, page
, reg
, val
);
252 case RTL9300_FAMILY_ID
:
253 return rtl930x_read_phy(port
, page
, reg
, val
);
254 case RTL9310_FAMILY_ID
:
255 return rtl931x_read_phy(port
, page
, reg
, val
);
260 int write_phy(u32 port
, u32 page
, u32 reg
, u32 val
)
262 switch (soc_info
.family
) {
263 case RTL8380_FAMILY_ID
:
264 return rtl838x_write_phy(port
, page
, reg
, val
);
265 case RTL8390_FAMILY_ID
:
266 return rtl839x_write_phy(port
, page
, reg
, val
);
267 case RTL9300_FAMILY_ID
:
268 return rtl930x_write_phy(port
, page
, reg
, val
);
269 case RTL9310_FAMILY_ID
:
270 return rtl931x_write_phy(port
, page
, reg
, val
);
275 static int __init
rtl83xx_mdio_probe(struct rtl838x_switch_priv
*priv
)
277 struct device
*dev
= priv
->dev
;
278 struct device_node
*dn
, *mii_np
= dev
->of_node
;
283 pr_debug("In %s\n", __func__
);
284 mii_np
= of_find_compatible_node(NULL
, NULL
, "realtek,rtl838x-mdio");
286 pr_debug("Found compatible MDIO node!\n");
288 dev_err(priv
->dev
, "no %s child node found", "mdio-bus");
292 priv
->mii_bus
= of_mdio_find_bus(mii_np
);
293 if (!priv
->mii_bus
) {
294 pr_debug("Deferring probe of mdio bus\n");
295 return -EPROBE_DEFER
;
297 if (!of_device_is_available(mii_np
))
300 bus
= devm_mdiobus_alloc(priv
->ds
->dev
);
304 bus
->name
= "rtl838x slave mii";
307 * Since the NIC driver is loaded first, we can use the mdio rw functions
310 bus
->read
= priv
->mii_bus
->read
;
311 bus
->write
= priv
->mii_bus
->write
;
312 snprintf(bus
->id
, MII_BUS_ID_SIZE
, "%s-%d", bus
->name
, dev
->id
);
315 priv
->ds
->slave_mii_bus
= bus
;
316 priv
->ds
->slave_mii_bus
->priv
= priv
;
318 ret
= mdiobus_register(priv
->ds
->slave_mii_bus
);
325 for_each_node_by_name(dn
, "ethernet-phy") {
326 if (of_property_read_u32(dn
, "reg", &pn
))
329 priv
->ports
[pn
].dp
= dsa_to_port(priv
->ds
, pn
);
331 // Check for the integrated SerDes of the RTL8380M first
332 if (of_property_read_bool(dn
, "phy-is-integrated")
333 && priv
->id
== 0x8380 && pn
>= 24) {
334 pr_debug("----> FÓUND A SERDES\n");
335 priv
->ports
[pn
].phy
= PHY_RTL838X_SDS
;
339 if (of_property_read_bool(dn
, "phy-is-integrated")
340 && !of_property_read_bool(dn
, "sfp")) {
341 priv
->ports
[pn
].phy
= PHY_RTL8218B_INT
;
345 if (!of_property_read_bool(dn
, "phy-is-integrated")
346 && of_property_read_bool(dn
, "sfp")) {
347 priv
->ports
[pn
].phy
= PHY_RTL8214FC
;
351 if (!of_property_read_bool(dn
, "phy-is-integrated")
352 && !of_property_read_bool(dn
, "sfp")) {
353 priv
->ports
[pn
].phy
= PHY_RTL8218B_EXT
;
358 // TODO: Do this needs to come from the .dts, at least the SerDes number
359 if (priv
->family_id
== RTL9300_FAMILY_ID
) {
360 priv
->ports
[24].is2G5
= true;
361 priv
->ports
[25].is2G5
= true;
362 priv
->ports
[24].sds_num
= 1;
363 priv
->ports
[24].sds_num
= 2;
366 /* Disable MAC polling the PHY so that we can start configuration */
367 priv
->r
->set_port_reg_le(0ULL, priv
->r
->smi_poll_ctrl
);
369 /* Enable PHY control via SoC */
370 if (priv
->family_id
== RTL8380_FAMILY_ID
) {
371 /* Enable PHY control via SoC */
372 sw_w32_mask(0, BIT(15), RTL838X_SMI_GLB_CTRL
);
374 /* Disable PHY polling via SoC */
375 sw_w32_mask(BIT(7), 0, RTL839X_SMI_GLB_CTRL
);
378 /* Power on fibre ports and reset them if necessary */
379 if (priv
->ports
[24].phy
== PHY_RTL838X_SDS
) {
380 pr_debug("Powering on fibre ports & reset\n");
381 rtl8380_sds_power(24, 1);
382 rtl8380_sds_power(26, 1);
385 // TODO: Only power on SerDes with external PHYs connected
386 if (priv
->family_id
== RTL9300_FAMILY_ID
) {
387 pr_info("RTL9300 Powering on SerDes ports\n");
388 rtl9300_sds_power(24, 1);
389 rtl9300_sds_power(25, 1);
390 rtl9300_sds_power(26, 1);
391 rtl9300_sds_power(27, 1);
394 pr_debug("%s done\n", __func__
);
398 static int __init
rtl83xx_get_l2aging(struct rtl838x_switch_priv
*priv
)
400 int t
= sw_r32(priv
->r
->l2_ctrl_1
);
402 t
&= priv
->family_id
== RTL8380_FAMILY_ID
? 0x7fffff : 0x1FFFFF;
404 if (priv
->family_id
== RTL8380_FAMILY_ID
)
405 t
= t
* 128 / 625; /* Aging time in seconds. 0: L2 aging disabled */
409 pr_debug("L2 AGING time: %d sec\n", t
);
410 pr_debug("Dynamic aging for ports: %x\n", sw_r32(priv
->r
->l2_port_aging_out
));
414 /* Caller must hold priv->reg_mutex */
415 int rtl83xx_lag_add(struct dsa_switch
*ds
, int group
, int port
)
417 struct rtl838x_switch_priv
*priv
= ds
->priv
;
420 pr_info("%s: Adding port %d to LA-group %d\n", __func__
, port
, group
);
421 if (group
>= priv
->n_lags
) {
422 pr_err("Link Agrregation group too large.\n");
426 if (port
>= priv
->cpu_port
) {
427 pr_err("Invalid port number.\n");
431 for (i
= 0; i
< priv
->n_lags
; i
++) {
432 if (priv
->lags_port_members
[i
] & BIT_ULL(i
))
435 if (i
!= priv
->n_lags
) {
436 pr_err("%s: Port already member of LAG: %d\n", __func__
, i
);
440 priv
->r
->mask_port_reg_be(0, BIT_ULL(port
), priv
->r
->trk_mbr_ctr(group
));
441 priv
->lags_port_members
[group
] |= BIT_ULL(port
);
443 pr_info("lags_port_members %d now %016llx\n", group
, priv
->lags_port_members
[group
]);
447 /* Caller must hold priv->reg_mutex */
448 int rtl83xx_lag_del(struct dsa_switch
*ds
, int group
, int port
)
450 struct rtl838x_switch_priv
*priv
= ds
->priv
;
452 pr_info("%s: Removing port %d from LA-group %d\n", __func__
, port
, group
);
454 if (group
>= priv
->n_lags
) {
455 pr_err("Link Agrregation group too large.\n");
459 if (port
>= priv
->cpu_port
) {
460 pr_err("Invalid port number.\n");
465 if (!(priv
->lags_port_members
[group
] & BIT_ULL(port
))) {
466 pr_err("%s: Port not member of LAG: %d\n", __func__
, group
471 priv
->r
->mask_port_reg_be(BIT_ULL(port
), 0, priv
->r
->trk_mbr_ctr(group
));
472 priv
->lags_port_members
[group
] &= ~BIT_ULL(port
);
474 pr_info("lags_port_members %d now %016llx\n", group
, priv
->lags_port_members
[group
]);
478 static int rtl83xx_handle_changeupper(struct rtl838x_switch_priv
*priv
,
479 struct net_device
*ndev
,
480 struct netdev_notifier_changeupper_info
*info
)
482 struct net_device
*upper
= info
->upper_dev
;
485 if (!netif_is_lag_master(upper
))
488 mutex_lock(&priv
->reg_mutex
);
490 for (i
= 0; i
< priv
->n_lags
; i
++) {
491 if ((!priv
->lag_devs
[i
]) || (priv
->lag_devs
[i
] == upper
))
494 for (j
= 0; j
< priv
->cpu_port
; j
++) {
495 if (priv
->ports
[j
].dp
->slave
== ndev
)
498 if (j
>= priv
->cpu_port
) {
504 if (!priv
->lag_devs
[i
])
505 priv
->lag_devs
[i
] = upper
;
506 err
= rtl83xx_lag_add(priv
->ds
, i
, priv
->ports
[j
].dp
->index
);
512 if (!priv
->lag_devs
[i
])
514 err
= rtl83xx_lag_del(priv
->ds
, i
, priv
->ports
[j
].dp
->index
);
519 if (!priv
->lags_port_members
[i
])
520 priv
->lag_devs
[i
] = NULL
;
524 mutex_unlock(&priv
->reg_mutex
);
528 static int rtl83xx_netdevice_event(struct notifier_block
*this,
529 unsigned long event
, void *ptr
)
531 struct net_device
*ndev
= netdev_notifier_info_to_dev(ptr
);
532 struct rtl838x_switch_priv
*priv
;
535 pr_debug("In: %s, event: %lu\n", __func__
, event
);
537 if ((event
!= NETDEV_CHANGEUPPER
) && (event
!= NETDEV_CHANGELOWERSTATE
))
540 priv
= container_of(this, struct rtl838x_switch_priv
, nb
);
542 case NETDEV_CHANGEUPPER
:
543 err
= rtl83xx_handle_changeupper(priv
, ndev
, ptr
);
553 static int __init
rtl83xx_sw_probe(struct platform_device
*pdev
)
556 struct rtl838x_switch_priv
*priv
;
557 struct device
*dev
= &pdev
->dev
;
561 pr_debug("Probing RTL838X switch device\n");
562 if (!pdev
->dev
.of_node
) {
563 dev_err(dev
, "No DT found\n");
567 // Initialize access to RTL switch tables
570 priv
= devm_kzalloc(dev
, sizeof(*priv
), GFP_KERNEL
);
574 priv
->ds
= dsa_switch_alloc(dev
, DSA_MAX_PORTS
);
579 priv
->ds
->priv
= priv
;
580 priv
->ds
->ops
= &rtl83xx_switch_ops
;
583 priv
->family_id
= soc_info
.family
;
584 priv
->id
= soc_info
.id
;
585 switch(soc_info
.family
) {
586 case RTL8380_FAMILY_ID
:
587 priv
->ds
->ops
= &rtl83xx_switch_ops
;
588 priv
->cpu_port
= RTL838X_CPU_PORT
;
589 priv
->port_mask
= 0x1f;
590 priv
->port_width
= 1;
591 priv
->irq_mask
= 0x0FFFFFFF;
592 priv
->r
= &rtl838x_reg
;
593 priv
->ds
->num_ports
= 29;
594 priv
->fib_entries
= 8192;
595 rtl8380_get_version(priv
);
598 case RTL8390_FAMILY_ID
:
599 priv
->ds
->ops
= &rtl83xx_switch_ops
;
600 priv
->cpu_port
= RTL839X_CPU_PORT
;
601 priv
->port_mask
= 0x3f;
602 priv
->port_width
= 2;
603 priv
->irq_mask
= 0xFFFFFFFFFFFFFULL
;
604 priv
->r
= &rtl839x_reg
;
605 priv
->ds
->num_ports
= 53;
606 priv
->fib_entries
= 16384;
607 rtl8390_get_version(priv
);
610 case RTL9300_FAMILY_ID
:
611 priv
->ds
->ops
= &rtl930x_switch_ops
;
612 priv
->cpu_port
= RTL930X_CPU_PORT
;
613 priv
->port_mask
= 0x1f;
614 priv
->port_width
= 1;
615 priv
->irq_mask
= 0x0FFFFFFF;
616 priv
->r
= &rtl930x_reg
;
617 priv
->ds
->num_ports
= 29;
618 priv
->fib_entries
= 16384;
619 priv
->version
= RTL8390_VERSION_A
;
621 sw_w32(1, RTL930X_ST_CTRL
);
623 case RTL9310_FAMILY_ID
:
624 priv
->ds
->ops
= &rtl930x_switch_ops
;
625 priv
->cpu_port
= RTL931X_CPU_PORT
;
626 priv
->port_mask
= 0x3f;
627 priv
->port_width
= 2;
628 priv
->irq_mask
= 0xFFFFFFFFFFFFFULL
;
629 priv
->r
= &rtl931x_reg
;
630 priv
->ds
->num_ports
= 57;
631 priv
->fib_entries
= 16384;
632 priv
->version
= RTL8390_VERSION_A
;
636 pr_debug("Chip version %c\n", priv
->version
);
638 err
= rtl83xx_mdio_probe(priv
);
640 /* Probing fails the 1st time because of missing ethernet driver
641 * initialization. Use this to disable traffic in case the bootloader left if on
645 err
= dsa_register_switch(priv
->ds
);
647 dev_err(dev
, "Error registering switch: %d\n", err
);
651 /* Enable link and media change interrupts. Are the SERDES masks needed? */
652 sw_w32_mask(0, 3, priv
->r
->isr_glb_src
);
654 priv
->r
->set_port_reg_le(irq_mask
, priv
->r
->isr_port_link_sts_chg
);
655 priv
->r
->set_port_reg_le(irq_mask
, priv
->r
->imr_port_link_sts_chg
);
657 priv
->link_state_irq
= platform_get_irq(pdev
, 0);
658 pr_info("LINK state irq: %d\n", priv
->link_state_irq
);
659 switch (priv
->family_id
) {
660 case RTL8380_FAMILY_ID
:
661 err
= request_irq(priv
->link_state_irq
, rtl838x_switch_irq
,
662 IRQF_SHARED
, "rtl838x-link-state", priv
->ds
);
664 case RTL8390_FAMILY_ID
:
665 err
= request_irq(priv
->link_state_irq
, rtl839x_switch_irq
,
666 IRQF_SHARED
, "rtl839x-link-state", priv
->ds
);
668 case RTL9300_FAMILY_ID
:
669 err
= request_irq(priv
->link_state_irq
, rtl930x_switch_irq
,
670 IRQF_SHARED
, "rtl930x-link-state", priv
->ds
);
672 case RTL9310_FAMILY_ID
:
673 err
= request_irq(priv
->link_state_irq
, rtl931x_switch_irq
,
674 IRQF_SHARED
, "rtl931x-link-state", priv
->ds
);
678 dev_err(dev
, "Error setting up switch interrupt.\n");
679 /* Need to free allocated switch here */
682 /* Enable interrupts for switch, on RTL931x, the IRQ is always on globally */
683 if (soc_info
.family
!= RTL9310_FAMILY_ID
)
684 sw_w32(0x1, priv
->r
->imr_glb
);
686 rtl83xx_get_l2aging(priv
);
688 rtl83xx_setup_qos(priv
);
690 /* Clear all destination ports for mirror groups */
691 for (i
= 0; i
< 4; i
++)
692 priv
->mirror_group_ports
[i
] = -1;
694 priv
->nb
.notifier_call
= rtl83xx_netdevice_event
;
695 if (register_netdevice_notifier(&priv
->nb
)) {
696 priv
->nb
.notifier_call
= NULL
;
697 dev_err(dev
, "Failed to register LAG netdev notifier\n");
700 // Flood BPDUs to all ports including cpu-port
701 if (soc_info
.family
!= RTL9300_FAMILY_ID
) { // TODO: Port this functionality
702 bpdu_mask
= soc_info
.family
== RTL8380_FAMILY_ID
? 0x1FFFFFFF : 0x1FFFFFFFFFFFFF;
703 priv
->r
->set_port_reg_be(bpdu_mask
, priv
->r
->rma_bpdu_fld_pmask
);
705 // TRAP 802.1X frames (EAPOL) to the CPU-Port, bypass STP and VLANs
706 sw_w32(7, priv
->r
->spcl_trap_eapol_ctrl
);
708 rtl838x_dbgfs_init(priv
);
714 static int rtl83xx_sw_remove(struct platform_device
*pdev
)
717 pr_debug("Removing platform driver for rtl83xx-sw\n");
721 static const struct of_device_id rtl83xx_switch_of_ids
[] = {
722 { .compatible
= "realtek,rtl83xx-switch"},
727 MODULE_DEVICE_TABLE(of
, rtl83xx_switch_of_ids
);
729 static struct platform_driver rtl83xx_switch_driver
= {
730 .probe
= rtl83xx_sw_probe
,
731 .remove
= rtl83xx_sw_remove
,
733 .name
= "rtl83xx-switch",
735 .of_match_table
= rtl83xx_switch_of_ids
,
739 module_platform_driver(rtl83xx_switch_driver
);
741 MODULE_AUTHOR("B. Koblitz");
742 MODULE_DESCRIPTION("RTL83XX SoC Switch Driver");
743 MODULE_LICENSE("GPL");