1 // SPDX-License-Identifier: GPL-2.0-only
4 #include <linux/if_bridge.h>
6 #include <asm/mach-rtl838x/mach-rtl83xx.h>
10 extern struct rtl83xx_soc_info soc_info
;
13 static void rtl83xx_init_stats(struct rtl838x_switch_priv
*priv
)
15 mutex_lock(&priv
->reg_mutex
);
17 /* Enable statistics module: all counters plus debug.
18 * On RTL839x all counters are enabled by default
20 if (priv
->family_id
== RTL8380_FAMILY_ID
)
21 sw_w32_mask(0, 3, RTL838X_STAT_CTRL
);
23 /* Reset statistics counters */
24 sw_w32_mask(0, 1, priv
->r
->stat_rst
);
26 mutex_unlock(&priv
->reg_mutex
);
29 static void rtl83xx_write_cam(int idx
, u32
*r
)
31 u32 cmd
= BIT(16) /* Execute cmd */
33 | BIT(13) /* Table type 0b01 */
36 sw_w32(r
[0], RTL838X_TBL_ACCESS_L2_DATA(0));
37 sw_w32(r
[1], RTL838X_TBL_ACCESS_L2_DATA(1));
38 sw_w32(r
[2], RTL838X_TBL_ACCESS_L2_DATA(2));
40 sw_w32(cmd
, RTL838X_TBL_ACCESS_L2_CTRL
);
41 do { } while (sw_r32(RTL838X_TBL_ACCESS_L2_CTRL
) & BIT(16));
44 static u64
rtl83xx_hash_key(struct rtl838x_switch_priv
*priv
, u64 mac
, u32 vid
)
46 switch (priv
->family_id
) {
47 case RTL8380_FAMILY_ID
:
48 return rtl838x_hash(priv
, mac
<< 12 | vid
);
49 case RTL8390_FAMILY_ID
:
50 return rtl839x_hash(priv
, mac
<< 12 | vid
);
51 case RTL9300_FAMILY_ID
:
52 return rtl930x_hash(priv
, ((u64
)vid
) << 48 | mac
);
54 pr_err("Hash not implemented\n");
59 static void rtl83xx_write_hash(int idx
, u32
*r
)
61 u32 cmd
= BIT(16) /* Execute cmd */
63 | 0 << 13 /* Table type 0b00 */
66 sw_w32(0, RTL838X_TBL_ACCESS_L2_DATA(0));
67 sw_w32(0, RTL838X_TBL_ACCESS_L2_DATA(1));
68 sw_w32(0, RTL838X_TBL_ACCESS_L2_DATA(2));
69 sw_w32(cmd
, RTL838X_TBL_ACCESS_L2_CTRL
);
70 do { } while (sw_r32(RTL838X_TBL_ACCESS_L2_CTRL
) & BIT(16));
73 static void rtl83xx_enable_phy_polling(struct rtl838x_switch_priv
*priv
)
79 /* Enable all ports with a PHY, including the SFP-ports */
80 for (i
= 0; i
< priv
->cpu_port
; i
++) {
81 if (priv
->ports
[i
].phy
)
85 pr_debug("%s: %16llx\n", __func__
, v
);
86 priv
->r
->set_port_reg_le(v
, priv
->r
->smi_poll_ctrl
);
88 /* PHY update complete, there is no global PHY polling enable bit on the 9300 */
89 if (priv
->family_id
== RTL8390_FAMILY_ID
)
90 sw_w32_mask(0, BIT(7), RTL839X_SMI_GLB_CTRL
);
91 else if(priv
->family_id
== RTL9300_FAMILY_ID
)
92 sw_w32_mask(0, 0x8000, RTL838X_SMI_GLB_CTRL
);
95 const struct rtl83xx_mib_desc rtl83xx_mib
[] = {
96 MIB_DESC(2, 0xf8, "ifInOctets"),
97 MIB_DESC(2, 0xf0, "ifOutOctets"),
98 MIB_DESC(1, 0xec, "dot1dTpPortInDiscards"),
99 MIB_DESC(1, 0xe8, "ifInUcastPkts"),
100 MIB_DESC(1, 0xe4, "ifInMulticastPkts"),
101 MIB_DESC(1, 0xe0, "ifInBroadcastPkts"),
102 MIB_DESC(1, 0xdc, "ifOutUcastPkts"),
103 MIB_DESC(1, 0xd8, "ifOutMulticastPkts"),
104 MIB_DESC(1, 0xd4, "ifOutBroadcastPkts"),
105 MIB_DESC(1, 0xd0, "ifOutDiscards"),
106 MIB_DESC(1, 0xcc, ".3SingleCollisionFrames"),
107 MIB_DESC(1, 0xc8, ".3MultipleCollisionFrames"),
108 MIB_DESC(1, 0xc4, ".3DeferredTransmissions"),
109 MIB_DESC(1, 0xc0, ".3LateCollisions"),
110 MIB_DESC(1, 0xbc, ".3ExcessiveCollisions"),
111 MIB_DESC(1, 0xb8, ".3SymbolErrors"),
112 MIB_DESC(1, 0xb4, ".3ControlInUnknownOpcodes"),
113 MIB_DESC(1, 0xb0, ".3InPauseFrames"),
114 MIB_DESC(1, 0xac, ".3OutPauseFrames"),
115 MIB_DESC(1, 0xa8, "DropEvents"),
116 MIB_DESC(1, 0xa4, "tx_BroadcastPkts"),
117 MIB_DESC(1, 0xa0, "tx_MulticastPkts"),
118 MIB_DESC(1, 0x9c, "CRCAlignErrors"),
119 MIB_DESC(1, 0x98, "tx_UndersizePkts"),
120 MIB_DESC(1, 0x94, "rx_UndersizePkts"),
121 MIB_DESC(1, 0x90, "rx_UndersizedropPkts"),
122 MIB_DESC(1, 0x8c, "tx_OversizePkts"),
123 MIB_DESC(1, 0x88, "rx_OversizePkts"),
124 MIB_DESC(1, 0x84, "Fragments"),
125 MIB_DESC(1, 0x80, "Jabbers"),
126 MIB_DESC(1, 0x7c, "Collisions"),
127 MIB_DESC(1, 0x78, "tx_Pkts64Octets"),
128 MIB_DESC(1, 0x74, "rx_Pkts64Octets"),
129 MIB_DESC(1, 0x70, "tx_Pkts65to127Octets"),
130 MIB_DESC(1, 0x6c, "rx_Pkts65to127Octets"),
131 MIB_DESC(1, 0x68, "tx_Pkts128to255Octets"),
132 MIB_DESC(1, 0x64, "rx_Pkts128to255Octets"),
133 MIB_DESC(1, 0x60, "tx_Pkts256to511Octets"),
134 MIB_DESC(1, 0x5c, "rx_Pkts256to511Octets"),
135 MIB_DESC(1, 0x58, "tx_Pkts512to1023Octets"),
136 MIB_DESC(1, 0x54, "rx_Pkts512to1023Octets"),
137 MIB_DESC(1, 0x50, "tx_Pkts1024to1518Octets"),
138 MIB_DESC(1, 0x4c, "rx_StatsPkts1024to1518Octets"),
139 MIB_DESC(1, 0x48, "tx_Pkts1519toMaxOctets"),
140 MIB_DESC(1, 0x44, "rx_Pkts1519toMaxOctets"),
141 MIB_DESC(1, 0x40, "rxMacDiscards")
148 static enum dsa_tag_protocol
rtl83xx_get_tag_protocol(struct dsa_switch
*ds
, int port
)
150 /* The switch does not tag the frames, instead internally the header
151 * structure for each packet is tagged accordingly.
153 return DSA_TAG_PROTO_TRAILER
;
157 * Initialize all VLANS
159 static void rtl83xx_vlan_setup(struct rtl838x_switch_priv
*priv
)
161 struct rtl838x_vlan_info info
;
164 pr_info("In %s\n", __func__
);
166 priv
->r
->vlan_profile_setup(0);
167 priv
->r
->vlan_profile_setup(1);
168 pr_info("UNKNOWN_MC_PMASK: %016llx\n", priv
->r
->read_mcast_pmask(UNKNOWN_MC_PMASK
));
169 priv
->r
->vlan_profile_dump(0);
171 info
.fid
= 0; // Default Forwarding ID / MSTI
172 info
.hash_uc_fid
= false; // Do not build the L2 lookup hash with FID, but VID
173 info
.hash_mc_fid
= false; // Do the same for Multicast packets
174 info
.profile_id
= 0; // Use default Vlan Profile 0
175 info
.tagged_ports
= 0; // Initially no port members
177 // Initialize all vlans 0-4095
178 for (i
= 0; i
< MAX_VLANS
; i
++)
179 priv
->r
->vlan_set_tagged(i
, &info
);
181 // Set forwarding action based on inner VLAN tag
182 for (i
= 0; i
< priv
->cpu_port
; i
++)
183 priv
->r
->vlan_fwd_on_inner(i
, true);
186 static int rtl83xx_setup(struct dsa_switch
*ds
)
189 struct rtl838x_switch_priv
*priv
= ds
->priv
;
190 u64 port_bitmap
= BIT_ULL(priv
->cpu_port
);
192 pr_debug("%s called\n", __func__
);
194 /* Disable MAC polling the PHY so that we can start configuration */
195 priv
->r
->set_port_reg_le(0ULL, priv
->r
->smi_poll_ctrl
);
197 for (i
= 0; i
< ds
->num_ports
; i
++)
198 priv
->ports
[i
].enable
= false;
199 priv
->ports
[priv
->cpu_port
].enable
= true;
201 /* Isolate ports from each other: traffic only CPU <-> port */
202 /* Setting bit j in register RTL838X_PORT_ISO_CTRL(i) allows
203 * traffic from source port i to destination port j
205 for (i
= 0; i
< priv
->cpu_port
; i
++) {
206 if (priv
->ports
[i
].phy
) {
207 priv
->r
->set_port_reg_be(BIT_ULL(priv
->cpu_port
) | BIT(i
),
208 priv
->r
->port_iso_ctrl(i
));
209 port_bitmap
|= BIT_ULL(i
);
212 priv
->r
->set_port_reg_be(port_bitmap
, priv
->r
->port_iso_ctrl(priv
->cpu_port
));
214 if (priv
->family_id
== RTL8380_FAMILY_ID
)
215 rtl838x_print_matrix();
217 rtl839x_print_matrix();
219 rtl83xx_init_stats(priv
);
221 rtl83xx_vlan_setup(priv
);
223 ds
->configure_vlan_while_not_filtering
= true;
225 /* Enable MAC Polling PHY again */
226 rtl83xx_enable_phy_polling(priv
);
227 pr_debug("Please wait until PHY is settled\n");
232 static int rtl930x_setup(struct dsa_switch
*ds
)
235 struct rtl838x_switch_priv
*priv
= ds
->priv
;
236 u32 port_bitmap
= BIT(priv
->cpu_port
);
238 pr_info("%s called\n", __func__
);
240 // Enable CSTI STP mode
241 // sw_w32(1, RTL930X_ST_CTRL);
243 /* Disable MAC polling the PHY so that we can start configuration */
244 sw_w32(0, RTL930X_SMI_POLL_CTRL
);
246 // Disable all ports except CPU port
247 for (i
= 0; i
< ds
->num_ports
; i
++)
248 priv
->ports
[i
].enable
= false;
249 priv
->ports
[priv
->cpu_port
].enable
= true;
251 for (i
= 0; i
< priv
->cpu_port
; i
++) {
252 if (priv
->ports
[i
].phy
) {
253 priv
->r
->traffic_set(i
, BIT(priv
->cpu_port
) | BIT(i
));
254 port_bitmap
|= 1ULL << i
;
257 priv
->r
->traffic_set(priv
->cpu_port
, port_bitmap
);
259 rtl930x_print_matrix();
261 // TODO: Initialize statistics
263 rtl83xx_vlan_setup(priv
);
265 ds
->configure_vlan_while_not_filtering
= true;
267 rtl83xx_enable_phy_polling(priv
);
272 static void rtl83xx_phylink_validate(struct dsa_switch
*ds
, int port
,
273 unsigned long *supported
,
274 struct phylink_link_state
*state
)
276 struct rtl838x_switch_priv
*priv
= ds
->priv
;
277 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask
) = { 0, };
279 pr_debug("In %s port %d", __func__
, port
);
281 if (!phy_interface_mode_is_rgmii(state
->interface
) &&
282 state
->interface
!= PHY_INTERFACE_MODE_NA
&&
283 state
->interface
!= PHY_INTERFACE_MODE_1000BASEX
&&
284 state
->interface
!= PHY_INTERFACE_MODE_MII
&&
285 state
->interface
!= PHY_INTERFACE_MODE_REVMII
&&
286 state
->interface
!= PHY_INTERFACE_MODE_GMII
&&
287 state
->interface
!= PHY_INTERFACE_MODE_QSGMII
&&
288 state
->interface
!= PHY_INTERFACE_MODE_INTERNAL
&&
289 state
->interface
!= PHY_INTERFACE_MODE_SGMII
) {
290 bitmap_zero(supported
, __ETHTOOL_LINK_MODE_MASK_NBITS
);
292 "Unsupported interface: %d for port %d\n",
293 state
->interface
, port
);
297 /* Allow all the expected bits */
298 phylink_set(mask
, Autoneg
);
299 phylink_set_port_modes(mask
);
300 phylink_set(mask
, Pause
);
301 phylink_set(mask
, Asym_Pause
);
303 /* With the exclusion of MII and Reverse MII, we support Gigabit,
304 * including Half duplex
306 if (state
->interface
!= PHY_INTERFACE_MODE_MII
&&
307 state
->interface
!= PHY_INTERFACE_MODE_REVMII
) {
308 phylink_set(mask
, 1000baseT_Full
);
309 phylink_set(mask
, 1000baseT_Half
);
312 /* On both the 8380 and 8382, ports 24-27 are SFP ports */
313 if (port
>= 24 && port
<= 27 && priv
->family_id
== RTL8380_FAMILY_ID
)
314 phylink_set(mask
, 1000baseX_Full
);
316 phylink_set(mask
, 10baseT_Half
);
317 phylink_set(mask
, 10baseT_Full
);
318 phylink_set(mask
, 100baseT_Half
);
319 phylink_set(mask
, 100baseT_Full
);
321 bitmap_and(supported
, supported
, mask
,
322 __ETHTOOL_LINK_MODE_MASK_NBITS
);
323 bitmap_and(state
->advertising
, state
->advertising
, mask
,
324 __ETHTOOL_LINK_MODE_MASK_NBITS
);
327 static int rtl83xx_phylink_mac_link_state(struct dsa_switch
*ds
, int port
,
328 struct phylink_link_state
*state
)
330 struct rtl838x_switch_priv
*priv
= ds
->priv
;
334 if (port
< 0 || port
> priv
->cpu_port
)
338 * On the RTL9300 for at least the RTL8226B PHY, the MAC-side link
339 * state needs to be read twice in order to read a correct result.
340 * This would not be necessary for ports connected e.g. to RTL8218D
344 link
= priv
->r
->get_port_reg_le(priv
->r
->mac_link_sts
);
345 link
= priv
->r
->get_port_reg_le(priv
->r
->mac_link_sts
);
346 if (link
& BIT_ULL(port
))
348 pr_debug("%s: link state: %llx\n", __func__
, link
& BIT_ULL(port
));
351 if (priv
->r
->get_port_reg_le(priv
->r
->mac_link_dup_sts
) & BIT_ULL(port
))
354 speed
= priv
->r
->get_port_reg_le(priv
->r
->mac_link_spd_sts(port
));
355 speed
>>= (port
% 16) << 1;
356 switch (speed
& 0x3) {
358 state
->speed
= SPEED_10
;
361 state
->speed
= SPEED_100
;
364 state
->speed
= SPEED_1000
;
367 if (port
== 24 || port
== 26) /* Internal serdes */
368 state
->speed
= SPEED_2500
;
370 state
->speed
= SPEED_100
; /* Is in fact 500Mbit */
373 state
->pause
&= (MLO_PAUSE_RX
| MLO_PAUSE_TX
);
374 if (priv
->r
->get_port_reg_le(priv
->r
->mac_rx_pause_sts
) & BIT_ULL(port
))
375 state
->pause
|= MLO_PAUSE_RX
;
376 if (priv
->r
->get_port_reg_le(priv
->r
->mac_tx_pause_sts
) & BIT_ULL(port
))
377 state
->pause
|= MLO_PAUSE_TX
;
382 static void rtl83xx_config_interface(int port
, phy_interface_t interface
)
384 u32 old
, int_shift
, sds_shift
;
399 old
= sw_r32(RTL838X_SDS_MODE_SEL
);
401 case PHY_INTERFACE_MODE_1000BASEX
:
402 if ((old
>> sds_shift
& 0x1f) == 4)
404 sw_w32_mask(0x7 << int_shift
, 1 << int_shift
, RTL838X_INT_MODE_CTRL
);
405 sw_w32_mask(0x1f << sds_shift
, 4 << sds_shift
, RTL838X_SDS_MODE_SEL
);
407 case PHY_INTERFACE_MODE_SGMII
:
408 if ((old
>> sds_shift
& 0x1f) == 2)
410 sw_w32_mask(0x7 << int_shift
, 2 << int_shift
, RTL838X_INT_MODE_CTRL
);
411 sw_w32_mask(0x1f << sds_shift
, 2 << sds_shift
, RTL838X_SDS_MODE_SEL
);
416 pr_debug("configured port %d for interface %s\n", port
, phy_modes(interface
));
419 static void rtl83xx_phylink_mac_config(struct dsa_switch
*ds
, int port
,
421 const struct phylink_link_state
*state
)
423 struct rtl838x_switch_priv
*priv
= ds
->priv
;
425 int speed_bit
= priv
->family_id
== RTL8380_FAMILY_ID
? 4 : 3;
427 pr_debug("%s port %d, mode %x\n", __func__
, port
, mode
);
429 // BUG: Make this work on RTL93XX
430 if (priv
->family_id
>= RTL9300_FAMILY_ID
)
433 if (port
== priv
->cpu_port
) {
434 /* Set Speed, duplex, flow control
435 * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL
436 * | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN
439 if (priv
->family_id
== RTL8380_FAMILY_ID
) {
440 sw_w32(0x6192F, priv
->r
->mac_force_mode_ctrl(priv
->cpu_port
));
441 /* allow CRC errors on CPU-port */
442 sw_w32_mask(0, 0x8, RTL838X_MAC_PORT_CTRL(priv
->cpu_port
));
444 sw_w32_mask(0, 3, priv
->r
->mac_force_mode_ctrl(priv
->cpu_port
));
449 reg
= sw_r32(priv
->r
->mac_force_mode_ctrl(port
));
450 /* Auto-Negotiation does not work for MAC in RTL8390 */
451 if (priv
->family_id
== RTL8380_FAMILY_ID
) {
452 if (mode
== MLO_AN_PHY
|| phylink_autoneg_inband(mode
)) {
453 pr_debug("PHY autonegotiates\n");
455 sw_w32(reg
, priv
->r
->mac_force_mode_ctrl(port
));
456 rtl83xx_config_interface(port
, state
->interface
);
461 if (mode
!= MLO_AN_FIXED
)
462 pr_debug("Fixed state.\n");
464 if (priv
->family_id
== RTL8380_FAMILY_ID
) {
465 /* Clear id_mode_dis bit, and the existing port mode, let
466 * RGMII_MODE_EN bet set by mac_link_{up,down}
468 reg
&= ~(RX_PAUSE_EN
| TX_PAUSE_EN
);
470 if (state
->pause
& MLO_PAUSE_TXRX_MASK
) {
471 if (state
->pause
& MLO_PAUSE_TX
)
477 reg
&= ~(3 << speed_bit
);
478 switch (state
->speed
) {
480 reg
|= 2 << speed_bit
;
483 reg
|= 1 << speed_bit
;
487 if (priv
->family_id
== RTL8380_FAMILY_ID
) {
488 reg
&= ~(DUPLEX_FULL
| FORCE_LINK_EN
);
490 reg
|= FORCE_LINK_EN
;
491 if (state
->duplex
== DUPLEX_FULL
)
496 if (priv
->family_id
== RTL8380_FAMILY_ID
)
498 sw_w32(reg
, priv
->r
->mac_force_mode_ctrl(port
));
501 static void rtl83xx_phylink_mac_link_down(struct dsa_switch
*ds
, int port
,
503 phy_interface_t interface
)
505 struct rtl838x_switch_priv
*priv
= ds
->priv
;
506 /* Stop TX/RX to port */
507 sw_w32_mask(0x3, 0, priv
->r
->mac_port_ctrl(port
));
510 static void rtl83xx_phylink_mac_link_up(struct dsa_switch
*ds
, int port
,
512 phy_interface_t interface
,
513 struct phy_device
*phydev
)
515 struct rtl838x_switch_priv
*priv
= ds
->priv
;
516 /* Restart TX/RX to port */
517 sw_w32_mask(0, 0x3, priv
->r
->mac_port_ctrl(port
));
520 static void rtl83xx_get_strings(struct dsa_switch
*ds
,
521 int port
, u32 stringset
, u8
*data
)
525 if (stringset
!= ETH_SS_STATS
)
528 for (i
= 0; i
< ARRAY_SIZE(rtl83xx_mib
); i
++)
529 strncpy(data
+ i
* ETH_GSTRING_LEN
, rtl83xx_mib
[i
].name
,
533 static void rtl83xx_get_ethtool_stats(struct dsa_switch
*ds
, int port
,
536 struct rtl838x_switch_priv
*priv
= ds
->priv
;
537 const struct rtl83xx_mib_desc
*mib
;
541 for (i
= 0; i
< ARRAY_SIZE(rtl83xx_mib
); i
++) {
542 mib
= &rtl83xx_mib
[i
];
544 data
[i
] = sw_r32(priv
->r
->stat_port_std_mib
+ (port
<< 8) + 252 - mib
->offset
);
545 if (mib
->size
== 2) {
546 h
= sw_r32(priv
->r
->stat_port_std_mib
+ (port
<< 8) + 248 - mib
->offset
);
552 static int rtl83xx_get_sset_count(struct dsa_switch
*ds
, int port
, int sset
)
554 if (sset
!= ETH_SS_STATS
)
557 return ARRAY_SIZE(rtl83xx_mib
);
560 static int rtl83xx_port_enable(struct dsa_switch
*ds
, int port
,
561 struct phy_device
*phydev
)
563 struct rtl838x_switch_priv
*priv
= ds
->priv
;
566 pr_debug("%s: %x %d", __func__
, (u32
) priv
, port
);
567 priv
->ports
[port
].enable
= true;
569 /* enable inner tagging on egress, do not keep any tags */
570 if (priv
->family_id
== RTL9310_FAMILY_ID
)
571 sw_w32(BIT(4), priv
->r
->vlan_port_tag_sts_ctrl
+ (port
<< 2));
573 sw_w32(1, priv
->r
->vlan_port_tag_sts_ctrl
+ (port
<< 2));
575 if (dsa_is_cpu_port(ds
, port
))
578 /* add port to switch mask of CPU_PORT */
579 priv
->r
->traffic_enable(priv
->cpu_port
, port
);
581 /* add all other ports in the same bridge to switch mask of port */
582 v
= priv
->r
->traffic_get(port
);
583 v
|= priv
->ports
[port
].pm
;
584 priv
->r
->traffic_set(port
, v
);
586 sw_w32_mask(0, BIT(port
), RTL930X_L2_PORT_SABLK_CTRL
);
587 sw_w32_mask(0, BIT(port
), RTL930X_L2_PORT_DABLK_CTRL
);
592 static void rtl83xx_port_disable(struct dsa_switch
*ds
, int port
)
594 struct rtl838x_switch_priv
*priv
= ds
->priv
;
597 pr_debug("%s %x: %d", __func__
, (u32
)priv
, port
);
598 /* you can only disable user ports */
599 if (!dsa_is_user_port(ds
, port
))
602 // BUG: This does not work on RTL931X
603 /* remove port from switch mask of CPU_PORT */
604 priv
->r
->traffic_disable(priv
->cpu_port
, port
);
606 /* remove all other ports in the same bridge from switch mask of port */
607 v
= priv
->r
->traffic_get(port
);
608 v
&= ~priv
->ports
[port
].pm
;
609 priv
->r
->traffic_set(port
, v
);
611 priv
->ports
[port
].enable
= false;
614 static int rtl83xx_set_mac_eee(struct dsa_switch
*ds
, int port
,
615 struct ethtool_eee
*e
)
617 struct rtl838x_switch_priv
*priv
= ds
->priv
;
619 if (e
->eee_enabled
&& !priv
->eee_enabled
) {
620 pr_info("Globally enabling EEE\n");
621 priv
->r
->init_eee(priv
, true);
624 priv
->r
->port_eee_set(priv
, port
, e
->eee_enabled
);
627 pr_info("Enabled EEE for port %d\n", port
);
629 pr_info("Disabled EEE for port %d\n", port
);
633 static int rtl83xx_get_mac_eee(struct dsa_switch
*ds
, int port
,
634 struct ethtool_eee
*e
)
636 struct rtl838x_switch_priv
*priv
= ds
->priv
;
638 e
->supported
= SUPPORTED_100baseT_Full
| SUPPORTED_1000baseT_Full
;
640 priv
->r
->eee_port_ability(priv
, e
, port
);
642 e
->eee_enabled
= priv
->ports
[port
].eee_enabled
;
644 e
->eee_active
= !!(e
->advertised
& e
->lp_advertised
);
649 static int rtl93xx_get_mac_eee(struct dsa_switch
*ds
, int port
,
650 struct ethtool_eee
*e
)
652 struct rtl838x_switch_priv
*priv
= ds
->priv
;
654 e
->supported
= SUPPORTED_100baseT_Full
| SUPPORTED_1000baseT_Full
655 | SUPPORTED_2500baseX_Full
;
657 priv
->r
->eee_port_ability(priv
, e
, port
);
659 e
->eee_enabled
= priv
->ports
[port
].eee_enabled
;
661 e
->eee_active
= !!(e
->advertised
& e
->lp_advertised
);
667 * Set Switch L2 Aging time, t is time in milliseconds
668 * t = 0: aging is disabled
670 static int rtl83xx_set_l2aging(struct dsa_switch
*ds
, u32 t
)
672 struct rtl838x_switch_priv
*priv
= ds
->priv
;
673 int t_max
= priv
->family_id
== RTL8380_FAMILY_ID
? 0x7fffff : 0x1FFFFF;
675 /* Convert time in mseconds to internal value */
676 if (t
> 0x10000000) { /* Set to maximum */
679 if (priv
->family_id
== RTL8380_FAMILY_ID
)
680 t
= ((t
* 625) / 1000 + 127) / 128;
684 sw_w32(t
, priv
->r
->l2_ctrl_1
);
688 static int rtl83xx_port_bridge_join(struct dsa_switch
*ds
, int port
,
689 struct net_device
*bridge
)
691 struct rtl838x_switch_priv
*priv
= ds
->priv
;
692 u64 port_bitmap
= 1ULL << priv
->cpu_port
, v
;
695 pr_debug("%s %x: %d %llx", __func__
, (u32
)priv
, port
, port_bitmap
);
696 mutex_lock(&priv
->reg_mutex
);
697 for (i
= 0; i
< ds
->num_ports
; i
++) {
698 /* Add this port to the port matrix of the other ports in the
699 * same bridge. If the port is disabled, port matrix is kept
700 * and not being setup until the port becomes enabled.
702 if (dsa_is_user_port(ds
, i
) && i
!= port
) {
703 if (dsa_to_port(ds
, i
)->bridge_dev
!= bridge
)
705 if (priv
->ports
[i
].enable
)
706 priv
->r
->traffic_enable(i
, port
);
708 priv
->ports
[i
].pm
|= 1ULL << port
;
709 port_bitmap
|= 1ULL << i
;
713 /* Add all other ports to this port matrix. */
714 if (priv
->ports
[port
].enable
) {
715 priv
->r
->traffic_enable(priv
->cpu_port
, port
);
716 v
= priv
->r
->traffic_get(port
);
718 priv
->r
->traffic_set(port
, v
);
720 priv
->ports
[port
].pm
|= port_bitmap
;
721 mutex_unlock(&priv
->reg_mutex
);
726 static void rtl83xx_port_bridge_leave(struct dsa_switch
*ds
, int port
,
727 struct net_device
*bridge
)
729 struct rtl838x_switch_priv
*priv
= ds
->priv
;
730 u64 port_bitmap
= 1ULL << priv
->cpu_port
, v
;
733 pr_debug("%s %x: %d", __func__
, (u32
)priv
, port
);
734 mutex_lock(&priv
->reg_mutex
);
735 for (i
= 0; i
< ds
->num_ports
; i
++) {
736 /* Remove this port from the port matrix of the other ports
737 * in the same bridge. If the port is disabled, port matrix
738 * is kept and not being setup until the port becomes enabled.
739 * And the other port's port matrix cannot be broken when the
740 * other port is still a VLAN-aware port.
742 if (dsa_is_user_port(ds
, i
) && i
!= port
) {
743 if (dsa_to_port(ds
, i
)->bridge_dev
!= bridge
)
745 if (priv
->ports
[i
].enable
)
746 priv
->r
->traffic_disable(i
, port
);
748 priv
->ports
[i
].pm
|= 1ULL << port
;
749 port_bitmap
&= ~BIT_ULL(i
);
753 /* Add all other ports to this port matrix. */
754 if (priv
->ports
[port
].enable
) {
755 v
= priv
->r
->traffic_get(port
);
757 priv
->r
->traffic_set(port
, v
);
759 priv
->ports
[port
].pm
&= ~port_bitmap
;
761 mutex_unlock(&priv
->reg_mutex
);
764 void rtl83xx_port_stp_state_set(struct dsa_switch
*ds
, int port
, u8 state
)
770 struct rtl838x_switch_priv
*priv
= ds
->priv
;
771 int n
= priv
->port_width
<< 1;
773 /* Ports above or equal CPU port can never be configured */
774 if (port
>= priv
->cpu_port
)
777 mutex_lock(&priv
->reg_mutex
);
779 /* For the RTL839x and following, the bits are left-aligned, 838x and 930x
780 * have 64 bit fields, 839x and 931x have 128 bit fields
782 if (priv
->family_id
== RTL8390_FAMILY_ID
)
784 if (priv
->family_id
== RTL9300_FAMILY_ID
)
786 if (priv
->family_id
== RTL9310_FAMILY_ID
)
789 index
= n
- (pos
>> 4) - 1;
790 bit
= (pos
<< 1) % 32;
792 priv
->r
->stp_get(priv
, msti
, port_state
);
794 pr_debug("Current state, port %d: %d\n", port
, (port_state
[index
] >> bit
) & 3);
795 port_state
[index
] &= ~(3 << bit
);
798 case BR_STATE_DISABLED
: /* 0 */
799 port_state
[index
] |= (0 << bit
);
801 case BR_STATE_BLOCKING
: /* 4 */
802 case BR_STATE_LISTENING
: /* 1 */
803 port_state
[index
] |= (1 << bit
);
805 case BR_STATE_LEARNING
: /* 2 */
806 port_state
[index
] |= (2 << bit
);
808 case BR_STATE_FORWARDING
: /* 3*/
809 port_state
[index
] |= (3 << bit
);
814 priv
->r
->stp_set(priv
, msti
, port_state
);
816 mutex_unlock(&priv
->reg_mutex
);
819 void rtl83xx_fast_age(struct dsa_switch
*ds
, int port
)
821 struct rtl838x_switch_priv
*priv
= ds
->priv
;
822 int s
= priv
->family_id
== RTL8390_FAMILY_ID
? 2 : 0;
824 pr_debug("FAST AGE port %d\n", port
);
825 mutex_lock(&priv
->reg_mutex
);
826 /* RTL838X_L2_TBL_FLUSH_CTRL register bits, 839x has 1 bit larger
828 * 0-4: Replacing port
829 * 5-9: Flushed/replaced port
831 * 22: Entry types: 1: dynamic, 0: also static
832 * 23: Match flush port
834 * 25: Flush (0) or replace (1) L2 entries
835 * 26: Status of action (1: Start, 0: Done)
837 sw_w32(1 << (26 + s
) | 1 << (23 + s
) | port
<< (5 + (s
/ 2)), priv
->r
->l2_tbl_flush_ctrl
);
839 do { } while (sw_r32(priv
->r
->l2_tbl_flush_ctrl
) & BIT(26 + s
));
841 mutex_unlock(&priv
->reg_mutex
);
844 void rtl930x_fast_age(struct dsa_switch
*ds
, int port
)
846 struct rtl838x_switch_priv
*priv
= ds
->priv
;
848 pr_debug("FAST AGE port %d\n", port
);
849 mutex_lock(&priv
->reg_mutex
);
850 sw_w32(port
<< 11, RTL930X_L2_TBL_FLUSH_CTRL
+ 4);
852 sw_w32(BIT(26) | BIT(30), RTL930X_L2_TBL_FLUSH_CTRL
);
854 do { } while (sw_r32(priv
->r
->l2_tbl_flush_ctrl
) & BIT(30));
856 mutex_unlock(&priv
->reg_mutex
);
859 static int rtl83xx_vlan_filtering(struct dsa_switch
*ds
, int port
,
862 struct rtl838x_switch_priv
*priv
= ds
->priv
;
864 pr_debug("%s: port %d\n", __func__
, port
);
865 mutex_lock(&priv
->reg_mutex
);
867 if (vlan_filtering
) {
868 /* Enable ingress and egress filtering
869 * The VLAN_PORT_IGR_FILTER register uses 2 bits for each port to define
873 * 2: Trap packet to CPU port
874 * The Egress filter used 1 bit per state (0: DISABLED, 1: ENABLED)
876 if (port
!= priv
->cpu_port
)
877 sw_w32_mask(0b10 << ((port
% 16) << 1), 0b01 << ((port
% 16) << 1),
878 priv
->r
->vlan_port_igr_filter
+ ((port
>> 5) << 2));
879 sw_w32_mask(0, BIT(port
% 32), priv
->r
->vlan_port_egr_filter
+ ((port
>> 4) << 2));
881 /* Disable ingress and egress filtering */
882 if (port
!= priv
->cpu_port
)
883 sw_w32_mask(0b11 << ((port
% 16) << 1), 0,
884 priv
->r
->vlan_port_igr_filter
+ ((port
>> 5) << 2));
885 sw_w32_mask(BIT(port
% 32), 0, priv
->r
->vlan_port_egr_filter
+ ((port
>> 4) << 2));
888 /* Do we need to do something to the CPU-Port, too? */
889 mutex_unlock(&priv
->reg_mutex
);
894 static int rtl83xx_vlan_prepare(struct dsa_switch
*ds
, int port
,
895 const struct switchdev_obj_port_vlan
*vlan
)
897 struct rtl838x_vlan_info info
;
898 struct rtl838x_switch_priv
*priv
= ds
->priv
;
900 pr_info("%s: port %d\n", __func__
, port
);
902 mutex_lock(&priv
->reg_mutex
);
904 priv
->r
->vlan_profile_dump(1);
905 priv
->r
->vlan_tables_read(1, &info
);
907 pr_info("Tagged ports %llx, untag %llx, prof %x, MC# %d, UC# %d, FID %x\n",
908 info
.tagged_ports
, info
.untagged_ports
, info
.profile_id
,
909 info
.hash_mc_fid
, info
.hash_uc_fid
, info
.fid
);
911 priv
->r
->vlan_set_untagged(1, info
.untagged_ports
);
912 pr_debug("SET: Untagged ports, VLAN %d: %llx\n", 1, info
.untagged_ports
);
914 priv
->r
->vlan_set_tagged(1, &info
);
915 pr_debug("SET: Tagged ports, VLAN %d: %llx\n", 1, info
.tagged_ports
);
917 mutex_unlock(&priv
->reg_mutex
);
921 static void rtl83xx_vlan_add(struct dsa_switch
*ds
, int port
,
922 const struct switchdev_obj_port_vlan
*vlan
)
924 struct rtl838x_vlan_info info
;
925 struct rtl838x_switch_priv
*priv
= ds
->priv
;
928 pr_info("%s port %d, vid_end %d, vid_end %d, flags %x\n", __func__
,
929 port
, vlan
->vid_begin
, vlan
->vid_end
, vlan
->flags
);
931 if (vlan
->vid_begin
> 4095 || vlan
->vid_end
> 4095) {
932 dev_err(priv
->dev
, "VLAN out of range: %d - %d",
933 vlan
->vid_begin
, vlan
->vid_end
);
937 mutex_lock(&priv
->reg_mutex
);
939 if (vlan
->flags
& BRIDGE_VLAN_INFO_PVID
) {
940 for (v
= vlan
->vid_begin
; v
<= vlan
->vid_end
; v
++) {
943 /* Set both inner and outer PVID of the port */
944 sw_w32((v
<< 16) | v
<< 2, priv
->r
->vlan_port_pb
+ (port
<< 2));
945 priv
->ports
[port
].pvid
= vlan
->vid_end
;
949 for (v
= vlan
->vid_begin
; v
<= vlan
->vid_end
; v
++) {
953 /* Get port memberships of this vlan */
954 priv
->r
->vlan_tables_read(v
, &info
);
957 if (!info
.tagged_ports
) {
959 info
.hash_mc_fid
= false;
960 info
.hash_uc_fid
= false;
964 /* sanitize untagged_ports - must be a subset */
965 if (info
.untagged_ports
& ~info
.tagged_ports
)
966 info
.untagged_ports
= 0;
968 info
.tagged_ports
|= BIT_ULL(port
);
969 if (vlan
->flags
& BRIDGE_VLAN_INFO_UNTAGGED
)
970 info
.untagged_ports
|= BIT_ULL(port
);
972 priv
->r
->vlan_set_untagged(v
, info
.untagged_ports
);
973 pr_info("Untagged ports, VLAN %d: %llx\n", v
, info
.untagged_ports
);
975 priv
->r
->vlan_set_tagged(v
, &info
);
976 pr_info("Tagged ports, VLAN %d: %llx\n", v
, info
.tagged_ports
);
979 mutex_unlock(&priv
->reg_mutex
);
982 static int rtl83xx_vlan_del(struct dsa_switch
*ds
, int port
,
983 const struct switchdev_obj_port_vlan
*vlan
)
985 struct rtl838x_vlan_info info
;
986 struct rtl838x_switch_priv
*priv
= ds
->priv
;
990 pr_debug("%s: port %d, vid_end %d, vid_end %d, flags %x\n", __func__
,
991 port
, vlan
->vid_begin
, vlan
->vid_end
, vlan
->flags
);
993 if (vlan
->vid_begin
> 4095 || vlan
->vid_end
> 4095) {
994 dev_err(priv
->dev
, "VLAN out of range: %d - %d",
995 vlan
->vid_begin
, vlan
->vid_end
);
999 mutex_lock(&priv
->reg_mutex
);
1000 pvid
= priv
->ports
[port
].pvid
;
1002 for (v
= vlan
->vid_begin
; v
<= vlan
->vid_end
; v
++) {
1003 /* Reset to default if removing the current PVID */
1005 sw_w32(0, priv
->r
->vlan_port_pb
+ (port
<< 2));
1007 /* Get port memberships of this vlan */
1008 priv
->r
->vlan_tables_read(v
, &info
);
1010 /* remove port from both tables */
1011 info
.untagged_ports
&= (~BIT_ULL(port
));
1012 /* always leave vid 1 */
1014 info
.tagged_ports
&= (~BIT_ULL(port
));
1016 priv
->r
->vlan_set_untagged(v
, info
.untagged_ports
);
1017 pr_debug("Untagged ports, VLAN %d: %llx\n", v
, info
.untagged_ports
);
1019 priv
->r
->vlan_set_tagged(v
, &info
);
1020 pr_debug("Tagged ports, VLAN %d: %llx\n", v
, info
.tagged_ports
);
1022 mutex_unlock(&priv
->reg_mutex
);
1027 static int rtl83xx_port_fdb_add(struct dsa_switch
*ds
, int port
,
1028 const unsigned char *addr
, u16 vid
)
1030 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1031 u64 mac
= ether_addr_to_u64(addr
);
1032 u32 key
= rtl83xx_hash_key(priv
, mac
, vid
);
1033 struct rtl838x_l2_entry e
;
1036 int idx
= -1, err
= 0, i
;
1038 mutex_lock(&priv
->reg_mutex
);
1039 for (i
= 0; i
< 4; i
++) {
1040 entry
= priv
->r
->read_l2_entry_using_hash(key
, i
, &e
);
1042 idx
= (key
<< 2) | i
;
1045 if ((entry
& 0x0fffffffffffffffULL
) == ((mac
<< 12) | vid
)) {
1046 idx
= (key
<< 2) | i
;
1051 r
[0] = 3 << 17 | port
<< 12; // Aging and port
1054 r
[2] = (mac
& 0xffff) << 12; /* rvid = 0 */
1055 rtl83xx_write_hash(idx
, r
);
1059 /* Hash buckets full, try CAM */
1060 for (i
= 0; i
< 64; i
++) {
1061 entry
= priv
->r
->read_cam(i
, &e
);
1063 if (idx
< 0) /* First empty entry? */
1066 } else if ((entry
& 0x0fffffffffffffffULL
) == ((mac
<< 12) | vid
)) {
1067 pr_debug("Found entry in CAM\n");
1073 r
[0] = 3 << 17 | port
<< 12; // Aging
1076 r
[2] = (mac
& 0xffff) << 12; /* rvid = 0 */
1077 rtl83xx_write_cam(idx
, r
);
1082 mutex_unlock(&priv
->reg_mutex
);
1086 static int rtl83xx_port_fdb_del(struct dsa_switch
*ds
, int port
,
1087 const unsigned char *addr
, u16 vid
)
1089 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1090 u64 mac
= ether_addr_to_u64(addr
);
1091 u32 key
= rtl83xx_hash_key(priv
, mac
, vid
);
1092 struct rtl838x_l2_entry e
;
1095 int idx
= -1, err
= 0, i
;
1097 pr_debug("In %s, mac %llx, vid: %d, key: %x08x\n", __func__
, mac
, vid
, key
);
1098 mutex_lock(&priv
->reg_mutex
);
1099 for (i
= 0; i
< 4; i
++) {
1100 entry
= priv
->r
->read_l2_entry_using_hash(key
, i
, &e
);
1103 if ((entry
& 0x0fffffffffffffffULL
) == ((mac
<< 12) | vid
)) {
1104 idx
= (key
<< 2) | i
;
1110 r
[0] = r
[1] = r
[2] = 0;
1111 rtl83xx_write_hash(idx
, r
);
1115 /* Check CAM for spillover from hash buckets */
1116 for (i
= 0; i
< 64; i
++) {
1117 entry
= priv
->r
->read_cam(i
, &e
);
1118 if ((entry
& 0x0fffffffffffffffULL
) == ((mac
<< 12) | vid
)) {
1124 r
[0] = r
[1] = r
[2] = 0;
1125 rtl83xx_write_cam(idx
, r
);
1130 mutex_unlock(&priv
->reg_mutex
);
1134 static int rtl83xx_port_fdb_dump(struct dsa_switch
*ds
, int port
,
1135 dsa_fdb_dump_cb_t
*cb
, void *data
)
1137 struct rtl838x_l2_entry e
;
1138 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1144 mutex_lock(&priv
->reg_mutex
);
1146 for (i
= 0; i
< priv
->fib_entries
; i
++) {
1147 priv
->r
->read_l2_entry_using_hash(i
>> 2, i
& 0x3, &e
);
1152 if (e
.port
== port
) {
1153 fid
= (i
& 0x3ff) | (e
.rvid
& ~0x3ff);
1154 mac
= ether_addr_to_u64(&e
.mac
[0]);
1155 pkey
= rtl838x_hash(priv
, mac
<< 12 | fid
);
1156 fid
= (pkey
& 0x3ff) | (fid
& ~0x3ff);
1157 pr_debug("-> mac %016llx, fid: %d\n", mac
, fid
);
1158 cb(e
.mac
, e
.vid
, e
.is_static
, data
);
1162 for (i
= 0; i
< 64; i
++) {
1163 priv
->r
->read_cam(i
, &e
);
1169 cb(e
.mac
, e
.vid
, e
.is_static
, data
);
1172 mutex_unlock(&priv
->reg_mutex
);
1176 static int rtl83xx_port_mirror_add(struct dsa_switch
*ds
, int port
,
1177 struct dsa_mall_mirror_tc_entry
*mirror
,
1180 /* We support 4 mirror groups, one destination port per group */
1182 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1183 int ctrl_reg
, dpm_reg
, spm_reg
;
1185 pr_debug("In %s\n", __func__
);
1187 for (group
= 0; group
< 4; group
++) {
1188 if (priv
->mirror_group_ports
[group
] == mirror
->to_local_port
)
1192 for (group
= 0; group
< 4; group
++) {
1193 if (priv
->mirror_group_ports
[group
] < 0)
1201 ctrl_reg
= priv
->r
->mir_ctrl
+ group
* 4;
1202 dpm_reg
= priv
->r
->mir_dpm
+ group
* 4 * priv
->port_width
;
1203 spm_reg
= priv
->r
->mir_spm
+ group
* 4 * priv
->port_width
;
1205 pr_debug("Using group %d\n", group
);
1206 mutex_lock(&priv
->reg_mutex
);
1208 if (priv
->family_id
== RTL8380_FAMILY_ID
) {
1209 /* Enable mirroring to port across VLANs (bit 11) */
1210 sw_w32(1 << 11 | (mirror
->to_local_port
<< 4) | 1, ctrl_reg
);
1212 /* Enable mirroring to destination port */
1213 sw_w32((mirror
->to_local_port
<< 4) | 1, ctrl_reg
);
1216 if (ingress
&& (priv
->r
->get_port_reg_be(spm_reg
) & (1ULL << port
))) {
1217 mutex_unlock(&priv
->reg_mutex
);
1220 if ((!ingress
) && (priv
->r
->get_port_reg_be(dpm_reg
) & (1ULL << port
))) {
1221 mutex_unlock(&priv
->reg_mutex
);
1226 priv
->r
->mask_port_reg_be(0, 1ULL << port
, spm_reg
);
1228 priv
->r
->mask_port_reg_be(0, 1ULL << port
, dpm_reg
);
1230 priv
->mirror_group_ports
[group
] = mirror
->to_local_port
;
1231 mutex_unlock(&priv
->reg_mutex
);
1235 static void rtl83xx_port_mirror_del(struct dsa_switch
*ds
, int port
,
1236 struct dsa_mall_mirror_tc_entry
*mirror
)
1239 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1240 int ctrl_reg
, dpm_reg
, spm_reg
;
1242 pr_debug("In %s\n", __func__
);
1243 for (group
= 0; group
< 4; group
++) {
1244 if (priv
->mirror_group_ports
[group
] == mirror
->to_local_port
)
1250 ctrl_reg
= priv
->r
->mir_ctrl
+ group
* 4;
1251 dpm_reg
= priv
->r
->mir_dpm
+ group
* 4 * priv
->port_width
;
1252 spm_reg
= priv
->r
->mir_spm
+ group
* 4 * priv
->port_width
;
1254 mutex_lock(&priv
->reg_mutex
);
1255 if (mirror
->ingress
) {
1256 /* Ingress, clear source port matrix */
1257 priv
->r
->mask_port_reg_be(1ULL << port
, 0, spm_reg
);
1259 /* Egress, clear destination port matrix */
1260 priv
->r
->mask_port_reg_be(1ULL << port
, 0, dpm_reg
);
1263 if (!(sw_r32(spm_reg
) || sw_r32(dpm_reg
))) {
1264 priv
->mirror_group_ports
[group
] = -1;
1265 sw_w32(0, ctrl_reg
);
1268 mutex_unlock(&priv
->reg_mutex
);
1271 int dsa_phy_read(struct dsa_switch
*ds
, int phy_addr
, int phy_reg
)
1275 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1277 if (phy_addr
>= 24 && phy_addr
<= 27
1278 && priv
->ports
[24].phy
== PHY_RTL838X_SDS
) {
1281 val
= sw_r32(RTL838X_SDS4_FIB_REG0
+ offset
+ (phy_reg
<< 2)) & 0xffff;
1285 read_phy(phy_addr
, 0, phy_reg
, &val
);
1289 int dsa_phy_write(struct dsa_switch
*ds
, int phy_addr
, int phy_reg
, u16 val
)
1292 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1294 if (phy_addr
>= 24 && phy_addr
<= 27
1295 && priv
->ports
[24].phy
== PHY_RTL838X_SDS
) {
1298 sw_w32(val
, RTL838X_SDS4_FIB_REG0
+ offset
+ (phy_reg
<< 2));
1301 return write_phy(phy_addr
, 0, phy_reg
, val
);
1304 const struct dsa_switch_ops rtl83xx_switch_ops
= {
1305 .get_tag_protocol
= rtl83xx_get_tag_protocol
,
1306 .setup
= rtl83xx_setup
,
1308 .phy_read
= dsa_phy_read
,
1309 .phy_write
= dsa_phy_write
,
1311 .phylink_validate
= rtl83xx_phylink_validate
,
1312 .phylink_mac_link_state
= rtl83xx_phylink_mac_link_state
,
1313 .phylink_mac_config
= rtl83xx_phylink_mac_config
,
1314 .phylink_mac_link_down
= rtl83xx_phylink_mac_link_down
,
1315 .phylink_mac_link_up
= rtl83xx_phylink_mac_link_up
,
1317 .get_strings
= rtl83xx_get_strings
,
1318 .get_ethtool_stats
= rtl83xx_get_ethtool_stats
,
1319 .get_sset_count
= rtl83xx_get_sset_count
,
1321 .port_enable
= rtl83xx_port_enable
,
1322 .port_disable
= rtl83xx_port_disable
,
1324 .get_mac_eee
= rtl83xx_get_mac_eee
,
1325 .set_mac_eee
= rtl83xx_set_mac_eee
,
1327 .set_ageing_time
= rtl83xx_set_l2aging
,
1328 .port_bridge_join
= rtl83xx_port_bridge_join
,
1329 .port_bridge_leave
= rtl83xx_port_bridge_leave
,
1330 .port_stp_state_set
= rtl83xx_port_stp_state_set
,
1331 .port_fast_age
= rtl83xx_fast_age
,
1333 .port_vlan_filtering
= rtl83xx_vlan_filtering
,
1334 .port_vlan_prepare
= rtl83xx_vlan_prepare
,
1335 .port_vlan_add
= rtl83xx_vlan_add
,
1336 .port_vlan_del
= rtl83xx_vlan_del
,
1338 .port_fdb_add
= rtl83xx_port_fdb_add
,
1339 .port_fdb_del
= rtl83xx_port_fdb_del
,
1340 .port_fdb_dump
= rtl83xx_port_fdb_dump
,
1342 .port_mirror_add
= rtl83xx_port_mirror_add
,
1343 .port_mirror_del
= rtl83xx_port_mirror_del
,
1346 const struct dsa_switch_ops rtl930x_switch_ops
= {
1347 .get_tag_protocol
= rtl83xx_get_tag_protocol
,
1348 .setup
= rtl930x_setup
,
1350 .phy_read
= dsa_phy_read
,
1351 .phy_write
= dsa_phy_write
,
1353 .phylink_validate
= rtl83xx_phylink_validate
,
1354 .phylink_mac_link_state
= rtl83xx_phylink_mac_link_state
,
1355 .phylink_mac_config
= rtl83xx_phylink_mac_config
,
1356 .phylink_mac_link_down
= rtl83xx_phylink_mac_link_down
,
1357 .phylink_mac_link_up
= rtl83xx_phylink_mac_link_up
,
1359 .get_strings
= rtl83xx_get_strings
,
1360 .get_ethtool_stats
= rtl83xx_get_ethtool_stats
,
1361 .get_sset_count
= rtl83xx_get_sset_count
,
1363 .port_enable
= rtl83xx_port_enable
,
1364 .port_disable
= rtl83xx_port_disable
,
1366 .get_mac_eee
= rtl93xx_get_mac_eee
,
1367 .set_mac_eee
= rtl83xx_set_mac_eee
,
1369 .set_ageing_time
= rtl83xx_set_l2aging
,
1370 .port_bridge_join
= rtl83xx_port_bridge_join
,
1371 .port_bridge_leave
= rtl83xx_port_bridge_leave
,
1372 .port_stp_state_set
= rtl83xx_port_stp_state_set
,
1373 .port_fast_age
= rtl930x_fast_age
,
1375 .port_vlan_filtering
= rtl83xx_vlan_filtering
,
1376 .port_vlan_prepare
= rtl83xx_vlan_prepare
,
1377 .port_vlan_add
= rtl83xx_vlan_add
,
1378 .port_vlan_del
= rtl83xx_vlan_del
,
1380 .port_fdb_add
= rtl83xx_port_fdb_add
,
1381 .port_fdb_del
= rtl83xx_port_fdb_del
,
1382 .port_fdb_dump
= rtl83xx_port_fdb_dump
,