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[openwrt/staging/rmilecki.git] / target / linux / realtek / files-5.4 / drivers / net / dsa / rtl83xx / dsa.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <net/dsa.h>
4 #include <linux/if_bridge.h>
5
6 #include <asm/mach-rtl838x/mach-rtl83xx.h>
7 #include "rtl83xx.h"
8
9
10 extern struct rtl83xx_soc_info soc_info;
11
12
13 static void rtl83xx_init_stats(struct rtl838x_switch_priv *priv)
14 {
15 mutex_lock(&priv->reg_mutex);
16
17 /* Enable statistics module: all counters plus debug.
18 * On RTL839x all counters are enabled by default
19 */
20 if (priv->family_id == RTL8380_FAMILY_ID)
21 sw_w32_mask(0, 3, RTL838X_STAT_CTRL);
22
23 /* Reset statistics counters */
24 sw_w32_mask(0, 1, priv->r->stat_rst);
25
26 mutex_unlock(&priv->reg_mutex);
27 }
28
29 static void rtl83xx_write_cam(int idx, u32 *r)
30 {
31 u32 cmd = BIT(16) /* Execute cmd */
32 | BIT(15) /* Read */
33 | BIT(13) /* Table type 0b01 */
34 | (idx & 0x3f);
35
36 sw_w32(r[0], RTL838X_TBL_ACCESS_L2_DATA(0));
37 sw_w32(r[1], RTL838X_TBL_ACCESS_L2_DATA(1));
38 sw_w32(r[2], RTL838X_TBL_ACCESS_L2_DATA(2));
39
40 sw_w32(cmd, RTL838X_TBL_ACCESS_L2_CTRL);
41 do { } while (sw_r32(RTL838X_TBL_ACCESS_L2_CTRL) & BIT(16));
42 }
43
44 static u64 rtl83xx_hash_key(struct rtl838x_switch_priv *priv, u64 mac, u32 vid)
45 {
46 switch (priv->family_id) {
47 case RTL8380_FAMILY_ID:
48 return rtl838x_hash(priv, mac << 12 | vid);
49 case RTL8390_FAMILY_ID:
50 return rtl839x_hash(priv, mac << 12 | vid);
51 case RTL9300_FAMILY_ID:
52 return rtl930x_hash(priv, ((u64)vid) << 48 | mac);
53 default:
54 pr_err("Hash not implemented\n");
55 }
56 return 0;
57 }
58
59 static void rtl83xx_write_hash(int idx, u32 *r)
60 {
61 u32 cmd = BIT(16) /* Execute cmd */
62 | 0 << 15 /* Write */
63 | 0 << 13 /* Table type 0b00 */
64 | (idx & 0x1fff);
65
66 sw_w32(0, RTL838X_TBL_ACCESS_L2_DATA(0));
67 sw_w32(0, RTL838X_TBL_ACCESS_L2_DATA(1));
68 sw_w32(0, RTL838X_TBL_ACCESS_L2_DATA(2));
69 sw_w32(cmd, RTL838X_TBL_ACCESS_L2_CTRL);
70 do { } while (sw_r32(RTL838X_TBL_ACCESS_L2_CTRL) & BIT(16));
71 }
72
73 static void rtl83xx_enable_phy_polling(struct rtl838x_switch_priv *priv)
74 {
75 int i;
76 u64 v = 0;
77
78 msleep(1000);
79 /* Enable all ports with a PHY, including the SFP-ports */
80 for (i = 0; i < priv->cpu_port; i++) {
81 if (priv->ports[i].phy)
82 v |= BIT(i);
83 }
84
85 pr_debug("%s: %16llx\n", __func__, v);
86 priv->r->set_port_reg_le(v, priv->r->smi_poll_ctrl);
87
88 /* PHY update complete, there is no global PHY polling enable bit on the 9300 */
89 if (priv->family_id == RTL8390_FAMILY_ID)
90 sw_w32_mask(0, BIT(7), RTL839X_SMI_GLB_CTRL);
91 else if(priv->family_id == RTL9300_FAMILY_ID)
92 sw_w32_mask(0, 0x8000, RTL838X_SMI_GLB_CTRL);
93 }
94
95 const struct rtl83xx_mib_desc rtl83xx_mib[] = {
96 MIB_DESC(2, 0xf8, "ifInOctets"),
97 MIB_DESC(2, 0xf0, "ifOutOctets"),
98 MIB_DESC(1, 0xec, "dot1dTpPortInDiscards"),
99 MIB_DESC(1, 0xe8, "ifInUcastPkts"),
100 MIB_DESC(1, 0xe4, "ifInMulticastPkts"),
101 MIB_DESC(1, 0xe0, "ifInBroadcastPkts"),
102 MIB_DESC(1, 0xdc, "ifOutUcastPkts"),
103 MIB_DESC(1, 0xd8, "ifOutMulticastPkts"),
104 MIB_DESC(1, 0xd4, "ifOutBroadcastPkts"),
105 MIB_DESC(1, 0xd0, "ifOutDiscards"),
106 MIB_DESC(1, 0xcc, ".3SingleCollisionFrames"),
107 MIB_DESC(1, 0xc8, ".3MultipleCollisionFrames"),
108 MIB_DESC(1, 0xc4, ".3DeferredTransmissions"),
109 MIB_DESC(1, 0xc0, ".3LateCollisions"),
110 MIB_DESC(1, 0xbc, ".3ExcessiveCollisions"),
111 MIB_DESC(1, 0xb8, ".3SymbolErrors"),
112 MIB_DESC(1, 0xb4, ".3ControlInUnknownOpcodes"),
113 MIB_DESC(1, 0xb0, ".3InPauseFrames"),
114 MIB_DESC(1, 0xac, ".3OutPauseFrames"),
115 MIB_DESC(1, 0xa8, "DropEvents"),
116 MIB_DESC(1, 0xa4, "tx_BroadcastPkts"),
117 MIB_DESC(1, 0xa0, "tx_MulticastPkts"),
118 MIB_DESC(1, 0x9c, "CRCAlignErrors"),
119 MIB_DESC(1, 0x98, "tx_UndersizePkts"),
120 MIB_DESC(1, 0x94, "rx_UndersizePkts"),
121 MIB_DESC(1, 0x90, "rx_UndersizedropPkts"),
122 MIB_DESC(1, 0x8c, "tx_OversizePkts"),
123 MIB_DESC(1, 0x88, "rx_OversizePkts"),
124 MIB_DESC(1, 0x84, "Fragments"),
125 MIB_DESC(1, 0x80, "Jabbers"),
126 MIB_DESC(1, 0x7c, "Collisions"),
127 MIB_DESC(1, 0x78, "tx_Pkts64Octets"),
128 MIB_DESC(1, 0x74, "rx_Pkts64Octets"),
129 MIB_DESC(1, 0x70, "tx_Pkts65to127Octets"),
130 MIB_DESC(1, 0x6c, "rx_Pkts65to127Octets"),
131 MIB_DESC(1, 0x68, "tx_Pkts128to255Octets"),
132 MIB_DESC(1, 0x64, "rx_Pkts128to255Octets"),
133 MIB_DESC(1, 0x60, "tx_Pkts256to511Octets"),
134 MIB_DESC(1, 0x5c, "rx_Pkts256to511Octets"),
135 MIB_DESC(1, 0x58, "tx_Pkts512to1023Octets"),
136 MIB_DESC(1, 0x54, "rx_Pkts512to1023Octets"),
137 MIB_DESC(1, 0x50, "tx_Pkts1024to1518Octets"),
138 MIB_DESC(1, 0x4c, "rx_StatsPkts1024to1518Octets"),
139 MIB_DESC(1, 0x48, "tx_Pkts1519toMaxOctets"),
140 MIB_DESC(1, 0x44, "rx_Pkts1519toMaxOctets"),
141 MIB_DESC(1, 0x40, "rxMacDiscards")
142 };
143
144
145 /* DSA callbacks */
146
147
148 static enum dsa_tag_protocol rtl83xx_get_tag_protocol(struct dsa_switch *ds, int port)
149 {
150 /* The switch does not tag the frames, instead internally the header
151 * structure for each packet is tagged accordingly.
152 */
153 return DSA_TAG_PROTO_TRAILER;
154 }
155
156 static int rtl83xx_setup(struct dsa_switch *ds)
157 {
158 int i;
159 struct rtl838x_switch_priv *priv = ds->priv;
160 u64 port_bitmap = BIT_ULL(priv->cpu_port);
161
162 pr_debug("%s called\n", __func__);
163
164 /* Disable MAC polling the PHY so that we can start configuration */
165 priv->r->set_port_reg_le(0ULL, priv->r->smi_poll_ctrl);
166
167 for (i = 0; i < ds->num_ports; i++)
168 priv->ports[i].enable = false;
169 priv->ports[priv->cpu_port].enable = true;
170
171 /* Isolate ports from each other: traffic only CPU <-> port */
172 /* Setting bit j in register RTL838X_PORT_ISO_CTRL(i) allows
173 * traffic from source port i to destination port j
174 */
175 for (i = 0; i < priv->cpu_port; i++) {
176 if (priv->ports[i].phy) {
177 priv->r->set_port_reg_be(BIT_ULL(priv->cpu_port) | BIT(i),
178 priv->r->port_iso_ctrl(i));
179 port_bitmap |= BIT_ULL(i);
180 }
181 }
182 priv->r->set_port_reg_be(port_bitmap, priv->r->port_iso_ctrl(priv->cpu_port));
183
184 if (priv->family_id == RTL8380_FAMILY_ID)
185 rtl838x_print_matrix();
186 else
187 rtl839x_print_matrix();
188
189 rtl83xx_init_stats(priv);
190
191 ds->configure_vlan_while_not_filtering = true;
192
193 /* Enable MAC Polling PHY again */
194 rtl83xx_enable_phy_polling(priv);
195 pr_debug("Please wait until PHY is settled\n");
196 msleep(1000);
197 return 0;
198 }
199
200 static int rtl930x_setup(struct dsa_switch *ds)
201 {
202 int i;
203 struct rtl838x_switch_priv *priv = ds->priv;
204 u32 port_bitmap = BIT(priv->cpu_port);
205
206 pr_info("%s called\n", __func__);
207
208 // Enable CSTI STP mode
209 // sw_w32(1, RTL930X_ST_CTRL);
210
211 /* Disable MAC polling the PHY so that we can start configuration */
212 sw_w32(0, RTL930X_SMI_POLL_CTRL);
213
214 // Disable all ports except CPU port
215 for (i = 0; i < ds->num_ports; i++)
216 priv->ports[i].enable = false;
217 priv->ports[priv->cpu_port].enable = true;
218
219 for (i = 0; i < priv->cpu_port; i++) {
220 if (priv->ports[i].phy) {
221 priv->r->traffic_set(i, BIT(priv->cpu_port) | BIT(i));
222 port_bitmap |= 1ULL << i;
223 }
224 }
225 priv->r->traffic_set(priv->cpu_port, port_bitmap);
226
227 rtl930x_print_matrix();
228
229 // TODO: Initialize statistics
230
231 ds->configure_vlan_while_not_filtering = true;
232
233 rtl83xx_enable_phy_polling(priv);
234
235 return 0;
236 }
237
238 static void rtl83xx_phylink_validate(struct dsa_switch *ds, int port,
239 unsigned long *supported,
240 struct phylink_link_state *state)
241 {
242 struct rtl838x_switch_priv *priv = ds->priv;
243 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
244
245 pr_debug("In %s port %d", __func__, port);
246
247 if (!phy_interface_mode_is_rgmii(state->interface) &&
248 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
249 state->interface != PHY_INTERFACE_MODE_MII &&
250 state->interface != PHY_INTERFACE_MODE_REVMII &&
251 state->interface != PHY_INTERFACE_MODE_GMII &&
252 state->interface != PHY_INTERFACE_MODE_QSGMII &&
253 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
254 state->interface != PHY_INTERFACE_MODE_SGMII) {
255 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
256 dev_err(ds->dev,
257 "Unsupported interface: %d for port %d\n",
258 state->interface, port);
259 return;
260 }
261
262 /* Allow all the expected bits */
263 phylink_set(mask, Autoneg);
264 phylink_set_port_modes(mask);
265 phylink_set(mask, Pause);
266 phylink_set(mask, Asym_Pause);
267
268 /* With the exclusion of MII and Reverse MII, we support Gigabit,
269 * including Half duplex
270 */
271 if (state->interface != PHY_INTERFACE_MODE_MII &&
272 state->interface != PHY_INTERFACE_MODE_REVMII) {
273 phylink_set(mask, 1000baseT_Full);
274 phylink_set(mask, 1000baseT_Half);
275 }
276
277 /* On both the 8380 and 8382, ports 24-27 are SFP ports */
278 if (port >= 24 && port <= 27 && priv->family_id == RTL8380_FAMILY_ID)
279 phylink_set(mask, 1000baseX_Full);
280
281 phylink_set(mask, 10baseT_Half);
282 phylink_set(mask, 10baseT_Full);
283 phylink_set(mask, 100baseT_Half);
284 phylink_set(mask, 100baseT_Full);
285
286 bitmap_and(supported, supported, mask,
287 __ETHTOOL_LINK_MODE_MASK_NBITS);
288 bitmap_and(state->advertising, state->advertising, mask,
289 __ETHTOOL_LINK_MODE_MASK_NBITS);
290 }
291
292 static int rtl83xx_phylink_mac_link_state(struct dsa_switch *ds, int port,
293 struct phylink_link_state *state)
294 {
295 struct rtl838x_switch_priv *priv = ds->priv;
296 u64 speed;
297 u64 link;
298
299 if (port < 0 || port > priv->cpu_port)
300 return -EINVAL;
301
302 /*
303 * On the RTL9300 for at least the RTL8226B PHY, the MAC-side link
304 * state needs to be read twice in order to read a correct result.
305 * This would not be necessary for ports connected e.g. to RTL8218D
306 * PHYs.
307 */
308 state->link = 0;
309 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
310 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
311 if (link & BIT_ULL(port))
312 state->link = 1;
313 pr_info("%s: link state: %llx\n", __func__, link & BIT_ULL(port));
314
315 state->duplex = 0;
316 if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port))
317 state->duplex = 1;
318
319 speed = priv->r->get_port_reg_le(priv->r->mac_link_spd_sts(port));
320 speed >>= (port % 16) << 1;
321 switch (speed & 0x3) {
322 case 0:
323 state->speed = SPEED_10;
324 break;
325 case 1:
326 state->speed = SPEED_100;
327 break;
328 case 2:
329 state->speed = SPEED_1000;
330 break;
331 case 3:
332 if (port == 24 || port == 26) /* Internal serdes */
333 state->speed = SPEED_2500;
334 else
335 state->speed = SPEED_100; /* Is in fact 500Mbit */
336 }
337
338 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
339 if (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & BIT_ULL(port))
340 state->pause |= MLO_PAUSE_RX;
341 if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port))
342 state->pause |= MLO_PAUSE_TX;
343 return 1;
344 }
345
346 static void rtl83xx_phylink_mac_config(struct dsa_switch *ds, int port,
347 unsigned int mode,
348 const struct phylink_link_state *state)
349 {
350 struct rtl838x_switch_priv *priv = ds->priv;
351 u32 reg;
352 int speed_bit = priv->family_id == RTL8380_FAMILY_ID ? 4 : 3;
353
354 pr_debug("%s port %d, mode %x\n", __func__, port, mode);
355
356 // BUG: Make this work on RTL93XX
357 if (priv->family_id >= RTL9300_FAMILY_ID)
358 return;
359
360 if (port == priv->cpu_port) {
361 /* Set Speed, duplex, flow control
362 * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL
363 * | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN
364 * | MEDIA_SEL
365 */
366 if (priv->family_id == RTL8380_FAMILY_ID) {
367 sw_w32(0x6192F, priv->r->mac_force_mode_ctrl(priv->cpu_port));
368 /* allow CRC errors on CPU-port */
369 sw_w32_mask(0, 0x8, RTL838X_MAC_PORT_CTRL(priv->cpu_port));
370 } else {
371 sw_w32_mask(0, 3, priv->r->mac_force_mode_ctrl(priv->cpu_port));
372 }
373 return;
374 }
375
376 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
377 /* Auto-Negotiation does not work for MAC in RTL8390 */
378 if (priv->family_id == RTL8380_FAMILY_ID) {
379 if (mode == MLO_AN_PHY) {
380 pr_debug("PHY autonegotiates\n");
381 reg |= BIT(2);
382 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
383 return;
384 }
385 }
386
387 if (mode != MLO_AN_FIXED)
388 pr_debug("Fixed state.\n");
389
390 if (priv->family_id == RTL8380_FAMILY_ID) {
391 /* Clear id_mode_dis bit, and the existing port mode, let
392 * RGMII_MODE_EN bet set by mac_link_{up,down}
393 */
394 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
395
396 if (state->pause & MLO_PAUSE_TXRX_MASK) {
397 if (state->pause & MLO_PAUSE_TX)
398 reg |= TX_PAUSE_EN;
399 reg |= RX_PAUSE_EN;
400 }
401 }
402
403 reg &= ~(3 << speed_bit);
404 switch (state->speed) {
405 case SPEED_1000:
406 reg |= 2 << speed_bit;
407 break;
408 case SPEED_100:
409 reg |= 1 << speed_bit;
410 break;
411 }
412
413 if (priv->family_id == RTL8380_FAMILY_ID) {
414 reg &= ~(DUPLEX_FULL | FORCE_LINK_EN);
415 if (state->link)
416 reg |= FORCE_LINK_EN;
417 if (state->duplex == DUPLEX_FULL)
418 reg |= DUPLX_MODE;
419 }
420
421 // Disable AN
422 if (priv->family_id == RTL8380_FAMILY_ID)
423 reg &= ~BIT(2);
424 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
425 }
426
427 static void rtl83xx_phylink_mac_link_down(struct dsa_switch *ds, int port,
428 unsigned int mode,
429 phy_interface_t interface)
430 {
431 struct rtl838x_switch_priv *priv = ds->priv;
432 /* Stop TX/RX to port */
433 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port));
434 }
435
436 static void rtl83xx_phylink_mac_link_up(struct dsa_switch *ds, int port,
437 unsigned int mode,
438 phy_interface_t interface,
439 struct phy_device *phydev)
440 {
441 struct rtl838x_switch_priv *priv = ds->priv;
442 /* Restart TX/RX to port */
443 sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port));
444 }
445
446 static void rtl83xx_get_strings(struct dsa_switch *ds,
447 int port, u32 stringset, u8 *data)
448 {
449 int i;
450
451 if (stringset != ETH_SS_STATS)
452 return;
453
454 for (i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++)
455 strncpy(data + i * ETH_GSTRING_LEN, rtl83xx_mib[i].name,
456 ETH_GSTRING_LEN);
457 }
458
459 static void rtl83xx_get_ethtool_stats(struct dsa_switch *ds, int port,
460 uint64_t *data)
461 {
462 struct rtl838x_switch_priv *priv = ds->priv;
463 const struct rtl83xx_mib_desc *mib;
464 int i;
465 u64 h;
466
467 for (i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++) {
468 mib = &rtl83xx_mib[i];
469
470 data[i] = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 252 - mib->offset);
471 if (mib->size == 2) {
472 h = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 248 - mib->offset);
473 data[i] |= h << 32;
474 }
475 }
476 }
477
478 static int rtl83xx_get_sset_count(struct dsa_switch *ds, int port, int sset)
479 {
480 if (sset != ETH_SS_STATS)
481 return 0;
482
483 return ARRAY_SIZE(rtl83xx_mib);
484 }
485
486 static int rtl83xx_port_enable(struct dsa_switch *ds, int port,
487 struct phy_device *phydev)
488 {
489 struct rtl838x_switch_priv *priv = ds->priv;
490 u64 v;
491
492 pr_debug("%s: %x %d", __func__, (u32) priv, port);
493 priv->ports[port].enable = true;
494
495 /* enable inner tagging on egress, do not keep any tags */
496 if (priv->family_id == RTL9310_FAMILY_ID)
497 sw_w32(BIT(4), priv->r->vlan_port_tag_sts_ctrl + (port << 2));
498 else
499 sw_w32(1, priv->r->vlan_port_tag_sts_ctrl + (port << 2));
500
501 if (dsa_is_cpu_port(ds, port))
502 return 0;
503
504 /* add port to switch mask of CPU_PORT */
505 priv->r->traffic_enable(priv->cpu_port, port);
506
507 /* add all other ports in the same bridge to switch mask of port */
508 v = priv->r->traffic_get(port);
509 v |= priv->ports[port].pm;
510 priv->r->traffic_set(port, v);
511
512 sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_SABLK_CTRL);
513 sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_DABLK_CTRL);
514
515 return 0;
516 }
517
518 static void rtl83xx_port_disable(struct dsa_switch *ds, int port)
519 {
520 struct rtl838x_switch_priv *priv = ds->priv;
521 u64 v;
522
523 pr_debug("%s %x: %d", __func__, (u32)priv, port);
524 /* you can only disable user ports */
525 if (!dsa_is_user_port(ds, port))
526 return;
527
528 // BUG: This does not work on RTL931X
529 /* remove port from switch mask of CPU_PORT */
530 priv->r->traffic_disable(priv->cpu_port, port);
531
532 /* remove all other ports in the same bridge from switch mask of port */
533 v = priv->r->traffic_get(port);
534 v &= ~priv->ports[port].pm;
535 priv->r->traffic_set(port, v);
536
537 priv->ports[port].enable = false;
538 }
539
540 static int rtl83xx_get_mac_eee(struct dsa_switch *ds, int port,
541 struct ethtool_eee *e)
542 {
543 struct rtl838x_switch_priv *priv = ds->priv;
544
545 pr_debug("%s: port %d", __func__, port);
546 e->supported = SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full;
547 if (sw_r32(priv->r->mac_force_mode_ctrl(port)) & BIT(9))
548 e->advertised |= ADVERTISED_100baseT_Full;
549
550 if (sw_r32(priv->r->mac_force_mode_ctrl(port)) & BIT(10))
551 e->advertised |= ADVERTISED_1000baseT_Full;
552
553 e->eee_enabled = priv->ports[port].eee_enabled;
554 pr_debug("enabled: %d, active %x\n", e->eee_enabled, e->advertised);
555
556 if (sw_r32(RTL838X_MAC_EEE_ABLTY) & BIT(port)) {
557 e->lp_advertised = ADVERTISED_100baseT_Full;
558 e->lp_advertised |= ADVERTISED_1000baseT_Full;
559 }
560
561 e->eee_active = !!(e->advertised & e->lp_advertised);
562 pr_debug("active: %d, lp %x\n", e->eee_active, e->lp_advertised);
563
564 return 0;
565 }
566
567 static int rtl83xx_set_mac_eee(struct dsa_switch *ds, int port,
568 struct ethtool_eee *e)
569 {
570 struct rtl838x_switch_priv *priv = ds->priv;
571
572 pr_debug("%s: port %d", __func__, port);
573 if (e->eee_enabled) {
574 pr_debug("Globally enabling EEE\n");
575 sw_w32_mask(0x4, 0, RTL838X_SMI_GLB_CTRL);
576 }
577 if (e->eee_enabled) {
578 pr_debug("Enabling EEE for MAC %d\n", port);
579 sw_w32_mask(0, 3 << 9, priv->r->mac_force_mode_ctrl(port));
580 sw_w32_mask(0, BIT(port), RTL838X_EEE_PORT_TX_EN);
581 sw_w32_mask(0, BIT(port), RTL838X_EEE_PORT_RX_EN);
582 priv->ports[port].eee_enabled = true;
583 e->eee_enabled = true;
584 } else {
585 pr_debug("Disabling EEE for MAC %d\n", port);
586 sw_w32_mask(3 << 9, 0, priv->r->mac_force_mode_ctrl(port));
587 sw_w32_mask(BIT(port), 0, RTL838X_EEE_PORT_TX_EN);
588 sw_w32_mask(BIT(port), 0, RTL838X_EEE_PORT_RX_EN);
589 priv->ports[port].eee_enabled = false;
590 e->eee_enabled = false;
591 }
592 return 0;
593 }
594
595 /*
596 * Set Switch L2 Aging time, t is time in milliseconds
597 * t = 0: aging is disabled
598 */
599 static int rtl83xx_set_l2aging(struct dsa_switch *ds, u32 t)
600 {
601 struct rtl838x_switch_priv *priv = ds->priv;
602 int t_max = priv->family_id == RTL8380_FAMILY_ID ? 0x7fffff : 0x1FFFFF;
603
604 /* Convert time in mseconds to internal value */
605 if (t > 0x10000000) { /* Set to maximum */
606 t = t_max;
607 } else {
608 if (priv->family_id == RTL8380_FAMILY_ID)
609 t = ((t * 625) / 1000 + 127) / 128;
610 else
611 t = (t * 5 + 2) / 3;
612 }
613 sw_w32(t, priv->r->l2_ctrl_1);
614 return 0;
615 }
616
617 static int rtl83xx_port_bridge_join(struct dsa_switch *ds, int port,
618 struct net_device *bridge)
619 {
620 struct rtl838x_switch_priv *priv = ds->priv;
621 u64 port_bitmap = 1ULL << priv->cpu_port, v;
622 int i;
623
624 pr_debug("%s %x: %d %llx", __func__, (u32)priv, port, port_bitmap);
625 mutex_lock(&priv->reg_mutex);
626 for (i = 0; i < ds->num_ports; i++) {
627 /* Add this port to the port matrix of the other ports in the
628 * same bridge. If the port is disabled, port matrix is kept
629 * and not being setup until the port becomes enabled.
630 */
631 if (dsa_is_user_port(ds, i) && i != port) {
632 if (dsa_to_port(ds, i)->bridge_dev != bridge)
633 continue;
634 if (priv->ports[i].enable)
635 priv->r->traffic_enable(i, port);
636
637 priv->ports[i].pm |= 1ULL << port;
638 port_bitmap |= 1ULL << i;
639 }
640 }
641
642 /* Add all other ports to this port matrix. */
643 if (priv->ports[port].enable) {
644 priv->r->traffic_enable(priv->cpu_port, port);
645 v = priv->r->traffic_get(port);
646 v |= port_bitmap;
647 priv->r->traffic_set(port, v);
648 }
649 priv->ports[port].pm |= port_bitmap;
650 mutex_unlock(&priv->reg_mutex);
651
652 return 0;
653 }
654
655 static void rtl83xx_port_bridge_leave(struct dsa_switch *ds, int port,
656 struct net_device *bridge)
657 {
658 struct rtl838x_switch_priv *priv = ds->priv;
659 u64 port_bitmap = 1ULL << priv->cpu_port, v;
660 int i;
661
662 pr_debug("%s %x: %d", __func__, (u32)priv, port);
663 mutex_lock(&priv->reg_mutex);
664 for (i = 0; i < ds->num_ports; i++) {
665 /* Remove this port from the port matrix of the other ports
666 * in the same bridge. If the port is disabled, port matrix
667 * is kept and not being setup until the port becomes enabled.
668 * And the other port's port matrix cannot be broken when the
669 * other port is still a VLAN-aware port.
670 */
671 if (dsa_is_user_port(ds, i) && i != port) {
672 if (dsa_to_port(ds, i)->bridge_dev != bridge)
673 continue;
674 if (priv->ports[i].enable)
675 priv->r->traffic_disable(i, port);
676
677 priv->ports[i].pm |= 1ULL << port;
678 port_bitmap &= ~BIT_ULL(i);
679 }
680 }
681
682 /* Add all other ports to this port matrix. */
683 if (priv->ports[port].enable) {
684 v = priv->r->traffic_get(port);
685 v |= port_bitmap;
686 priv->r->traffic_set(port, v);
687 }
688 priv->ports[port].pm &= ~port_bitmap;
689
690 mutex_unlock(&priv->reg_mutex);
691 }
692
693 void rtl83xx_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
694 {
695 u32 msti = 0;
696 u32 port_state[4];
697 int index, bit;
698 int pos = port;
699 struct rtl838x_switch_priv *priv = ds->priv;
700 int n = priv->port_width << 1;
701
702 /* Ports above or equal CPU port can never be configured */
703 if (port >= priv->cpu_port)
704 return;
705
706 mutex_lock(&priv->reg_mutex);
707
708 /* For the RTL839x and following, the bits are left-aligned, 838x and 930x
709 * have 64 bit fields, 839x and 931x have 128 bit fields
710 */
711 if (priv->family_id == RTL8390_FAMILY_ID)
712 pos += 12;
713 if (priv->family_id == RTL9300_FAMILY_ID)
714 pos += 3;
715 if (priv->family_id == RTL9310_FAMILY_ID)
716 pos += 8;
717
718 index = n - (pos >> 4) - 1;
719 bit = (pos << 1) % 32;
720
721 priv->r->stp_get(priv, msti, port_state);
722
723 pr_debug("Current state, port %d: %d\n", port, (port_state[index] >> bit) & 3);
724 port_state[index] &= ~(3 << bit);
725
726 switch (state) {
727 case BR_STATE_DISABLED: /* 0 */
728 port_state[index] |= (0 << bit);
729 break;
730 case BR_STATE_BLOCKING: /* 4 */
731 case BR_STATE_LISTENING: /* 1 */
732 port_state[index] |= (1 << bit);
733 break;
734 case BR_STATE_LEARNING: /* 2 */
735 port_state[index] |= (2 << bit);
736 break;
737 case BR_STATE_FORWARDING: /* 3*/
738 port_state[index] |= (3 << bit);
739 default:
740 break;
741 }
742
743 priv->r->stp_set(priv, msti, port_state);
744
745 mutex_unlock(&priv->reg_mutex);
746 }
747
748 void rtl83xx_fast_age(struct dsa_switch *ds, int port)
749 {
750 struct rtl838x_switch_priv *priv = ds->priv;
751 int s = priv->family_id == RTL8390_FAMILY_ID ? 2 : 0;
752
753 pr_debug("FAST AGE port %d\n", port);
754 mutex_lock(&priv->reg_mutex);
755 /* RTL838X_L2_TBL_FLUSH_CTRL register bits, 839x has 1 bit larger
756 * port fields:
757 * 0-4: Replacing port
758 * 5-9: Flushed/replaced port
759 * 10-21: FVID
760 * 22: Entry types: 1: dynamic, 0: also static
761 * 23: Match flush port
762 * 24: Match FVID
763 * 25: Flush (0) or replace (1) L2 entries
764 * 26: Status of action (1: Start, 0: Done)
765 */
766 sw_w32(1 << (26 + s) | 1 << (23 + s) | port << (5 + (s / 2)), priv->r->l2_tbl_flush_ctrl);
767
768 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(26 + s));
769
770 mutex_unlock(&priv->reg_mutex);
771 }
772
773 void rtl930x_fast_age(struct dsa_switch *ds, int port)
774 {
775 struct rtl838x_switch_priv *priv = ds->priv;
776
777 pr_debug("FAST AGE port %d\n", port);
778 mutex_lock(&priv->reg_mutex);
779 sw_w32(port << 11, RTL930X_L2_TBL_FLUSH_CTRL + 4);
780
781 sw_w32(BIT(26) | BIT(30), RTL930X_L2_TBL_FLUSH_CTRL);
782
783 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(30));
784
785 mutex_unlock(&priv->reg_mutex);
786 }
787
788 static int rtl83xx_vlan_filtering(struct dsa_switch *ds, int port,
789 bool vlan_filtering)
790 {
791 struct rtl838x_switch_priv *priv = ds->priv;
792
793 pr_debug("%s: port %d\n", __func__, port);
794 mutex_lock(&priv->reg_mutex);
795
796 if (vlan_filtering) {
797 /* Enable ingress and egress filtering
798 * The VLAN_PORT_IGR_FILTER register uses 2 bits for each port to define
799 * the filter action:
800 * 0: Always Forward
801 * 1: Drop packet
802 * 2: Trap packet to CPU port
803 * The Egress filter used 1 bit per state (0: DISABLED, 1: ENABLED)
804 */
805 if (port != priv->cpu_port)
806 sw_w32_mask(0b10 << ((port % 16) << 1), 0b01 << ((port % 16) << 1),
807 priv->r->vlan_port_igr_filter + ((port >> 5) << 2));
808 sw_w32_mask(0, BIT(port % 32), priv->r->vlan_port_egr_filter + ((port >> 4) << 2));
809 } else {
810 /* Disable ingress and egress filtering */
811 if (port != priv->cpu_port)
812 sw_w32_mask(0b11 << ((port % 16) << 1), 0,
813 priv->r->vlan_port_igr_filter + ((port >> 5) << 2));
814 sw_w32_mask(BIT(port % 32), 0, priv->r->vlan_port_egr_filter + ((port >> 4) << 2));
815 }
816
817 /* Do we need to do something to the CPU-Port, too? */
818 mutex_unlock(&priv->reg_mutex);
819
820 return 0;
821 }
822
823 static int rtl83xx_vlan_prepare(struct dsa_switch *ds, int port,
824 const struct switchdev_obj_port_vlan *vlan)
825 {
826 struct rtl838x_vlan_info info;
827 struct rtl838x_switch_priv *priv = ds->priv;
828
829 pr_info("%s: port %d\n", __func__, port);
830
831 mutex_lock(&priv->reg_mutex);
832
833 priv->r->vlan_profile_dump(1);
834 priv->r->vlan_tables_read(1, &info);
835
836 pr_info("Tagged ports %llx, untag %llx, prof %x, MC# %d, UC# %d, FID %x\n",
837 info.tagged_ports, info.untagged_ports, info.profile_id,
838 info.hash_mc_fid, info.hash_uc_fid, info.fid);
839
840 priv->r->vlan_set_untagged(1, info.untagged_ports);
841 pr_debug("SET: Untagged ports, VLAN %d: %llx\n", 1, info.untagged_ports);
842
843 priv->r->vlan_set_tagged(1, &info);
844 pr_debug("SET: Tagged ports, VLAN %d: %llx\n", 1, info.tagged_ports);
845
846 mutex_unlock(&priv->reg_mutex);
847 return 0;
848 }
849
850 static void rtl83xx_vlan_add(struct dsa_switch *ds, int port,
851 const struct switchdev_obj_port_vlan *vlan)
852 {
853 struct rtl838x_vlan_info info;
854 struct rtl838x_switch_priv *priv = ds->priv;
855 int v;
856
857 pr_info("%s port %d, vid_end %d, vid_end %d, flags %x\n", __func__,
858 port, vlan->vid_begin, vlan->vid_end, vlan->flags);
859
860 if (vlan->vid_begin > 4095 || vlan->vid_end > 4095) {
861 dev_err(priv->dev, "VLAN out of range: %d - %d",
862 vlan->vid_begin, vlan->vid_end);
863 return;
864 }
865
866 mutex_lock(&priv->reg_mutex);
867
868 if (vlan->flags & BRIDGE_VLAN_INFO_PVID) {
869 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
870 if (!v)
871 continue;
872 /* Set both inner and outer PVID of the port */
873 sw_w32((v << 16) | v << 2, priv->r->vlan_port_pb + (port << 2));
874 priv->ports[port].pvid = vlan->vid_end;
875 }
876 }
877
878 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
879 if (!v)
880 continue;
881
882 /* Get port memberships of this vlan */
883 priv->r->vlan_tables_read(v, &info);
884
885 /* new VLAN? */
886 if (!info.tagged_ports) {
887 info.fid = 0;
888 info.hash_mc_fid = false;
889 info.hash_uc_fid = false;
890 info.profile_id = 0;
891 }
892
893 /* sanitize untagged_ports - must be a subset */
894 if (info.untagged_ports & ~info.tagged_ports)
895 info.untagged_ports = 0;
896
897 info.tagged_ports |= BIT_ULL(port);
898 if (vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED)
899 info.untagged_ports |= BIT_ULL(port);
900
901 priv->r->vlan_set_untagged(v, info.untagged_ports);
902 pr_info("Untagged ports, VLAN %d: %llx\n", v, info.untagged_ports);
903
904 priv->r->vlan_set_tagged(v, &info);
905 pr_info("Tagged ports, VLAN %d: %llx\n", v, info.tagged_ports);
906 }
907
908 mutex_unlock(&priv->reg_mutex);
909 }
910
911 static int rtl83xx_vlan_del(struct dsa_switch *ds, int port,
912 const struct switchdev_obj_port_vlan *vlan)
913 {
914 struct rtl838x_vlan_info info;
915 struct rtl838x_switch_priv *priv = ds->priv;
916 int v;
917 u16 pvid;
918
919 pr_debug("%s: port %d, vid_end %d, vid_end %d, flags %x\n", __func__,
920 port, vlan->vid_begin, vlan->vid_end, vlan->flags);
921
922 if (vlan->vid_begin > 4095 || vlan->vid_end > 4095) {
923 dev_err(priv->dev, "VLAN out of range: %d - %d",
924 vlan->vid_begin, vlan->vid_end);
925 return -ENOTSUPP;
926 }
927
928 mutex_lock(&priv->reg_mutex);
929 pvid = priv->ports[port].pvid;
930
931 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
932 /* Reset to default if removing the current PVID */
933 if (v == pvid)
934 sw_w32(0, priv->r->vlan_port_pb + (port << 2));
935
936 /* Get port memberships of this vlan */
937 priv->r->vlan_tables_read(v, &info);
938
939 /* remove port from both tables */
940 info.untagged_ports &= (~BIT_ULL(port));
941 /* always leave vid 1 */
942 if (v != 1)
943 info.tagged_ports &= (~BIT_ULL(port));
944
945 priv->r->vlan_set_untagged(v, info.untagged_ports);
946 pr_debug("Untagged ports, VLAN %d: %llx\n", v, info.untagged_ports);
947
948 priv->r->vlan_set_tagged(v, &info);
949 pr_debug("Tagged ports, VLAN %d: %llx\n", v, info.tagged_ports);
950 }
951 mutex_unlock(&priv->reg_mutex);
952
953 return 0;
954 }
955
956 static int rtl83xx_port_fdb_add(struct dsa_switch *ds, int port,
957 const unsigned char *addr, u16 vid)
958 {
959 struct rtl838x_switch_priv *priv = ds->priv;
960 u64 mac = ether_addr_to_u64(addr);
961 u32 key = rtl83xx_hash_key(priv, mac, vid);
962 struct rtl838x_l2_entry e;
963 u32 r[3];
964 u64 entry;
965 int idx = -1, err = 0, i;
966
967 mutex_lock(&priv->reg_mutex);
968 for (i = 0; i < 4; i++) {
969 entry = priv->r->read_l2_entry_using_hash(key, i, &e);
970 if (!e.valid) {
971 idx = (key << 2) | i;
972 break;
973 }
974 if ((entry & 0x0fffffffffffffffULL) == ((mac << 12) | vid)) {
975 idx = (key << 2) | i;
976 break;
977 }
978 }
979 if (idx >= 0) {
980 r[0] = 3 << 17 | port << 12; // Aging and port
981 r[0] |= vid;
982 r[1] = mac >> 16;
983 r[2] = (mac & 0xffff) << 12; /* rvid = 0 */
984 rtl83xx_write_hash(idx, r);
985 goto out;
986 }
987
988 /* Hash buckets full, try CAM */
989 for (i = 0; i < 64; i++) {
990 entry = priv->r->read_cam(i, &e);
991 if (!e.valid) {
992 if (idx < 0) /* First empty entry? */
993 idx = i;
994 break;
995 } else if ((entry & 0x0fffffffffffffffULL) == ((mac << 12) | vid)) {
996 pr_debug("Found entry in CAM\n");
997 idx = i;
998 break;
999 }
1000 }
1001 if (idx >= 0) {
1002 r[0] = 3 << 17 | port << 12; // Aging
1003 r[0] |= vid;
1004 r[1] = mac >> 16;
1005 r[2] = (mac & 0xffff) << 12; /* rvid = 0 */
1006 rtl83xx_write_cam(idx, r);
1007 goto out;
1008 }
1009 err = -ENOTSUPP;
1010 out:
1011 mutex_unlock(&priv->reg_mutex);
1012 return err;
1013 }
1014
1015 static int rtl83xx_port_fdb_del(struct dsa_switch *ds, int port,
1016 const unsigned char *addr, u16 vid)
1017 {
1018 struct rtl838x_switch_priv *priv = ds->priv;
1019 u64 mac = ether_addr_to_u64(addr);
1020 u32 key = rtl83xx_hash_key(priv, mac, vid);
1021 struct rtl838x_l2_entry e;
1022 u32 r[3];
1023 u64 entry;
1024 int idx = -1, err = 0, i;
1025
1026 pr_debug("In %s, mac %llx, vid: %d, key: %x08x\n", __func__, mac, vid, key);
1027 mutex_lock(&priv->reg_mutex);
1028 for (i = 0; i < 4; i++) {
1029 entry = priv->r->read_l2_entry_using_hash(key, i, &e);
1030 if (!e.valid)
1031 continue;
1032 if ((entry & 0x0fffffffffffffffULL) == ((mac << 12) | vid)) {
1033 idx = (key << 2) | i;
1034 break;
1035 }
1036 }
1037
1038 if (idx >= 0) {
1039 r[0] = r[1] = r[2] = 0;
1040 rtl83xx_write_hash(idx, r);
1041 goto out;
1042 }
1043
1044 /* Check CAM for spillover from hash buckets */
1045 for (i = 0; i < 64; i++) {
1046 entry = priv->r->read_cam(i, &e);
1047 if ((entry & 0x0fffffffffffffffULL) == ((mac << 12) | vid)) {
1048 idx = i;
1049 break;
1050 }
1051 }
1052 if (idx >= 0) {
1053 r[0] = r[1] = r[2] = 0;
1054 rtl83xx_write_cam(idx, r);
1055 goto out;
1056 }
1057 err = -ENOENT;
1058 out:
1059 mutex_unlock(&priv->reg_mutex);
1060 return err;
1061 }
1062
1063 static int rtl83xx_port_fdb_dump(struct dsa_switch *ds, int port,
1064 dsa_fdb_dump_cb_t *cb, void *data)
1065 {
1066 struct rtl838x_l2_entry e;
1067 struct rtl838x_switch_priv *priv = ds->priv;
1068 int i;
1069 u32 fid;
1070 u32 pkey;
1071 u64 mac;
1072
1073 mutex_lock(&priv->reg_mutex);
1074
1075 for (i = 0; i < priv->fib_entries; i++) {
1076 priv->r->read_l2_entry_using_hash(i >> 2, i & 0x3, &e);
1077
1078 if (!e.valid)
1079 continue;
1080
1081 if (e.port == port) {
1082 fid = (i & 0x3ff) | (e.rvid & ~0x3ff);
1083 mac = ether_addr_to_u64(&e.mac[0]);
1084 pkey = rtl838x_hash(priv, mac << 12 | fid);
1085 fid = (pkey & 0x3ff) | (fid & ~0x3ff);
1086 pr_debug("-> mac %016llx, fid: %d\n", mac, fid);
1087 cb(e.mac, e.vid, e.is_static, data);
1088 }
1089 }
1090
1091 for (i = 0; i < 64; i++) {
1092 priv->r->read_cam(i, &e);
1093
1094 if (!e.valid)
1095 continue;
1096
1097 if (e.port == port)
1098 cb(e.mac, e.vid, e.is_static, data);
1099 }
1100
1101 mutex_unlock(&priv->reg_mutex);
1102 return 0;
1103 }
1104
1105 static int rtl83xx_port_mirror_add(struct dsa_switch *ds, int port,
1106 struct dsa_mall_mirror_tc_entry *mirror,
1107 bool ingress)
1108 {
1109 /* We support 4 mirror groups, one destination port per group */
1110 int group;
1111 struct rtl838x_switch_priv *priv = ds->priv;
1112 int ctrl_reg, dpm_reg, spm_reg;
1113
1114 pr_debug("In %s\n", __func__);
1115
1116 for (group = 0; group < 4; group++) {
1117 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1118 break;
1119 }
1120 if (group >= 4) {
1121 for (group = 0; group < 4; group++) {
1122 if (priv->mirror_group_ports[group] < 0)
1123 break;
1124 }
1125 }
1126
1127 if (group >= 4)
1128 return -ENOSPC;
1129
1130 ctrl_reg = priv->r->mir_ctrl + group * 4;
1131 dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width;
1132 spm_reg = priv->r->mir_spm + group * 4 * priv->port_width;
1133
1134 pr_debug("Using group %d\n", group);
1135 mutex_lock(&priv->reg_mutex);
1136
1137 if (priv->family_id == RTL8380_FAMILY_ID) {
1138 /* Enable mirroring to port across VLANs (bit 11) */
1139 sw_w32(1 << 11 | (mirror->to_local_port << 4) | 1, ctrl_reg);
1140 } else {
1141 /* Enable mirroring to destination port */
1142 sw_w32((mirror->to_local_port << 4) | 1, ctrl_reg);
1143 }
1144
1145 if (ingress && (priv->r->get_port_reg_be(spm_reg) & (1ULL << port))) {
1146 mutex_unlock(&priv->reg_mutex);
1147 return -EEXIST;
1148 }
1149 if ((!ingress) && (priv->r->get_port_reg_be(dpm_reg) & (1ULL << port))) {
1150 mutex_unlock(&priv->reg_mutex);
1151 return -EEXIST;
1152 }
1153
1154 if (ingress)
1155 priv->r->mask_port_reg_be(0, 1ULL << port, spm_reg);
1156 else
1157 priv->r->mask_port_reg_be(0, 1ULL << port, dpm_reg);
1158
1159 priv->mirror_group_ports[group] = mirror->to_local_port;
1160 mutex_unlock(&priv->reg_mutex);
1161 return 0;
1162 }
1163
1164 static void rtl83xx_port_mirror_del(struct dsa_switch *ds, int port,
1165 struct dsa_mall_mirror_tc_entry *mirror)
1166 {
1167 int group = 0;
1168 struct rtl838x_switch_priv *priv = ds->priv;
1169 int ctrl_reg, dpm_reg, spm_reg;
1170
1171 pr_debug("In %s\n", __func__);
1172 for (group = 0; group < 4; group++) {
1173 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1174 break;
1175 }
1176 if (group >= 4)
1177 return;
1178
1179 ctrl_reg = priv->r->mir_ctrl + group * 4;
1180 dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width;
1181 spm_reg = priv->r->mir_spm + group * 4 * priv->port_width;
1182
1183 mutex_lock(&priv->reg_mutex);
1184 if (mirror->ingress) {
1185 /* Ingress, clear source port matrix */
1186 priv->r->mask_port_reg_be(1ULL << port, 0, spm_reg);
1187 } else {
1188 /* Egress, clear destination port matrix */
1189 priv->r->mask_port_reg_be(1ULL << port, 0, dpm_reg);
1190 }
1191
1192 if (!(sw_r32(spm_reg) || sw_r32(dpm_reg))) {
1193 priv->mirror_group_ports[group] = -1;
1194 sw_w32(0, ctrl_reg);
1195 }
1196
1197 mutex_unlock(&priv->reg_mutex);
1198 }
1199
1200 int dsa_phy_read(struct dsa_switch *ds, int phy_addr, int phy_reg)
1201 {
1202 u32 val;
1203 u32 offset = 0;
1204 struct rtl838x_switch_priv *priv = ds->priv;
1205
1206 if (phy_addr >= 24 && phy_addr <= 27
1207 && priv->ports[24].phy == PHY_RTL838X_SDS) {
1208 if (phy_addr == 26)
1209 offset = 0x100;
1210 val = sw_r32(RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2)) & 0xffff;
1211 return val;
1212 }
1213
1214 read_phy(phy_addr, 0, phy_reg, &val);
1215 return val;
1216 }
1217
1218 int dsa_phy_write(struct dsa_switch *ds, int phy_addr, int phy_reg, u16 val)
1219 {
1220 u32 offset = 0;
1221 struct rtl838x_switch_priv *priv = ds->priv;
1222
1223 if (phy_addr >= 24 && phy_addr <= 27
1224 && priv->ports[24].phy == PHY_RTL838X_SDS) {
1225 if (phy_addr == 26)
1226 offset = 0x100;
1227 sw_w32(val, RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2));
1228 return 0;
1229 }
1230 return write_phy(phy_addr, 0, phy_reg, val);
1231 }
1232
1233 const struct dsa_switch_ops rtl83xx_switch_ops = {
1234 .get_tag_protocol = rtl83xx_get_tag_protocol,
1235 .setup = rtl83xx_setup,
1236
1237 .phy_read = dsa_phy_read,
1238 .phy_write = dsa_phy_write,
1239
1240 .phylink_validate = rtl83xx_phylink_validate,
1241 .phylink_mac_link_state = rtl83xx_phylink_mac_link_state,
1242 .phylink_mac_config = rtl83xx_phylink_mac_config,
1243 .phylink_mac_link_down = rtl83xx_phylink_mac_link_down,
1244 .phylink_mac_link_up = rtl83xx_phylink_mac_link_up,
1245
1246 .get_strings = rtl83xx_get_strings,
1247 .get_ethtool_stats = rtl83xx_get_ethtool_stats,
1248 .get_sset_count = rtl83xx_get_sset_count,
1249
1250 .port_enable = rtl83xx_port_enable,
1251 .port_disable = rtl83xx_port_disable,
1252
1253 .get_mac_eee = rtl83xx_get_mac_eee,
1254 .set_mac_eee = rtl83xx_set_mac_eee,
1255
1256 .set_ageing_time = rtl83xx_set_l2aging,
1257 .port_bridge_join = rtl83xx_port_bridge_join,
1258 .port_bridge_leave = rtl83xx_port_bridge_leave,
1259 .port_stp_state_set = rtl83xx_port_stp_state_set,
1260 .port_fast_age = rtl83xx_fast_age,
1261
1262 .port_vlan_filtering = rtl83xx_vlan_filtering,
1263 .port_vlan_prepare = rtl83xx_vlan_prepare,
1264 .port_vlan_add = rtl83xx_vlan_add,
1265 .port_vlan_del = rtl83xx_vlan_del,
1266
1267 .port_fdb_add = rtl83xx_port_fdb_add,
1268 .port_fdb_del = rtl83xx_port_fdb_del,
1269 .port_fdb_dump = rtl83xx_port_fdb_dump,
1270
1271 .port_mirror_add = rtl83xx_port_mirror_add,
1272 .port_mirror_del = rtl83xx_port_mirror_del,
1273 };
1274
1275 const struct dsa_switch_ops rtl930x_switch_ops = {
1276 .get_tag_protocol = rtl83xx_get_tag_protocol,
1277 .setup = rtl930x_setup,
1278
1279 .phy_read = dsa_phy_read,
1280 .phy_write = dsa_phy_write,
1281
1282 .phylink_validate = rtl83xx_phylink_validate,
1283 .phylink_mac_link_state = rtl83xx_phylink_mac_link_state,
1284 .phylink_mac_config = rtl83xx_phylink_mac_config,
1285 .phylink_mac_link_down = rtl83xx_phylink_mac_link_down,
1286 .phylink_mac_link_up = rtl83xx_phylink_mac_link_up,
1287
1288 .get_strings = rtl83xx_get_strings,
1289 .get_ethtool_stats = rtl83xx_get_ethtool_stats,
1290 .get_sset_count = rtl83xx_get_sset_count,
1291
1292 .port_enable = rtl83xx_port_enable,
1293 .port_disable = rtl83xx_port_disable,
1294
1295 .set_ageing_time = rtl83xx_set_l2aging,
1296 .port_bridge_join = rtl83xx_port_bridge_join,
1297 .port_bridge_leave = rtl83xx_port_bridge_leave,
1298 .port_stp_state_set = rtl83xx_port_stp_state_set,
1299 .port_fast_age = rtl930x_fast_age,
1300
1301 .port_vlan_filtering = rtl83xx_vlan_filtering,
1302 .port_vlan_prepare = rtl83xx_vlan_prepare,
1303 .port_vlan_add = rtl83xx_vlan_add,
1304 .port_vlan_del = rtl83xx_vlan_del,
1305
1306 .port_fdb_add = rtl83xx_port_fdb_add,
1307 .port_fdb_del = rtl83xx_port_fdb_del,
1308 .port_fdb_dump = rtl83xx_port_fdb_dump,
1309 };
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