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realtek: update rtl83xx switch driver to the updated DSA API
[openwrt/staging/hauke.git] / target / linux / realtek / files-5.4 / drivers / net / dsa / rtl83xx / dsa.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <net/dsa.h>
4 #include <linux/if_bridge.h>
5
6 #include <asm/mach-rtl838x/mach-rtl83xx.h>
7 #include "rtl83xx.h"
8
9
10 extern struct rtl83xx_soc_info soc_info;
11
12
13 static void rtl83xx_init_stats(struct rtl838x_switch_priv *priv)
14 {
15 mutex_lock(&priv->reg_mutex);
16
17 /* Enable statistics module: all counters plus debug.
18 * On RTL839x all counters are enabled by default
19 */
20 if (priv->family_id == RTL8380_FAMILY_ID)
21 sw_w32_mask(0, 3, RTL838X_STAT_CTRL);
22
23 /* Reset statistics counters */
24 sw_w32_mask(0, 1, priv->r->stat_rst);
25
26 mutex_unlock(&priv->reg_mutex);
27 }
28
29 static void rtl83xx_write_cam(int idx, u32 *r)
30 {
31 u32 cmd = BIT(16) /* Execute cmd */
32 | BIT(15) /* Read */
33 | BIT(13) /* Table type 0b01 */
34 | (idx & 0x3f);
35
36 sw_w32(r[0], RTL838X_TBL_ACCESS_L2_DATA(0));
37 sw_w32(r[1], RTL838X_TBL_ACCESS_L2_DATA(1));
38 sw_w32(r[2], RTL838X_TBL_ACCESS_L2_DATA(2));
39
40 sw_w32(cmd, RTL838X_TBL_ACCESS_L2_CTRL);
41 do { } while (sw_r32(RTL838X_TBL_ACCESS_L2_CTRL) & BIT(16));
42 }
43
44 static u64 rtl83xx_hash_key(struct rtl838x_switch_priv *priv, u64 mac, u32 vid)
45 {
46 switch (priv->family_id) {
47 case RTL8380_FAMILY_ID:
48 return rtl838x_hash(priv, mac << 12 | vid);
49 case RTL8390_FAMILY_ID:
50 return rtl839x_hash(priv, mac << 12 | vid);
51 case RTL9300_FAMILY_ID:
52 return rtl930x_hash(priv, ((u64)vid) << 48 | mac);
53 default:
54 pr_err("Hash not implemented\n");
55 }
56 return 0;
57 }
58
59 static void rtl83xx_write_hash(int idx, u32 *r)
60 {
61 u32 cmd = BIT(16) /* Execute cmd */
62 | 0 << 15 /* Write */
63 | 0 << 13 /* Table type 0b00 */
64 | (idx & 0x1fff);
65
66 sw_w32(0, RTL838X_TBL_ACCESS_L2_DATA(0));
67 sw_w32(0, RTL838X_TBL_ACCESS_L2_DATA(1));
68 sw_w32(0, RTL838X_TBL_ACCESS_L2_DATA(2));
69 sw_w32(cmd, RTL838X_TBL_ACCESS_L2_CTRL);
70 do { } while (sw_r32(RTL838X_TBL_ACCESS_L2_CTRL) & BIT(16));
71 }
72
73 static void rtl83xx_enable_phy_polling(struct rtl838x_switch_priv *priv)
74 {
75 int i;
76 u64 v = 0;
77
78 msleep(1000);
79 /* Enable all ports with a PHY, including the SFP-ports */
80 for (i = 0; i < priv->cpu_port; i++) {
81 if (priv->ports[i].phy)
82 v |= BIT(i);
83 }
84
85 pr_debug("%s: %16llx\n", __func__, v);
86 priv->r->set_port_reg_le(v, priv->r->smi_poll_ctrl);
87
88 /* PHY update complete, there is no global PHY polling enable bit on the 9300 */
89 if (priv->family_id == RTL8390_FAMILY_ID)
90 sw_w32_mask(0, BIT(7), RTL839X_SMI_GLB_CTRL);
91 else if(priv->family_id == RTL9300_FAMILY_ID)
92 sw_w32_mask(0, 0x8000, RTL838X_SMI_GLB_CTRL);
93 }
94
95 const struct rtl83xx_mib_desc rtl83xx_mib[] = {
96 MIB_DESC(2, 0xf8, "ifInOctets"),
97 MIB_DESC(2, 0xf0, "ifOutOctets"),
98 MIB_DESC(1, 0xec, "dot1dTpPortInDiscards"),
99 MIB_DESC(1, 0xe8, "ifInUcastPkts"),
100 MIB_DESC(1, 0xe4, "ifInMulticastPkts"),
101 MIB_DESC(1, 0xe0, "ifInBroadcastPkts"),
102 MIB_DESC(1, 0xdc, "ifOutUcastPkts"),
103 MIB_DESC(1, 0xd8, "ifOutMulticastPkts"),
104 MIB_DESC(1, 0xd4, "ifOutBroadcastPkts"),
105 MIB_DESC(1, 0xd0, "ifOutDiscards"),
106 MIB_DESC(1, 0xcc, ".3SingleCollisionFrames"),
107 MIB_DESC(1, 0xc8, ".3MultipleCollisionFrames"),
108 MIB_DESC(1, 0xc4, ".3DeferredTransmissions"),
109 MIB_DESC(1, 0xc0, ".3LateCollisions"),
110 MIB_DESC(1, 0xbc, ".3ExcessiveCollisions"),
111 MIB_DESC(1, 0xb8, ".3SymbolErrors"),
112 MIB_DESC(1, 0xb4, ".3ControlInUnknownOpcodes"),
113 MIB_DESC(1, 0xb0, ".3InPauseFrames"),
114 MIB_DESC(1, 0xac, ".3OutPauseFrames"),
115 MIB_DESC(1, 0xa8, "DropEvents"),
116 MIB_DESC(1, 0xa4, "tx_BroadcastPkts"),
117 MIB_DESC(1, 0xa0, "tx_MulticastPkts"),
118 MIB_DESC(1, 0x9c, "CRCAlignErrors"),
119 MIB_DESC(1, 0x98, "tx_UndersizePkts"),
120 MIB_DESC(1, 0x94, "rx_UndersizePkts"),
121 MIB_DESC(1, 0x90, "rx_UndersizedropPkts"),
122 MIB_DESC(1, 0x8c, "tx_OversizePkts"),
123 MIB_DESC(1, 0x88, "rx_OversizePkts"),
124 MIB_DESC(1, 0x84, "Fragments"),
125 MIB_DESC(1, 0x80, "Jabbers"),
126 MIB_DESC(1, 0x7c, "Collisions"),
127 MIB_DESC(1, 0x78, "tx_Pkts64Octets"),
128 MIB_DESC(1, 0x74, "rx_Pkts64Octets"),
129 MIB_DESC(1, 0x70, "tx_Pkts65to127Octets"),
130 MIB_DESC(1, 0x6c, "rx_Pkts65to127Octets"),
131 MIB_DESC(1, 0x68, "tx_Pkts128to255Octets"),
132 MIB_DESC(1, 0x64, "rx_Pkts128to255Octets"),
133 MIB_DESC(1, 0x60, "tx_Pkts256to511Octets"),
134 MIB_DESC(1, 0x5c, "rx_Pkts256to511Octets"),
135 MIB_DESC(1, 0x58, "tx_Pkts512to1023Octets"),
136 MIB_DESC(1, 0x54, "rx_Pkts512to1023Octets"),
137 MIB_DESC(1, 0x50, "tx_Pkts1024to1518Octets"),
138 MIB_DESC(1, 0x4c, "rx_StatsPkts1024to1518Octets"),
139 MIB_DESC(1, 0x48, "tx_Pkts1519toMaxOctets"),
140 MIB_DESC(1, 0x44, "rx_Pkts1519toMaxOctets"),
141 MIB_DESC(1, 0x40, "rxMacDiscards")
142 };
143
144
145 /* DSA callbacks */
146
147
148 static enum dsa_tag_protocol rtl83xx_get_tag_protocol(struct dsa_switch *ds,
149 int port,
150 enum dsa_tag_protocol mprot)
151 {
152 /* The switch does not tag the frames, instead internally the header
153 * structure for each packet is tagged accordingly.
154 */
155 return DSA_TAG_PROTO_TRAILER;
156 }
157
158 static int rtl83xx_setup(struct dsa_switch *ds)
159 {
160 int i;
161 struct rtl838x_switch_priv *priv = ds->priv;
162 u64 port_bitmap = BIT_ULL(priv->cpu_port);
163
164 pr_debug("%s called\n", __func__);
165
166 /* Disable MAC polling the PHY so that we can start configuration */
167 priv->r->set_port_reg_le(0ULL, priv->r->smi_poll_ctrl);
168
169 for (i = 0; i < ds->num_ports; i++)
170 priv->ports[i].enable = false;
171 priv->ports[priv->cpu_port].enable = true;
172
173 /* Isolate ports from each other: traffic only CPU <-> port */
174 /* Setting bit j in register RTL838X_PORT_ISO_CTRL(i) allows
175 * traffic from source port i to destination port j
176 */
177 for (i = 0; i < priv->cpu_port; i++) {
178 if (priv->ports[i].phy) {
179 priv->r->set_port_reg_be(BIT_ULL(priv->cpu_port) | BIT(i),
180 priv->r->port_iso_ctrl(i));
181 port_bitmap |= BIT_ULL(i);
182 }
183 }
184 priv->r->set_port_reg_be(port_bitmap, priv->r->port_iso_ctrl(priv->cpu_port));
185
186 if (priv->family_id == RTL8380_FAMILY_ID)
187 rtl838x_print_matrix();
188 else
189 rtl839x_print_matrix();
190
191 rtl83xx_init_stats(priv);
192
193 ds->configure_vlan_while_not_filtering = true;
194
195 /* Enable MAC Polling PHY again */
196 rtl83xx_enable_phy_polling(priv);
197 pr_debug("Please wait until PHY is settled\n");
198 msleep(1000);
199 return 0;
200 }
201
202 static int rtl930x_setup(struct dsa_switch *ds)
203 {
204 int i;
205 struct rtl838x_switch_priv *priv = ds->priv;
206 u32 port_bitmap = BIT(priv->cpu_port);
207
208 pr_info("%s called\n", __func__);
209
210 // Enable CSTI STP mode
211 // sw_w32(1, RTL930X_ST_CTRL);
212
213 /* Disable MAC polling the PHY so that we can start configuration */
214 sw_w32(0, RTL930X_SMI_POLL_CTRL);
215
216 // Disable all ports except CPU port
217 for (i = 0; i < ds->num_ports; i++)
218 priv->ports[i].enable = false;
219 priv->ports[priv->cpu_port].enable = true;
220
221 for (i = 0; i < priv->cpu_port; i++) {
222 if (priv->ports[i].phy) {
223 priv->r->traffic_set(i, BIT(priv->cpu_port) | BIT(i));
224 port_bitmap |= 1ULL << i;
225 }
226 }
227 priv->r->traffic_set(priv->cpu_port, port_bitmap);
228
229 rtl930x_print_matrix();
230
231 // TODO: Initialize statistics
232
233 ds->configure_vlan_while_not_filtering = true;
234
235 rtl83xx_enable_phy_polling(priv);
236
237 return 0;
238 }
239
240 static void rtl83xx_phylink_validate(struct dsa_switch *ds, int port,
241 unsigned long *supported,
242 struct phylink_link_state *state)
243 {
244 struct rtl838x_switch_priv *priv = ds->priv;
245 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
246
247 pr_debug("In %s port %d", __func__, port);
248
249 if (!phy_interface_mode_is_rgmii(state->interface) &&
250 state->interface != PHY_INTERFACE_MODE_NA &&
251 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
252 state->interface != PHY_INTERFACE_MODE_MII &&
253 state->interface != PHY_INTERFACE_MODE_REVMII &&
254 state->interface != PHY_INTERFACE_MODE_GMII &&
255 state->interface != PHY_INTERFACE_MODE_QSGMII &&
256 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
257 state->interface != PHY_INTERFACE_MODE_SGMII) {
258 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
259 dev_err(ds->dev,
260 "Unsupported interface: %d for port %d\n",
261 state->interface, port);
262 return;
263 }
264
265 /* Allow all the expected bits */
266 phylink_set(mask, Autoneg);
267 phylink_set_port_modes(mask);
268 phylink_set(mask, Pause);
269 phylink_set(mask, Asym_Pause);
270
271 /* With the exclusion of MII and Reverse MII, we support Gigabit,
272 * including Half duplex
273 */
274 if (state->interface != PHY_INTERFACE_MODE_MII &&
275 state->interface != PHY_INTERFACE_MODE_REVMII) {
276 phylink_set(mask, 1000baseT_Full);
277 phylink_set(mask, 1000baseT_Half);
278 }
279
280 /* On both the 8380 and 8382, ports 24-27 are SFP ports */
281 if (port >= 24 && port <= 27 && priv->family_id == RTL8380_FAMILY_ID)
282 phylink_set(mask, 1000baseX_Full);
283
284 phylink_set(mask, 10baseT_Half);
285 phylink_set(mask, 10baseT_Full);
286 phylink_set(mask, 100baseT_Half);
287 phylink_set(mask, 100baseT_Full);
288
289 bitmap_and(supported, supported, mask,
290 __ETHTOOL_LINK_MODE_MASK_NBITS);
291 bitmap_and(state->advertising, state->advertising, mask,
292 __ETHTOOL_LINK_MODE_MASK_NBITS);
293 }
294
295 static int rtl83xx_phylink_mac_link_state(struct dsa_switch *ds, int port,
296 struct phylink_link_state *state)
297 {
298 struct rtl838x_switch_priv *priv = ds->priv;
299 u64 speed;
300 u64 link;
301
302 if (port < 0 || port > priv->cpu_port)
303 return -EINVAL;
304
305 /*
306 * On the RTL9300 for at least the RTL8226B PHY, the MAC-side link
307 * state needs to be read twice in order to read a correct result.
308 * This would not be necessary for ports connected e.g. to RTL8218D
309 * PHYs.
310 */
311 state->link = 0;
312 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
313 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
314 if (link & BIT_ULL(port))
315 state->link = 1;
316 pr_debug("%s: link state: %llx\n", __func__, link & BIT_ULL(port));
317
318 state->duplex = 0;
319 if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port))
320 state->duplex = 1;
321
322 speed = priv->r->get_port_reg_le(priv->r->mac_link_spd_sts(port));
323 speed >>= (port % 16) << 1;
324 switch (speed & 0x3) {
325 case 0:
326 state->speed = SPEED_10;
327 break;
328 case 1:
329 state->speed = SPEED_100;
330 break;
331 case 2:
332 state->speed = SPEED_1000;
333 break;
334 case 3:
335 if (port == 24 || port == 26) /* Internal serdes */
336 state->speed = SPEED_2500;
337 else
338 state->speed = SPEED_100; /* Is in fact 500Mbit */
339 }
340
341 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
342 if (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & BIT_ULL(port))
343 state->pause |= MLO_PAUSE_RX;
344 if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port))
345 state->pause |= MLO_PAUSE_TX;
346 return 1;
347 }
348
349
350 static void rtl83xx_config_interface(int port, phy_interface_t interface)
351 {
352 u32 old, int_shift, sds_shift;
353
354 switch (port) {
355 case 24:
356 int_shift = 0;
357 sds_shift = 5;
358 break;
359 case 26:
360 int_shift = 3;
361 sds_shift = 0;
362 break;
363 default:
364 return;
365 }
366
367 old = sw_r32(RTL838X_SDS_MODE_SEL);
368 switch (interface) {
369 case PHY_INTERFACE_MODE_1000BASEX:
370 if ((old >> sds_shift & 0x1f) == 4)
371 return;
372 sw_w32_mask(0x7 << int_shift, 1 << int_shift, RTL838X_INT_MODE_CTRL);
373 sw_w32_mask(0x1f << sds_shift, 4 << sds_shift, RTL838X_SDS_MODE_SEL);
374 break;
375 case PHY_INTERFACE_MODE_SGMII:
376 if ((old >> sds_shift & 0x1f) == 2)
377 return;
378 sw_w32_mask(0x7 << int_shift, 2 << int_shift, RTL838X_INT_MODE_CTRL);
379 sw_w32_mask(0x1f << sds_shift, 2 << sds_shift, RTL838X_SDS_MODE_SEL);
380 break;
381 default:
382 return;
383 }
384 pr_debug("configured port %d for interface %s\n", port, phy_modes(interface));
385 }
386
387 static void rtl83xx_phylink_mac_config(struct dsa_switch *ds, int port,
388 unsigned int mode,
389 const struct phylink_link_state *state)
390 {
391 struct rtl838x_switch_priv *priv = ds->priv;
392 u32 reg;
393 int speed_bit = priv->family_id == RTL8380_FAMILY_ID ? 4 : 3;
394
395 pr_debug("%s port %d, mode %x\n", __func__, port, mode);
396
397 // BUG: Make this work on RTL93XX
398 if (priv->family_id >= RTL9300_FAMILY_ID)
399 return;
400
401 if (port == priv->cpu_port) {
402 /* Set Speed, duplex, flow control
403 * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL
404 * | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN
405 * | MEDIA_SEL
406 */
407 if (priv->family_id == RTL8380_FAMILY_ID) {
408 sw_w32(0x6192F, priv->r->mac_force_mode_ctrl(priv->cpu_port));
409 /* allow CRC errors on CPU-port */
410 sw_w32_mask(0, 0x8, RTL838X_MAC_PORT_CTRL(priv->cpu_port));
411 } else {
412 sw_w32_mask(0, 3, priv->r->mac_force_mode_ctrl(priv->cpu_port));
413 }
414 return;
415 }
416
417 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
418 /* Auto-Negotiation does not work for MAC in RTL8390 */
419 if (priv->family_id == RTL8380_FAMILY_ID) {
420 if (mode == MLO_AN_PHY || phylink_autoneg_inband(mode)) {
421 pr_debug("PHY autonegotiates\n");
422 reg |= BIT(2);
423 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
424 rtl83xx_config_interface(port, state->interface);
425 return;
426 }
427 }
428
429 if (mode != MLO_AN_FIXED)
430 pr_debug("Fixed state.\n");
431
432 if (priv->family_id == RTL8380_FAMILY_ID) {
433 /* Clear id_mode_dis bit, and the existing port mode, let
434 * RGMII_MODE_EN bet set by mac_link_{up,down}
435 */
436 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
437
438 if (state->pause & MLO_PAUSE_TXRX_MASK) {
439 if (state->pause & MLO_PAUSE_TX)
440 reg |= TX_PAUSE_EN;
441 reg |= RX_PAUSE_EN;
442 }
443 }
444
445 reg &= ~(3 << speed_bit);
446 switch (state->speed) {
447 case SPEED_1000:
448 reg |= 2 << speed_bit;
449 break;
450 case SPEED_100:
451 reg |= 1 << speed_bit;
452 break;
453 }
454
455 if (priv->family_id == RTL8380_FAMILY_ID) {
456 reg &= ~(DUPLEX_FULL | FORCE_LINK_EN);
457 if (state->link)
458 reg |= FORCE_LINK_EN;
459 if (state->duplex == DUPLEX_FULL)
460 reg |= DUPLX_MODE;
461 }
462
463 // Disable AN
464 if (priv->family_id == RTL8380_FAMILY_ID)
465 reg &= ~BIT(2);
466 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
467 }
468
469 static void rtl83xx_phylink_mac_link_down(struct dsa_switch *ds, int port,
470 unsigned int mode,
471 phy_interface_t interface)
472 {
473 struct rtl838x_switch_priv *priv = ds->priv;
474 /* Stop TX/RX to port */
475 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port));
476 }
477
478 static void rtl83xx_phylink_mac_link_up(struct dsa_switch *ds, int port,
479 unsigned int mode,
480 phy_interface_t interface,
481 struct phy_device *phydev)
482 {
483 struct rtl838x_switch_priv *priv = ds->priv;
484 /* Restart TX/RX to port */
485 sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port));
486 }
487
488 static void rtl83xx_get_strings(struct dsa_switch *ds,
489 int port, u32 stringset, u8 *data)
490 {
491 int i;
492
493 if (stringset != ETH_SS_STATS)
494 return;
495
496 for (i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++)
497 strncpy(data + i * ETH_GSTRING_LEN, rtl83xx_mib[i].name,
498 ETH_GSTRING_LEN);
499 }
500
501 static void rtl83xx_get_ethtool_stats(struct dsa_switch *ds, int port,
502 uint64_t *data)
503 {
504 struct rtl838x_switch_priv *priv = ds->priv;
505 const struct rtl83xx_mib_desc *mib;
506 int i;
507 u64 h;
508
509 for (i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++) {
510 mib = &rtl83xx_mib[i];
511
512 data[i] = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 252 - mib->offset);
513 if (mib->size == 2) {
514 h = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 248 - mib->offset);
515 data[i] |= h << 32;
516 }
517 }
518 }
519
520 static int rtl83xx_get_sset_count(struct dsa_switch *ds, int port, int sset)
521 {
522 if (sset != ETH_SS_STATS)
523 return 0;
524
525 return ARRAY_SIZE(rtl83xx_mib);
526 }
527
528 static int rtl83xx_port_enable(struct dsa_switch *ds, int port,
529 struct phy_device *phydev)
530 {
531 struct rtl838x_switch_priv *priv = ds->priv;
532 u64 v;
533
534 pr_debug("%s: %x %d", __func__, (u32) priv, port);
535 priv->ports[port].enable = true;
536
537 /* enable inner tagging on egress, do not keep any tags */
538 if (priv->family_id == RTL9310_FAMILY_ID)
539 sw_w32(BIT(4), priv->r->vlan_port_tag_sts_ctrl + (port << 2));
540 else
541 sw_w32(1, priv->r->vlan_port_tag_sts_ctrl + (port << 2));
542
543 if (dsa_is_cpu_port(ds, port))
544 return 0;
545
546 /* add port to switch mask of CPU_PORT */
547 priv->r->traffic_enable(priv->cpu_port, port);
548
549 /* add all other ports in the same bridge to switch mask of port */
550 v = priv->r->traffic_get(port);
551 v |= priv->ports[port].pm;
552 priv->r->traffic_set(port, v);
553
554 sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_SABLK_CTRL);
555 sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_DABLK_CTRL);
556
557 return 0;
558 }
559
560 static void rtl83xx_port_disable(struct dsa_switch *ds, int port)
561 {
562 struct rtl838x_switch_priv *priv = ds->priv;
563 u64 v;
564
565 pr_debug("%s %x: %d", __func__, (u32)priv, port);
566 /* you can only disable user ports */
567 if (!dsa_is_user_port(ds, port))
568 return;
569
570 // BUG: This does not work on RTL931X
571 /* remove port from switch mask of CPU_PORT */
572 priv->r->traffic_disable(priv->cpu_port, port);
573
574 /* remove all other ports in the same bridge from switch mask of port */
575 v = priv->r->traffic_get(port);
576 v &= ~priv->ports[port].pm;
577 priv->r->traffic_set(port, v);
578
579 priv->ports[port].enable = false;
580 }
581
582 static int rtl83xx_get_mac_eee(struct dsa_switch *ds, int port,
583 struct ethtool_eee *e)
584 {
585 struct rtl838x_switch_priv *priv = ds->priv;
586
587 pr_debug("%s: port %d", __func__, port);
588 e->supported = SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full;
589 if (sw_r32(priv->r->mac_force_mode_ctrl(port)) & BIT(9))
590 e->advertised |= ADVERTISED_100baseT_Full;
591
592 if (sw_r32(priv->r->mac_force_mode_ctrl(port)) & BIT(10))
593 e->advertised |= ADVERTISED_1000baseT_Full;
594
595 e->eee_enabled = priv->ports[port].eee_enabled;
596 pr_debug("enabled: %d, active %x\n", e->eee_enabled, e->advertised);
597
598 if (sw_r32(RTL838X_MAC_EEE_ABLTY) & BIT(port)) {
599 e->lp_advertised = ADVERTISED_100baseT_Full;
600 e->lp_advertised |= ADVERTISED_1000baseT_Full;
601 }
602
603 e->eee_active = !!(e->advertised & e->lp_advertised);
604 pr_debug("active: %d, lp %x\n", e->eee_active, e->lp_advertised);
605
606 return 0;
607 }
608
609 static int rtl83xx_set_mac_eee(struct dsa_switch *ds, int port,
610 struct ethtool_eee *e)
611 {
612 struct rtl838x_switch_priv *priv = ds->priv;
613
614 pr_debug("%s: port %d", __func__, port);
615 if (e->eee_enabled) {
616 pr_debug("Globally enabling EEE\n");
617 sw_w32_mask(0x4, 0, RTL838X_SMI_GLB_CTRL);
618 }
619 if (e->eee_enabled) {
620 pr_debug("Enabling EEE for MAC %d\n", port);
621 sw_w32_mask(0, 3 << 9, priv->r->mac_force_mode_ctrl(port));
622 sw_w32_mask(0, BIT(port), RTL838X_EEE_PORT_TX_EN);
623 sw_w32_mask(0, BIT(port), RTL838X_EEE_PORT_RX_EN);
624 priv->ports[port].eee_enabled = true;
625 e->eee_enabled = true;
626 } else {
627 pr_debug("Disabling EEE for MAC %d\n", port);
628 sw_w32_mask(3 << 9, 0, priv->r->mac_force_mode_ctrl(port));
629 sw_w32_mask(BIT(port), 0, RTL838X_EEE_PORT_TX_EN);
630 sw_w32_mask(BIT(port), 0, RTL838X_EEE_PORT_RX_EN);
631 priv->ports[port].eee_enabled = false;
632 e->eee_enabled = false;
633 }
634 return 0;
635 }
636
637 /*
638 * Set Switch L2 Aging time, t is time in milliseconds
639 * t = 0: aging is disabled
640 */
641 static int rtl83xx_set_l2aging(struct dsa_switch *ds, u32 t)
642 {
643 struct rtl838x_switch_priv *priv = ds->priv;
644 int t_max = priv->family_id == RTL8380_FAMILY_ID ? 0x7fffff : 0x1FFFFF;
645
646 /* Convert time in mseconds to internal value */
647 if (t > 0x10000000) { /* Set to maximum */
648 t = t_max;
649 } else {
650 if (priv->family_id == RTL8380_FAMILY_ID)
651 t = ((t * 625) / 1000 + 127) / 128;
652 else
653 t = (t * 5 + 2) / 3;
654 }
655 sw_w32(t, priv->r->l2_ctrl_1);
656 return 0;
657 }
658
659 static int rtl83xx_port_bridge_join(struct dsa_switch *ds, int port,
660 struct net_device *bridge)
661 {
662 struct rtl838x_switch_priv *priv = ds->priv;
663 u64 port_bitmap = 1ULL << priv->cpu_port, v;
664 int i;
665
666 pr_debug("%s %x: %d %llx", __func__, (u32)priv, port, port_bitmap);
667 mutex_lock(&priv->reg_mutex);
668 for (i = 0; i < ds->num_ports; i++) {
669 /* Add this port to the port matrix of the other ports in the
670 * same bridge. If the port is disabled, port matrix is kept
671 * and not being setup until the port becomes enabled.
672 */
673 if (dsa_is_user_port(ds, i) && i != port) {
674 if (dsa_to_port(ds, i)->bridge_dev != bridge)
675 continue;
676 if (priv->ports[i].enable)
677 priv->r->traffic_enable(i, port);
678
679 priv->ports[i].pm |= 1ULL << port;
680 port_bitmap |= 1ULL << i;
681 }
682 }
683
684 /* Add all other ports to this port matrix. */
685 if (priv->ports[port].enable) {
686 priv->r->traffic_enable(priv->cpu_port, port);
687 v = priv->r->traffic_get(port);
688 v |= port_bitmap;
689 priv->r->traffic_set(port, v);
690 }
691 priv->ports[port].pm |= port_bitmap;
692 mutex_unlock(&priv->reg_mutex);
693
694 return 0;
695 }
696
697 static void rtl83xx_port_bridge_leave(struct dsa_switch *ds, int port,
698 struct net_device *bridge)
699 {
700 struct rtl838x_switch_priv *priv = ds->priv;
701 u64 port_bitmap = 1ULL << priv->cpu_port, v;
702 int i;
703
704 pr_debug("%s %x: %d", __func__, (u32)priv, port);
705 mutex_lock(&priv->reg_mutex);
706 for (i = 0; i < ds->num_ports; i++) {
707 /* Remove this port from the port matrix of the other ports
708 * in the same bridge. If the port is disabled, port matrix
709 * is kept and not being setup until the port becomes enabled.
710 * And the other port's port matrix cannot be broken when the
711 * other port is still a VLAN-aware port.
712 */
713 if (dsa_is_user_port(ds, i) && i != port) {
714 if (dsa_to_port(ds, i)->bridge_dev != bridge)
715 continue;
716 if (priv->ports[i].enable)
717 priv->r->traffic_disable(i, port);
718
719 priv->ports[i].pm |= 1ULL << port;
720 port_bitmap &= ~BIT_ULL(i);
721 }
722 }
723
724 /* Add all other ports to this port matrix. */
725 if (priv->ports[port].enable) {
726 v = priv->r->traffic_get(port);
727 v |= port_bitmap;
728 priv->r->traffic_set(port, v);
729 }
730 priv->ports[port].pm &= ~port_bitmap;
731
732 mutex_unlock(&priv->reg_mutex);
733 }
734
735 void rtl83xx_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
736 {
737 u32 msti = 0;
738 u32 port_state[4];
739 int index, bit;
740 int pos = port;
741 struct rtl838x_switch_priv *priv = ds->priv;
742 int n = priv->port_width << 1;
743
744 /* Ports above or equal CPU port can never be configured */
745 if (port >= priv->cpu_port)
746 return;
747
748 mutex_lock(&priv->reg_mutex);
749
750 /* For the RTL839x and following, the bits are left-aligned, 838x and 930x
751 * have 64 bit fields, 839x and 931x have 128 bit fields
752 */
753 if (priv->family_id == RTL8390_FAMILY_ID)
754 pos += 12;
755 if (priv->family_id == RTL9300_FAMILY_ID)
756 pos += 3;
757 if (priv->family_id == RTL9310_FAMILY_ID)
758 pos += 8;
759
760 index = n - (pos >> 4) - 1;
761 bit = (pos << 1) % 32;
762
763 priv->r->stp_get(priv, msti, port_state);
764
765 pr_debug("Current state, port %d: %d\n", port, (port_state[index] >> bit) & 3);
766 port_state[index] &= ~(3 << bit);
767
768 switch (state) {
769 case BR_STATE_DISABLED: /* 0 */
770 port_state[index] |= (0 << bit);
771 break;
772 case BR_STATE_BLOCKING: /* 4 */
773 case BR_STATE_LISTENING: /* 1 */
774 port_state[index] |= (1 << bit);
775 break;
776 case BR_STATE_LEARNING: /* 2 */
777 port_state[index] |= (2 << bit);
778 break;
779 case BR_STATE_FORWARDING: /* 3*/
780 port_state[index] |= (3 << bit);
781 default:
782 break;
783 }
784
785 priv->r->stp_set(priv, msti, port_state);
786
787 mutex_unlock(&priv->reg_mutex);
788 }
789
790 void rtl83xx_fast_age(struct dsa_switch *ds, int port)
791 {
792 struct rtl838x_switch_priv *priv = ds->priv;
793 int s = priv->family_id == RTL8390_FAMILY_ID ? 2 : 0;
794
795 pr_debug("FAST AGE port %d\n", port);
796 mutex_lock(&priv->reg_mutex);
797 /* RTL838X_L2_TBL_FLUSH_CTRL register bits, 839x has 1 bit larger
798 * port fields:
799 * 0-4: Replacing port
800 * 5-9: Flushed/replaced port
801 * 10-21: FVID
802 * 22: Entry types: 1: dynamic, 0: also static
803 * 23: Match flush port
804 * 24: Match FVID
805 * 25: Flush (0) or replace (1) L2 entries
806 * 26: Status of action (1: Start, 0: Done)
807 */
808 sw_w32(1 << (26 + s) | 1 << (23 + s) | port << (5 + (s / 2)), priv->r->l2_tbl_flush_ctrl);
809
810 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(26 + s));
811
812 mutex_unlock(&priv->reg_mutex);
813 }
814
815 void rtl930x_fast_age(struct dsa_switch *ds, int port)
816 {
817 struct rtl838x_switch_priv *priv = ds->priv;
818
819 pr_debug("FAST AGE port %d\n", port);
820 mutex_lock(&priv->reg_mutex);
821 sw_w32(port << 11, RTL930X_L2_TBL_FLUSH_CTRL + 4);
822
823 sw_w32(BIT(26) | BIT(30), RTL930X_L2_TBL_FLUSH_CTRL);
824
825 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(30));
826
827 mutex_unlock(&priv->reg_mutex);
828 }
829
830 static int rtl83xx_vlan_filtering(struct dsa_switch *ds, int port,
831 bool vlan_filtering)
832 {
833 struct rtl838x_switch_priv *priv = ds->priv;
834
835 pr_debug("%s: port %d\n", __func__, port);
836 mutex_lock(&priv->reg_mutex);
837
838 if (vlan_filtering) {
839 /* Enable ingress and egress filtering
840 * The VLAN_PORT_IGR_FILTER register uses 2 bits for each port to define
841 * the filter action:
842 * 0: Always Forward
843 * 1: Drop packet
844 * 2: Trap packet to CPU port
845 * The Egress filter used 1 bit per state (0: DISABLED, 1: ENABLED)
846 */
847 if (port != priv->cpu_port)
848 sw_w32_mask(0b10 << ((port % 16) << 1), 0b01 << ((port % 16) << 1),
849 priv->r->vlan_port_igr_filter + ((port >> 5) << 2));
850 sw_w32_mask(0, BIT(port % 32), priv->r->vlan_port_egr_filter + ((port >> 4) << 2));
851 } else {
852 /* Disable ingress and egress filtering */
853 if (port != priv->cpu_port)
854 sw_w32_mask(0b11 << ((port % 16) << 1), 0,
855 priv->r->vlan_port_igr_filter + ((port >> 5) << 2));
856 sw_w32_mask(BIT(port % 32), 0, priv->r->vlan_port_egr_filter + ((port >> 4) << 2));
857 }
858
859 /* Do we need to do something to the CPU-Port, too? */
860 mutex_unlock(&priv->reg_mutex);
861
862 return 0;
863 }
864
865 static int rtl83xx_vlan_prepare(struct dsa_switch *ds, int port,
866 const struct switchdev_obj_port_vlan *vlan)
867 {
868 struct rtl838x_vlan_info info;
869 struct rtl838x_switch_priv *priv = ds->priv;
870
871 pr_info("%s: port %d\n", __func__, port);
872
873 mutex_lock(&priv->reg_mutex);
874
875 priv->r->vlan_profile_dump(1);
876 priv->r->vlan_tables_read(1, &info);
877
878 pr_info("Tagged ports %llx, untag %llx, prof %x, MC# %d, UC# %d, FID %x\n",
879 info.tagged_ports, info.untagged_ports, info.profile_id,
880 info.hash_mc_fid, info.hash_uc_fid, info.fid);
881
882 priv->r->vlan_set_untagged(1, info.untagged_ports);
883 pr_debug("SET: Untagged ports, VLAN %d: %llx\n", 1, info.untagged_ports);
884
885 priv->r->vlan_set_tagged(1, &info);
886 pr_debug("SET: Tagged ports, VLAN %d: %llx\n", 1, info.tagged_ports);
887
888 mutex_unlock(&priv->reg_mutex);
889 return 0;
890 }
891
892 static void rtl83xx_vlan_add(struct dsa_switch *ds, int port,
893 const struct switchdev_obj_port_vlan *vlan)
894 {
895 struct rtl838x_vlan_info info;
896 struct rtl838x_switch_priv *priv = ds->priv;
897 int v;
898
899 pr_info("%s port %d, vid_end %d, vid_end %d, flags %x\n", __func__,
900 port, vlan->vid_begin, vlan->vid_end, vlan->flags);
901
902 if (vlan->vid_begin > 4095 || vlan->vid_end > 4095) {
903 dev_err(priv->dev, "VLAN out of range: %d - %d",
904 vlan->vid_begin, vlan->vid_end);
905 return;
906 }
907
908 mutex_lock(&priv->reg_mutex);
909
910 if (vlan->flags & BRIDGE_VLAN_INFO_PVID) {
911 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
912 if (!v)
913 continue;
914 /* Set both inner and outer PVID of the port */
915 sw_w32((v << 16) | v << 2, priv->r->vlan_port_pb + (port << 2));
916 priv->ports[port].pvid = vlan->vid_end;
917 }
918 }
919
920 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
921 if (!v)
922 continue;
923
924 /* Get port memberships of this vlan */
925 priv->r->vlan_tables_read(v, &info);
926
927 /* new VLAN? */
928 if (!info.tagged_ports) {
929 info.fid = 0;
930 info.hash_mc_fid = false;
931 info.hash_uc_fid = false;
932 info.profile_id = 0;
933 }
934
935 /* sanitize untagged_ports - must be a subset */
936 if (info.untagged_ports & ~info.tagged_ports)
937 info.untagged_ports = 0;
938
939 info.tagged_ports |= BIT_ULL(port);
940 if (vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED)
941 info.untagged_ports |= BIT_ULL(port);
942
943 priv->r->vlan_set_untagged(v, info.untagged_ports);
944 pr_info("Untagged ports, VLAN %d: %llx\n", v, info.untagged_ports);
945
946 priv->r->vlan_set_tagged(v, &info);
947 pr_info("Tagged ports, VLAN %d: %llx\n", v, info.tagged_ports);
948 }
949
950 mutex_unlock(&priv->reg_mutex);
951 }
952
953 static int rtl83xx_vlan_del(struct dsa_switch *ds, int port,
954 const struct switchdev_obj_port_vlan *vlan)
955 {
956 struct rtl838x_vlan_info info;
957 struct rtl838x_switch_priv *priv = ds->priv;
958 int v;
959 u16 pvid;
960
961 pr_debug("%s: port %d, vid_end %d, vid_end %d, flags %x\n", __func__,
962 port, vlan->vid_begin, vlan->vid_end, vlan->flags);
963
964 if (vlan->vid_begin > 4095 || vlan->vid_end > 4095) {
965 dev_err(priv->dev, "VLAN out of range: %d - %d",
966 vlan->vid_begin, vlan->vid_end);
967 return -ENOTSUPP;
968 }
969
970 mutex_lock(&priv->reg_mutex);
971 pvid = priv->ports[port].pvid;
972
973 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
974 /* Reset to default if removing the current PVID */
975 if (v == pvid)
976 sw_w32(0, priv->r->vlan_port_pb + (port << 2));
977
978 /* Get port memberships of this vlan */
979 priv->r->vlan_tables_read(v, &info);
980
981 /* remove port from both tables */
982 info.untagged_ports &= (~BIT_ULL(port));
983 /* always leave vid 1 */
984 if (v != 1)
985 info.tagged_ports &= (~BIT_ULL(port));
986
987 priv->r->vlan_set_untagged(v, info.untagged_ports);
988 pr_debug("Untagged ports, VLAN %d: %llx\n", v, info.untagged_ports);
989
990 priv->r->vlan_set_tagged(v, &info);
991 pr_debug("Tagged ports, VLAN %d: %llx\n", v, info.tagged_ports);
992 }
993 mutex_unlock(&priv->reg_mutex);
994
995 return 0;
996 }
997
998 static int rtl83xx_port_fdb_add(struct dsa_switch *ds, int port,
999 const unsigned char *addr, u16 vid)
1000 {
1001 struct rtl838x_switch_priv *priv = ds->priv;
1002 u64 mac = ether_addr_to_u64(addr);
1003 u32 key = rtl83xx_hash_key(priv, mac, vid);
1004 struct rtl838x_l2_entry e;
1005 u32 r[3];
1006 u64 entry;
1007 int idx = -1, err = 0, i;
1008
1009 mutex_lock(&priv->reg_mutex);
1010 for (i = 0; i < 4; i++) {
1011 entry = priv->r->read_l2_entry_using_hash(key, i, &e);
1012 if (!e.valid) {
1013 idx = (key << 2) | i;
1014 break;
1015 }
1016 if ((entry & 0x0fffffffffffffffULL) == ((mac << 12) | vid)) {
1017 idx = (key << 2) | i;
1018 break;
1019 }
1020 }
1021 if (idx >= 0) {
1022 r[0] = 3 << 17 | port << 12; // Aging and port
1023 r[0] |= vid;
1024 r[1] = mac >> 16;
1025 r[2] = (mac & 0xffff) << 12; /* rvid = 0 */
1026 rtl83xx_write_hash(idx, r);
1027 goto out;
1028 }
1029
1030 /* Hash buckets full, try CAM */
1031 for (i = 0; i < 64; i++) {
1032 entry = priv->r->read_cam(i, &e);
1033 if (!e.valid) {
1034 if (idx < 0) /* First empty entry? */
1035 idx = i;
1036 break;
1037 } else if ((entry & 0x0fffffffffffffffULL) == ((mac << 12) | vid)) {
1038 pr_debug("Found entry in CAM\n");
1039 idx = i;
1040 break;
1041 }
1042 }
1043 if (idx >= 0) {
1044 r[0] = 3 << 17 | port << 12; // Aging
1045 r[0] |= vid;
1046 r[1] = mac >> 16;
1047 r[2] = (mac & 0xffff) << 12; /* rvid = 0 */
1048 rtl83xx_write_cam(idx, r);
1049 goto out;
1050 }
1051 err = -ENOTSUPP;
1052 out:
1053 mutex_unlock(&priv->reg_mutex);
1054 return err;
1055 }
1056
1057 static int rtl83xx_port_fdb_del(struct dsa_switch *ds, int port,
1058 const unsigned char *addr, u16 vid)
1059 {
1060 struct rtl838x_switch_priv *priv = ds->priv;
1061 u64 mac = ether_addr_to_u64(addr);
1062 u32 key = rtl83xx_hash_key(priv, mac, vid);
1063 struct rtl838x_l2_entry e;
1064 u32 r[3];
1065 u64 entry;
1066 int idx = -1, err = 0, i;
1067
1068 pr_debug("In %s, mac %llx, vid: %d, key: %x08x\n", __func__, mac, vid, key);
1069 mutex_lock(&priv->reg_mutex);
1070 for (i = 0; i < 4; i++) {
1071 entry = priv->r->read_l2_entry_using_hash(key, i, &e);
1072 if (!e.valid)
1073 continue;
1074 if ((entry & 0x0fffffffffffffffULL) == ((mac << 12) | vid)) {
1075 idx = (key << 2) | i;
1076 break;
1077 }
1078 }
1079
1080 if (idx >= 0) {
1081 r[0] = r[1] = r[2] = 0;
1082 rtl83xx_write_hash(idx, r);
1083 goto out;
1084 }
1085
1086 /* Check CAM for spillover from hash buckets */
1087 for (i = 0; i < 64; i++) {
1088 entry = priv->r->read_cam(i, &e);
1089 if ((entry & 0x0fffffffffffffffULL) == ((mac << 12) | vid)) {
1090 idx = i;
1091 break;
1092 }
1093 }
1094 if (idx >= 0) {
1095 r[0] = r[1] = r[2] = 0;
1096 rtl83xx_write_cam(idx, r);
1097 goto out;
1098 }
1099 err = -ENOENT;
1100 out:
1101 mutex_unlock(&priv->reg_mutex);
1102 return err;
1103 }
1104
1105 static int rtl83xx_port_fdb_dump(struct dsa_switch *ds, int port,
1106 dsa_fdb_dump_cb_t *cb, void *data)
1107 {
1108 struct rtl838x_l2_entry e;
1109 struct rtl838x_switch_priv *priv = ds->priv;
1110 int i;
1111 u32 fid;
1112 u32 pkey;
1113 u64 mac;
1114
1115 mutex_lock(&priv->reg_mutex);
1116
1117 for (i = 0; i < priv->fib_entries; i++) {
1118 priv->r->read_l2_entry_using_hash(i >> 2, i & 0x3, &e);
1119
1120 if (!e.valid)
1121 continue;
1122
1123 if (e.port == port) {
1124 fid = (i & 0x3ff) | (e.rvid & ~0x3ff);
1125 mac = ether_addr_to_u64(&e.mac[0]);
1126 pkey = rtl838x_hash(priv, mac << 12 | fid);
1127 fid = (pkey & 0x3ff) | (fid & ~0x3ff);
1128 pr_debug("-> mac %016llx, fid: %d\n", mac, fid);
1129 cb(e.mac, e.vid, e.is_static, data);
1130 }
1131 }
1132
1133 for (i = 0; i < 64; i++) {
1134 priv->r->read_cam(i, &e);
1135
1136 if (!e.valid)
1137 continue;
1138
1139 if (e.port == port)
1140 cb(e.mac, e.vid, e.is_static, data);
1141 }
1142
1143 mutex_unlock(&priv->reg_mutex);
1144 return 0;
1145 }
1146
1147 static int rtl83xx_port_mirror_add(struct dsa_switch *ds, int port,
1148 struct dsa_mall_mirror_tc_entry *mirror,
1149 bool ingress)
1150 {
1151 /* We support 4 mirror groups, one destination port per group */
1152 int group;
1153 struct rtl838x_switch_priv *priv = ds->priv;
1154 int ctrl_reg, dpm_reg, spm_reg;
1155
1156 pr_debug("In %s\n", __func__);
1157
1158 for (group = 0; group < 4; group++) {
1159 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1160 break;
1161 }
1162 if (group >= 4) {
1163 for (group = 0; group < 4; group++) {
1164 if (priv->mirror_group_ports[group] < 0)
1165 break;
1166 }
1167 }
1168
1169 if (group >= 4)
1170 return -ENOSPC;
1171
1172 ctrl_reg = priv->r->mir_ctrl + group * 4;
1173 dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width;
1174 spm_reg = priv->r->mir_spm + group * 4 * priv->port_width;
1175
1176 pr_debug("Using group %d\n", group);
1177 mutex_lock(&priv->reg_mutex);
1178
1179 if (priv->family_id == RTL8380_FAMILY_ID) {
1180 /* Enable mirroring to port across VLANs (bit 11) */
1181 sw_w32(1 << 11 | (mirror->to_local_port << 4) | 1, ctrl_reg);
1182 } else {
1183 /* Enable mirroring to destination port */
1184 sw_w32((mirror->to_local_port << 4) | 1, ctrl_reg);
1185 }
1186
1187 if (ingress && (priv->r->get_port_reg_be(spm_reg) & (1ULL << port))) {
1188 mutex_unlock(&priv->reg_mutex);
1189 return -EEXIST;
1190 }
1191 if ((!ingress) && (priv->r->get_port_reg_be(dpm_reg) & (1ULL << port))) {
1192 mutex_unlock(&priv->reg_mutex);
1193 return -EEXIST;
1194 }
1195
1196 if (ingress)
1197 priv->r->mask_port_reg_be(0, 1ULL << port, spm_reg);
1198 else
1199 priv->r->mask_port_reg_be(0, 1ULL << port, dpm_reg);
1200
1201 priv->mirror_group_ports[group] = mirror->to_local_port;
1202 mutex_unlock(&priv->reg_mutex);
1203 return 0;
1204 }
1205
1206 static void rtl83xx_port_mirror_del(struct dsa_switch *ds, int port,
1207 struct dsa_mall_mirror_tc_entry *mirror)
1208 {
1209 int group = 0;
1210 struct rtl838x_switch_priv *priv = ds->priv;
1211 int ctrl_reg, dpm_reg, spm_reg;
1212
1213 pr_debug("In %s\n", __func__);
1214 for (group = 0; group < 4; group++) {
1215 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1216 break;
1217 }
1218 if (group >= 4)
1219 return;
1220
1221 ctrl_reg = priv->r->mir_ctrl + group * 4;
1222 dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width;
1223 spm_reg = priv->r->mir_spm + group * 4 * priv->port_width;
1224
1225 mutex_lock(&priv->reg_mutex);
1226 if (mirror->ingress) {
1227 /* Ingress, clear source port matrix */
1228 priv->r->mask_port_reg_be(1ULL << port, 0, spm_reg);
1229 } else {
1230 /* Egress, clear destination port matrix */
1231 priv->r->mask_port_reg_be(1ULL << port, 0, dpm_reg);
1232 }
1233
1234 if (!(sw_r32(spm_reg) || sw_r32(dpm_reg))) {
1235 priv->mirror_group_ports[group] = -1;
1236 sw_w32(0, ctrl_reg);
1237 }
1238
1239 mutex_unlock(&priv->reg_mutex);
1240 }
1241
1242 int dsa_phy_read(struct dsa_switch *ds, int phy_addr, int phy_reg)
1243 {
1244 u32 val;
1245 u32 offset = 0;
1246 struct rtl838x_switch_priv *priv = ds->priv;
1247
1248 if (phy_addr >= 24 && phy_addr <= 27
1249 && priv->ports[24].phy == PHY_RTL838X_SDS) {
1250 if (phy_addr == 26)
1251 offset = 0x100;
1252 val = sw_r32(RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2)) & 0xffff;
1253 return val;
1254 }
1255
1256 read_phy(phy_addr, 0, phy_reg, &val);
1257 return val;
1258 }
1259
1260 int dsa_phy_write(struct dsa_switch *ds, int phy_addr, int phy_reg, u16 val)
1261 {
1262 u32 offset = 0;
1263 struct rtl838x_switch_priv *priv = ds->priv;
1264
1265 if (phy_addr >= 24 && phy_addr <= 27
1266 && priv->ports[24].phy == PHY_RTL838X_SDS) {
1267 if (phy_addr == 26)
1268 offset = 0x100;
1269 sw_w32(val, RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2));
1270 return 0;
1271 }
1272 return write_phy(phy_addr, 0, phy_reg, val);
1273 }
1274
1275 const struct dsa_switch_ops rtl83xx_switch_ops = {
1276 .get_tag_protocol = rtl83xx_get_tag_protocol,
1277 .setup = rtl83xx_setup,
1278
1279 .phy_read = dsa_phy_read,
1280 .phy_write = dsa_phy_write,
1281
1282 .phylink_validate = rtl83xx_phylink_validate,
1283 .phylink_mac_link_state = rtl83xx_phylink_mac_link_state,
1284 .phylink_mac_config = rtl83xx_phylink_mac_config,
1285 .phylink_mac_link_down = rtl83xx_phylink_mac_link_down,
1286 .phylink_mac_link_up = rtl83xx_phylink_mac_link_up,
1287
1288 .get_strings = rtl83xx_get_strings,
1289 .get_ethtool_stats = rtl83xx_get_ethtool_stats,
1290 .get_sset_count = rtl83xx_get_sset_count,
1291
1292 .port_enable = rtl83xx_port_enable,
1293 .port_disable = rtl83xx_port_disable,
1294
1295 .get_mac_eee = rtl83xx_get_mac_eee,
1296 .set_mac_eee = rtl83xx_set_mac_eee,
1297
1298 .set_ageing_time = rtl83xx_set_l2aging,
1299 .port_bridge_join = rtl83xx_port_bridge_join,
1300 .port_bridge_leave = rtl83xx_port_bridge_leave,
1301 .port_stp_state_set = rtl83xx_port_stp_state_set,
1302 .port_fast_age = rtl83xx_fast_age,
1303
1304 .port_vlan_filtering = rtl83xx_vlan_filtering,
1305 .port_vlan_prepare = rtl83xx_vlan_prepare,
1306 .port_vlan_add = rtl83xx_vlan_add,
1307 .port_vlan_del = rtl83xx_vlan_del,
1308
1309 .port_fdb_add = rtl83xx_port_fdb_add,
1310 .port_fdb_del = rtl83xx_port_fdb_del,
1311 .port_fdb_dump = rtl83xx_port_fdb_dump,
1312
1313 .port_mirror_add = rtl83xx_port_mirror_add,
1314 .port_mirror_del = rtl83xx_port_mirror_del,
1315 };
1316
1317 const struct dsa_switch_ops rtl930x_switch_ops = {
1318 .get_tag_protocol = rtl83xx_get_tag_protocol,
1319 .setup = rtl930x_setup,
1320
1321 .phy_read = dsa_phy_read,
1322 .phy_write = dsa_phy_write,
1323
1324 .phylink_validate = rtl83xx_phylink_validate,
1325 .phylink_mac_link_state = rtl83xx_phylink_mac_link_state,
1326 .phylink_mac_config = rtl83xx_phylink_mac_config,
1327 .phylink_mac_link_down = rtl83xx_phylink_mac_link_down,
1328 .phylink_mac_link_up = rtl83xx_phylink_mac_link_up,
1329
1330 .get_strings = rtl83xx_get_strings,
1331 .get_ethtool_stats = rtl83xx_get_ethtool_stats,
1332 .get_sset_count = rtl83xx_get_sset_count,
1333
1334 .port_enable = rtl83xx_port_enable,
1335 .port_disable = rtl83xx_port_disable,
1336
1337 .set_ageing_time = rtl83xx_set_l2aging,
1338 .port_bridge_join = rtl83xx_port_bridge_join,
1339 .port_bridge_leave = rtl83xx_port_bridge_leave,
1340 .port_stp_state_set = rtl83xx_port_stp_state_set,
1341 .port_fast_age = rtl930x_fast_age,
1342
1343 .port_vlan_filtering = rtl83xx_vlan_filtering,
1344 .port_vlan_prepare = rtl83xx_vlan_prepare,
1345 .port_vlan_add = rtl83xx_vlan_add,
1346 .port_vlan_del = rtl83xx_vlan_del,
1347
1348 .port_fdb_add = rtl83xx_port_fdb_add,
1349 .port_fdb_del = rtl83xx_port_fdb_del,
1350 .port_fdb_dump = rtl83xx_port_fdb_dump,
1351 };
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