1 // SPDX-License-Identifier: GPL-2.0-only
3 #include <asm/mach-rtl838x/mach-rtl83xx.h>
6 extern struct mutex smi_lock
;
8 void rtl838x_print_matrix(void)
10 unsigned volatile int *ptr8
;
13 ptr8
= RTL838X_SW_BASE
+ RTL838X_PORT_ISO_CTRL(0);
14 for (i
= 0; i
< 28; i
+= 8)
15 pr_debug("> %8x %8x %8x %8x %8x %8x %8x %8x\n",
16 ptr8
[i
+ 0], ptr8
[i
+ 1], ptr8
[i
+ 2], ptr8
[i
+ 3],
17 ptr8
[i
+ 4], ptr8
[i
+ 5], ptr8
[i
+ 6], ptr8
[i
+ 7]);
18 pr_debug("CPU_PORT> %8x\n", ptr8
[28]);
21 static inline int rtl838x_port_iso_ctrl(int p
)
23 return RTL838X_PORT_ISO_CTRL(p
);
26 static inline void rtl838x_exec_tbl0_cmd(u32 cmd
)
28 sw_w32(cmd
, RTL838X_TBL_ACCESS_CTRL_0
);
29 do { } while (sw_r32(RTL838X_TBL_ACCESS_CTRL_0
) & BIT(15));
32 static inline void rtl838x_exec_tbl1_cmd(u32 cmd
)
34 sw_w32(cmd
, RTL838X_TBL_ACCESS_CTRL_1
);
35 do { } while (sw_r32(RTL838X_TBL_ACCESS_CTRL_1
) & BIT(15));
38 static inline int rtl838x_tbl_access_data_0(int i
)
40 return RTL838X_TBL_ACCESS_DATA_0(i
);
43 static void rtl838x_vlan_tables_read(u32 vlan
, struct rtl838x_vlan_info
*info
)
46 // Read VLAN table (0) via register 0
47 struct table_reg
*r
= rtl_table_get(RTL8380_TBL_0
, 0);
49 rtl_table_read(r
, vlan
);
50 info
->tagged_ports
= sw_r32(rtl_table_data(r
, 0));
51 v
= sw_r32(rtl_table_data(r
, 1));
52 pr_debug("VLAN_READ %d: %016llx %08x\n", vlan
, info
->tagged_ports
, v
);
55 info
->profile_id
= v
& 0x7;
56 info
->hash_mc_fid
= !!(v
& 0x8);
57 info
->hash_uc_fid
= !!(v
& 0x10);
58 info
->fid
= (v
>> 5) & 0x3f;
60 // Read UNTAG table (0) via table register 1
61 r
= rtl_table_get(RTL8380_TBL_1
, 0);
62 rtl_table_read(r
, vlan
);
63 info
->untagged_ports
= sw_r32(rtl_table_data(r
, 0));
67 static void rtl838x_vlan_set_tagged(u32 vlan
, struct rtl838x_vlan_info
*info
)
70 // Access VLAN table (0) via register 0
71 struct table_reg
*r
= rtl_table_get(RTL8380_TBL_0
, 0);
73 sw_w32(info
->tagged_ports
, rtl_table_data(r
, 0));
76 v
|= info
->hash_mc_fid
? 0x8 : 0;
77 v
|= info
->hash_uc_fid
? 0x10 : 0;
78 v
|= ((u32
)info
->fid
) << 5;
79 sw_w32(v
, rtl_table_data(r
, 1));
81 rtl_table_write(r
, vlan
);
85 static void rtl838x_vlan_set_untagged(u32 vlan
, u64 portmask
)
87 // Access UNTAG table (0) via register 1
88 struct table_reg
*r
= rtl_table_get(RTL8380_TBL_1
, 0);
90 sw_w32(portmask
& 0x1fffffff, rtl_table_data(r
, 0));
91 rtl_table_write(r
, vlan
);
95 static inline int rtl838x_mac_force_mode_ctrl(int p
)
97 return RTL838X_MAC_FORCE_MODE_CTRL
+ (p
<< 2);
100 static inline int rtl838x_mac_port_ctrl(int p
)
102 return RTL838X_MAC_PORT_CTRL(p
);
105 static inline int rtl838x_l2_port_new_salrn(int p
)
107 return RTL838X_L2_PORT_NEW_SALRN(p
);
110 static inline int rtl838x_l2_port_new_sa_fwd(int p
)
112 return RTL838X_L2_PORT_NEW_SA_FWD(p
);
115 static inline int rtl838x_mac_link_spd_sts(int p
)
117 return RTL838X_MAC_LINK_SPD_STS(p
);
120 inline static int rtl838x_trk_mbr_ctr(int group
)
122 return RTL838X_TRK_MBR_CTR
+ (group
<< 2);
125 static u64
rtl838x_read_l2_entry_using_hash(u32 hash
, u32 position
, struct rtl838x_l2_entry
*e
)
130 /* Search in SRAM, with hash and at position in hash bucket (0-3) */
131 u32 idx
= (0 << 14) | (hash
<< 2) | position
;
133 u32 cmd
= BIT(16) /* Execute cmd */
135 | 0 << 13 /* Table type 0b00 */
138 sw_w32(cmd
, RTL838X_TBL_ACCESS_L2_CTRL
);
139 do { } while (sw_r32(RTL838X_TBL_ACCESS_L2_CTRL
) & BIT(16));
140 r
[0] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(0));
141 r
[1] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(1));
142 r
[2] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(2));
144 e
->mac
[0] = (r
[1] >> 20);
145 e
->mac
[1] = (r
[1] >> 12);
146 e
->mac
[2] = (r
[1] >> 4);
147 e
->mac
[3] = (r
[1] & 0xf) << 4 | (r
[2] >> 28);
148 e
->mac
[4] = (r
[2] >> 20);
149 e
->mac
[5] = (r
[2] >> 12);
150 e
->is_static
= !!((r
[0] >> 19) & 1);
151 e
->vid
= r
[0] & 0xfff;
152 e
->rvid
= r
[2] & 0xfff;
153 e
->port
= (r
[0] >> 12) & 0x1f;
156 if (!(r
[0] >> 17)) /* Check for invalid entry */
160 pr_debug("Found in Hash: R1 %x R2 %x R3 %x\n", r
[0], r
[1], r
[2]);
162 entry
= (((u64
) r
[1]) << 32) | (r
[2] & 0xfffff000) | (r
[0] & 0xfff);
166 static u64
rtl838x_read_cam(int idx
, struct rtl838x_l2_entry
*e
)
171 u32 cmd
= BIT(16) /* Execute cmd */
173 | BIT(13) /* Table type 0b01 */
175 sw_w32(cmd
, RTL838X_TBL_ACCESS_L2_CTRL
);
176 do { } while (sw_r32(RTL838X_TBL_ACCESS_L2_CTRL
) & BIT(16));
177 r
[0] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(0));
178 r
[1] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(1));
179 r
[2] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(2));
181 e
->mac
[0] = (r
[1] >> 20);
182 e
->mac
[1] = (r
[1] >> 12);
183 e
->mac
[2] = (r
[1] >> 4);
184 e
->mac
[3] = (r
[1] & 0xf) << 4 | (r
[2] >> 28);
185 e
->mac
[4] = (r
[2] >> 20);
186 e
->mac
[5] = (r
[2] >> 12);
187 e
->is_static
= !!((r
[0] >> 19) & 1);
188 e
->vid
= r
[0] & 0xfff;
189 e
->rvid
= r
[2] & 0xfff;
190 e
->port
= (r
[0] >> 12) & 0x1f;
193 if (!(r
[0] >> 17)) /* Check for invalid entry */
197 pr_debug("Found in CAM: R1 %x R2 %x R3 %x\n", r
[0], r
[1], r
[2]);
199 entry
= (((u64
) r
[1]) << 32) | (r
[2] & 0xfffff000) | (r
[0] & 0xfff);
203 static u64
rtl838x_read_mcast_pmask(int idx
)
206 // Read MC_PMSK (2) via register RTL8380_TBL_L2
207 struct table_reg
*q
= rtl_table_get(RTL8380_TBL_L2
, 2);
209 rtl_table_read(q
, idx
);
210 portmask
= sw_r32(rtl_table_data(q
, 0));
211 rtl_table_release(q
);
216 static void rtl838x_write_mcast_pmask(int idx
, u64 portmask
)
218 // Access MC_PMSK (2) via register RTL8380_TBL_L2
219 struct table_reg
*q
= rtl_table_get(RTL8380_TBL_L2
, 2);
221 sw_w32(((u32
)portmask
) & 0x1fffffff, rtl_table_data(q
, 0));
222 rtl_table_write(q
, idx
);
223 rtl_table_release(q
);
226 static void rtl838x_vlan_profile_setup(int profile
)
228 u32 pmask_id
= UNKNOWN_MC_PMASK
;
229 // Enable L2 Learning BIT 0, portmask UNKNOWN_MC_PMASK for unknown MC traffic flooding
230 u32 p
= 1 | pmask_id
<< 1 | pmask_id
<< 10 | pmask_id
<< 19;
232 sw_w32(p
, RTL838X_VLAN_PROFILE(profile
));
234 /* RTL8380 and RTL8390 use an index into the portmask table to set the
235 * unknown multicast portmask, setup a default at a safe location
236 * On RTL93XX, the portmask is directly set in the profile,
237 * see e.g. rtl9300_vlan_profile_setup
239 rtl838x_write_mcast_pmask(UNKNOWN_MC_PMASK
, 0xfffffff);
242 static inline int rtl838x_vlan_port_egr_filter(int port
)
244 return RTL838X_VLAN_PORT_EGR_FLTR
;
247 static inline int rtl838x_vlan_port_igr_filter(int port
)
249 return RTL838X_VLAN_PORT_IGR_FLTR(port
);
252 static void rtl838x_stp_get(struct rtl838x_switch_priv
*priv
, u16 msti
, u32 port_state
[])
255 u32 cmd
= 1 << 15 /* Execute cmd */
257 | 2 << 12 /* Table type 0b10 */
259 priv
->r
->exec_tbl0_cmd(cmd
);
261 for (i
= 0; i
< 2; i
++)
262 port_state
[i
] = sw_r32(priv
->r
->tbl_access_data_0(i
));
265 static void rtl838x_stp_set(struct rtl838x_switch_priv
*priv
, u16 msti
, u32 port_state
[])
268 u32 cmd
= 1 << 15 /* Execute cmd */
269 | 0 << 14 /* Write */
270 | 2 << 12 /* Table type 0b10 */
273 for (i
= 0; i
< 2; i
++)
274 sw_w32(port_state
[i
], priv
->r
->tbl_access_data_0(i
));
275 priv
->r
->exec_tbl0_cmd(cmd
);
278 u64
rtl838x_traffic_get(int source
)
280 return rtl838x_get_port_reg(rtl838x_port_iso_ctrl(source
));
283 void rtl838x_traffic_set(int source
, u64 dest_matrix
)
285 rtl838x_set_port_reg(dest_matrix
, rtl838x_port_iso_ctrl(source
));
288 void rtl838x_traffic_enable(int source
, int dest
)
290 rtl838x_mask_port_reg(0, BIT(dest
), rtl838x_port_iso_ctrl(source
));
293 void rtl838x_traffic_disable(int source
, int dest
)
295 rtl838x_mask_port_reg(BIT(dest
), 0, rtl838x_port_iso_ctrl(source
));
299 * Enables or disables the EEE/EEEP capability of a port
301 static void rtl838x_port_eee_set(struct rtl838x_switch_priv
*priv
, int port
, bool enable
)
305 // This works only for Ethernet ports, and on the RTL838X, ports from 24 are SFP
309 pr_debug("In %s: setting port %d to %d\n", __func__
, port
, enable
);
310 v
= enable
? 0x3 : 0x0;
312 // Set EEE state for 100 (bit 9) & 1000MBit (bit 10)
313 sw_w32_mask(0x3 << 9, v
<< 9, priv
->r
->mac_force_mode_ctrl(port
));
315 // Set TX/RX EEE state
317 sw_w32_mask(0, BIT(port
), RTL838X_EEE_PORT_TX_EN
);
318 sw_w32_mask(0, BIT(port
), RTL838X_EEE_PORT_RX_EN
);
320 sw_w32_mask(BIT(port
), 0, RTL838X_EEE_PORT_TX_EN
);
321 sw_w32_mask(BIT(port
), 0, RTL838X_EEE_PORT_RX_EN
);
323 priv
->ports
[port
].eee_enabled
= enable
;
328 * Get EEE own capabilities and negotiation result
330 static int rtl838x_eee_port_ability(struct rtl838x_switch_priv
*priv
,
331 struct ethtool_eee
*e
, int port
)
338 link
= rtl839x_get_port_reg_le(RTL838X_MAC_LINK_STS
);
339 if (!(link
& BIT(port
)))
342 if (sw_r32(rtl838x_mac_force_mode_ctrl(port
)) & BIT(9))
343 e
->advertised
|= ADVERTISED_100baseT_Full
;
345 if (sw_r32(rtl838x_mac_force_mode_ctrl(port
)) & BIT(10))
346 e
->advertised
|= ADVERTISED_1000baseT_Full
;
348 if (sw_r32(RTL838X_MAC_EEE_ABLTY
) & BIT(port
)) {
349 e
->lp_advertised
= ADVERTISED_100baseT_Full
;
350 e
->lp_advertised
|= ADVERTISED_1000baseT_Full
;
357 static void rtl838x_init_eee(struct rtl838x_switch_priv
*priv
, bool enable
)
361 pr_info("Setting up EEE, state: %d\n", enable
);
362 sw_w32_mask(0x4, 0, RTL838X_SMI_GLB_CTRL
);
364 /* Set timers for EEE */
365 sw_w32(0x5001411, RTL838X_EEE_TX_TIMER_GIGA_CTRL
);
366 sw_w32(0x5001417, RTL838X_EEE_TX_TIMER_GELITE_CTRL
);
368 // Enable EEE MAC support on ports
369 for (i
= 0; i
< priv
->cpu_port
; i
++) {
370 if (priv
->ports
[i
].phy
)
371 rtl838x_port_eee_set(priv
, i
, enable
);
373 priv
->eee_enabled
= enable
;
376 const struct rtl838x_reg rtl838x_reg
= {
377 .mask_port_reg_be
= rtl838x_mask_port_reg
,
378 .set_port_reg_be
= rtl838x_set_port_reg
,
379 .get_port_reg_be
= rtl838x_get_port_reg
,
380 .mask_port_reg_le
= rtl838x_mask_port_reg
,
381 .set_port_reg_le
= rtl838x_set_port_reg
,
382 .get_port_reg_le
= rtl838x_get_port_reg
,
383 .stat_port_rst
= RTL838X_STAT_PORT_RST
,
384 .stat_rst
= RTL838X_STAT_RST
,
385 .stat_port_std_mib
= RTL838X_STAT_PORT_STD_MIB
,
386 .port_iso_ctrl
= rtl838x_port_iso_ctrl
,
387 .traffic_enable
= rtl838x_traffic_enable
,
388 .traffic_disable
= rtl838x_traffic_disable
,
389 .traffic_get
= rtl838x_traffic_get
,
390 .traffic_set
= rtl838x_traffic_set
,
391 .l2_ctrl_0
= RTL838X_L2_CTRL_0
,
392 .l2_ctrl_1
= RTL838X_L2_CTRL_1
,
393 .l2_port_aging_out
= RTL838X_L2_PORT_AGING_OUT
,
394 .smi_poll_ctrl
= RTL838X_SMI_POLL_CTRL
,
395 .l2_tbl_flush_ctrl
= RTL838X_L2_TBL_FLUSH_CTRL
,
396 .exec_tbl0_cmd
= rtl838x_exec_tbl0_cmd
,
397 .exec_tbl1_cmd
= rtl838x_exec_tbl1_cmd
,
398 .tbl_access_data_0
= rtl838x_tbl_access_data_0
,
399 .isr_glb_src
= RTL838X_ISR_GLB_SRC
,
400 .isr_port_link_sts_chg
= RTL838X_ISR_PORT_LINK_STS_CHG
,
401 .imr_port_link_sts_chg
= RTL838X_IMR_PORT_LINK_STS_CHG
,
402 .imr_glb
= RTL838X_IMR_GLB
,
403 .vlan_tables_read
= rtl838x_vlan_tables_read
,
404 .vlan_set_tagged
= rtl838x_vlan_set_tagged
,
405 .vlan_set_untagged
= rtl838x_vlan_set_untagged
,
406 .mac_force_mode_ctrl
= rtl838x_mac_force_mode_ctrl
,
407 .vlan_profile_dump
= rtl838x_vlan_profile_dump
,
408 .vlan_profile_setup
= rtl838x_vlan_profile_setup
,
409 .stp_get
= rtl838x_stp_get
,
410 .stp_set
= rtl838x_stp_set
,
411 .mac_port_ctrl
= rtl838x_mac_port_ctrl
,
412 .l2_port_new_salrn
= rtl838x_l2_port_new_salrn
,
413 .l2_port_new_sa_fwd
= rtl838x_l2_port_new_sa_fwd
,
414 .mir_ctrl
= RTL838X_MIR_CTRL
,
415 .mir_dpm
= RTL838X_MIR_DPM_CTRL
,
416 .mir_spm
= RTL838X_MIR_SPM_CTRL
,
417 .mac_link_sts
= RTL838X_MAC_LINK_STS
,
418 .mac_link_dup_sts
= RTL838X_MAC_LINK_DUP_STS
,
419 .mac_link_spd_sts
= rtl838x_mac_link_spd_sts
,
420 .mac_rx_pause_sts
= RTL838X_MAC_RX_PAUSE_STS
,
421 .mac_tx_pause_sts
= RTL838X_MAC_TX_PAUSE_STS
,
422 .read_l2_entry_using_hash
= rtl838x_read_l2_entry_using_hash
,
423 .read_cam
= rtl838x_read_cam
,
424 .vlan_port_egr_filter
= RTL838X_VLAN_PORT_EGR_FLTR
,
425 .vlan_port_igr_filter
= RTL838X_VLAN_PORT_IGR_FLTR(0),
426 .vlan_port_pb
= RTL838X_VLAN_PORT_PB_VLAN
,
427 .vlan_port_tag_sts_ctrl
= RTL838X_VLAN_PORT_TAG_STS_CTRL
,
428 .trk_mbr_ctr
= rtl838x_trk_mbr_ctr
,
429 .rma_bpdu_fld_pmask
= RTL838X_RMA_BPDU_FLD_PMSK
,
430 .spcl_trap_eapol_ctrl
= RTL838X_SPCL_TRAP_EAPOL_CTRL
,
431 .init_eee
= rtl838x_init_eee
,
432 .port_eee_set
= rtl838x_port_eee_set
,
433 .eee_port_ability
= rtl838x_eee_port_ability
,
434 .read_mcast_pmask
= rtl838x_read_mcast_pmask
,
435 .write_mcast_pmask
= rtl838x_write_mcast_pmask
,
438 irqreturn_t
rtl838x_switch_irq(int irq
, void *dev_id
)
440 struct dsa_switch
*ds
= dev_id
;
441 u32 status
= sw_r32(RTL838X_ISR_GLB_SRC
);
442 u32 ports
= sw_r32(RTL838X_ISR_PORT_LINK_STS_CHG
);
447 sw_w32(ports
, RTL838X_ISR_PORT_LINK_STS_CHG
);
448 pr_info("RTL8380 Link change: status: %x, ports %x\n", status
, ports
);
450 for (i
= 0; i
< 28; i
++) {
451 if (ports
& BIT(i
)) {
452 link
= sw_r32(RTL838X_MAC_LINK_STS
);
454 dsa_port_phylink_mac_change(ds
, i
, true);
456 dsa_port_phylink_mac_change(ds
, i
, false);
462 int rtl838x_smi_wait_op(int timeout
)
467 } while ((sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_1
) & 0x1) && (timeout
>= 0));
474 * Reads a register in a page from the PHY
476 int rtl838x_read_phy(u32 port
, u32 page
, u32 reg
, u32
*val
)
486 if (page
> 4095 || reg
> 31)
489 mutex_lock(&smi_lock
);
491 if (rtl838x_smi_wait_op(10000))
494 sw_w32_mask(0xffff0000, port
<< 16, RTL838X_SMI_ACCESS_PHY_CTRL_2
);
496 park_page
= sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_1
) & ((0x1f << 15) | 0x2);
497 v
= reg
<< 20 | page
<< 3;
498 sw_w32(v
| park_page
, RTL838X_SMI_ACCESS_PHY_CTRL_1
);
499 sw_w32_mask(0, 1, RTL838X_SMI_ACCESS_PHY_CTRL_1
);
501 if (rtl838x_smi_wait_op(10000))
504 *val
= sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_2
) & 0xffff;
506 mutex_unlock(&smi_lock
);
510 mutex_unlock(&smi_lock
);
515 * Write to a register in a page of the PHY
517 int rtl838x_write_phy(u32 port
, u32 page
, u32 reg
, u32 val
)
523 if (port
> 31 || page
> 4095 || reg
> 31)
526 mutex_lock(&smi_lock
);
527 if (rtl838x_smi_wait_op(10000))
530 sw_w32(BIT(port
), RTL838X_SMI_ACCESS_PHY_CTRL_0
);
533 sw_w32_mask(0xffff0000, val
<< 16, RTL838X_SMI_ACCESS_PHY_CTRL_2
);
535 park_page
= sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_1
) & ((0x1f << 15) | 0x2);
536 v
= reg
<< 20 | page
<< 3 | 0x4;
537 sw_w32(v
| park_page
, RTL838X_SMI_ACCESS_PHY_CTRL_1
);
538 sw_w32_mask(0, 1, RTL838X_SMI_ACCESS_PHY_CTRL_1
);
540 if (rtl838x_smi_wait_op(10000))
543 mutex_unlock(&smi_lock
);
547 mutex_unlock(&smi_lock
);
552 * Read an mmd register of a PHY
554 int rtl838x_read_mmd_phy(u32 port
, u32 addr
, u32 reg
, u32
*val
)
558 mutex_lock(&smi_lock
);
560 if (rtl838x_smi_wait_op(10000))
563 sw_w32(1 << port
, RTL838X_SMI_ACCESS_PHY_CTRL_0
);
566 sw_w32_mask(0xffff0000, port
<< 16, RTL838X_SMI_ACCESS_PHY_CTRL_2
);
568 v
= addr
<< 16 | reg
;
569 sw_w32(v
, RTL838X_SMI_ACCESS_PHY_CTRL_3
);
571 /* mmd-access | read | cmd-start */
572 v
= 1 << 1 | 0 << 2 | 1;
573 sw_w32(v
, RTL838X_SMI_ACCESS_PHY_CTRL_1
);
575 if (rtl838x_smi_wait_op(10000))
578 *val
= sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_2
) & 0xffff;
580 mutex_unlock(&smi_lock
);
584 mutex_unlock(&smi_lock
);
589 * Write to an mmd register of a PHY
591 int rtl838x_write_mmd_phy(u32 port
, u32 addr
, u32 reg
, u32 val
)
595 pr_debug("MMD write: port %d, dev %d, reg %d, val %x\n", port
, addr
, reg
, val
);
597 mutex_lock(&smi_lock
);
599 if (rtl838x_smi_wait_op(10000))
602 sw_w32(1 << port
, RTL838X_SMI_ACCESS_PHY_CTRL_0
);
605 sw_w32_mask(0xffff0000, val
<< 16, RTL838X_SMI_ACCESS_PHY_CTRL_2
);
607 sw_w32_mask(0x1f << 16, addr
<< 16, RTL838X_SMI_ACCESS_PHY_CTRL_3
);
608 sw_w32_mask(0xffff, reg
, RTL838X_SMI_ACCESS_PHY_CTRL_3
);
609 /* mmd-access | write | cmd-start */
610 v
= 1 << 1 | 1 << 2 | 1;
611 sw_w32(v
, RTL838X_SMI_ACCESS_PHY_CTRL_1
);
613 if (rtl838x_smi_wait_op(10000))
616 mutex_unlock(&smi_lock
);
620 mutex_unlock(&smi_lock
);
624 void rtl8380_get_version(struct rtl838x_switch_priv
*priv
)
626 u32 rw_save
, info_save
;
629 rw_save
= sw_r32(RTL838X_INT_RW_CTRL
);
630 sw_w32(rw_save
| 0x3, RTL838X_INT_RW_CTRL
);
632 info_save
= sw_r32(RTL838X_CHIP_INFO
);
633 sw_w32(info_save
| 0xA0000000, RTL838X_CHIP_INFO
);
635 info
= sw_r32(RTL838X_CHIP_INFO
);
636 sw_w32(info_save
, RTL838X_CHIP_INFO
);
637 sw_w32(rw_save
, RTL838X_INT_RW_CTRL
);
639 if ((info
& 0xFFFF) == 0x6275) {
640 if (((info
>> 16) & 0x1F) == 0x1)
641 priv
->version
= RTL8380_VERSION_A
;
642 else if (((info
>> 16) & 0x1F) == 0x2)
643 priv
->version
= RTL8380_VERSION_B
;
645 priv
->version
= RTL8380_VERSION_B
;
652 * Applies the same hash algorithm as the one used currently by the ASIC
654 u32
rtl838x_hash(struct rtl838x_switch_priv
*priv
, u64 seed
)
658 if (sw_r32(priv
->r
->l2_ctrl_0
) & 1) {
659 h1
= (seed
>> 11) & 0x7ff;
660 h1
= ((h1
& 0x1f) << 6) | ((h1
>> 5) & 0x3f);
662 h2
= (seed
>> 33) & 0x7ff;
663 h2
= ((h2
& 0x3f) << 5) | ((h2
>> 6) & 0x1f);
665 h3
= (seed
>> 44) & 0x7ff;
666 h3
= ((h3
& 0x7f) << 4) | ((h3
>> 7) & 0xf);
668 h
= h1
^ h2
^ h3
^ ((seed
>> 55) & 0x1ff);
669 h
^= ((seed
>> 22) & 0x7ff) ^ (seed
& 0x7ff);
671 h
= ((seed
>> 55) & 0x1ff) ^ ((seed
>> 44) & 0x7ff)
672 ^ ((seed
>> 33) & 0x7ff) ^ ((seed
>> 22) & 0x7ff)
673 ^ ((seed
>> 11) & 0x7ff) ^ (seed
& 0x7ff);
679 void rtl838x_vlan_profile_dump(int profile
)
683 if (profile
< 0 || profile
> 7)
686 p
= sw_r32(RTL838X_VLAN_PROFILE(profile
));
688 pr_info("VLAN profile %d: L2 learning: %d, UNKN L2MC FLD PMSK %d, \
689 UNKN IPMC FLD PMSK %d, UNKN IPv6MC FLD PMSK: %d",
690 profile
, p
& 1, (p
>> 1) & 0x1ff, (p
>> 10) & 0x1ff, (p
>> 19) & 0x1ff);
693 void rtl8380_sds_rst(int mac
)
695 u32 offset
= (mac
== 24) ? 0 : 0x100;
697 sw_w32_mask(1 << 11, 0, RTL838X_SDS4_FIB_REG0
+ offset
);
698 sw_w32_mask(0x3, 0, RTL838X_SDS4_REG28
+ offset
);
699 sw_w32_mask(0x3, 0x3, RTL838X_SDS4_REG28
+ offset
);
700 sw_w32_mask(0, 0x1 << 6, RTL838X_SDS4_DUMMY0
+ offset
);
701 sw_w32_mask(0x1 << 6, 0, RTL838X_SDS4_DUMMY0
+ offset
);
702 pr_debug("SERDES reset: %d\n", mac
);
705 int rtl8380_sds_power(int mac
, int val
)
707 u32 mode
= (val
== 1) ? 0x4 : 0x9;
708 u32 offset
= (mac
== 24) ? 5 : 0;
710 if ((mac
!= 24) && (mac
!= 26)) {
711 pr_err("%s: not a fibre port: %d\n", __func__
, mac
);
715 sw_w32_mask(0x1f << offset
, mode
<< offset
, RTL838X_SDS_MODE_SEL
);
717 rtl8380_sds_rst(mac
);