1 // SPDX-License-Identifier: GPL-2.0-only
3 #include <asm/mach-rtl838x/mach-rtl83xx.h>
6 extern struct mutex smi_lock
;
8 void rtl838x_print_matrix(void)
10 unsigned volatile int *ptr8
;
13 ptr8
= RTL838X_SW_BASE
+ RTL838X_PORT_ISO_CTRL(0);
14 for (i
= 0; i
< 28; i
+= 8)
15 pr_info("> %8x %8x %8x %8x %8x %8x %8x %8x\n",
16 ptr8
[i
+ 0], ptr8
[i
+ 1], ptr8
[i
+ 2], ptr8
[i
+ 3],
17 ptr8
[i
+ 4], ptr8
[i
+ 5], ptr8
[i
+ 6], ptr8
[i
+ 7]);
18 pr_info("CPU_PORT> %8x\n", ptr8
[28]);
21 static inline int rtl838x_port_iso_ctrl(int p
)
23 return RTL838X_PORT_ISO_CTRL(p
);
26 static inline void rtl838x_exec_tbl0_cmd(u32 cmd
)
28 sw_w32(cmd
, RTL838X_TBL_ACCESS_CTRL_0
);
29 do { } while (sw_r32(RTL838X_TBL_ACCESS_CTRL_0
) & BIT(15));
32 static inline void rtl838x_exec_tbl1_cmd(u32 cmd
)
34 sw_w32(cmd
, RTL838X_TBL_ACCESS_CTRL_1
);
35 do { } while (sw_r32(RTL838X_TBL_ACCESS_CTRL_1
) & BIT(15));
38 static inline int rtl838x_tbl_access_data_0(int i
)
40 return RTL838X_TBL_ACCESS_DATA_0(i
);
43 static void rtl838x_vlan_tables_read(u32 vlan
, struct rtl838x_vlan_info
*info
)
47 cmd
= BIT(15) /* Execute cmd */
49 | 0 << 12 /* Table type 0b00 */
51 rtl838x_exec_tbl0_cmd(cmd
);
52 info
->tagged_ports
= sw_r32(RTL838X_TBL_ACCESS_DATA_0(0));
53 v
= sw_r32(RTL838X_TBL_ACCESS_DATA_0(1));
54 info
->profile_id
= v
& 0x7;
55 info
->hash_mc_fid
= !!(v
& 0x8);
56 info
->hash_uc_fid
= !!(v
& 0x10);
57 info
->fid
= (v
>> 5) & 0x3f;
60 cmd
= BIT(15) /* Execute cmd */
62 | 0 << 12 /* Table type 0b00 */
64 rtl838x_exec_tbl1_cmd(cmd
);
65 info
->untagged_ports
= sw_r32(RTL838X_TBL_ACCESS_DATA_1(0));
68 static void rtl838x_vlan_set_tagged(u32 vlan
, struct rtl838x_vlan_info
*info
)
70 u32 cmd
= BIT(15) /* Execute cmd */
72 | 0 << 12 /* Table type 0b00 */
76 sw_w32(info
->tagged_ports
, RTL838X_TBL_ACCESS_DATA_0(0));
79 v
|= info
->hash_mc_fid
? 0x8 : 0;
80 v
|= info
->hash_uc_fid
? 0x10 : 0;
81 v
|= ((u32
)info
->fid
) << 5;
83 sw_w32(v
, RTL838X_TBL_ACCESS_DATA_0(1));
84 rtl838x_exec_tbl0_cmd(cmd
);
87 static void rtl838x_vlan_set_untagged(u32 vlan
, u64 portmask
)
89 u32 cmd
= BIT(15) /* Execute cmd */
91 | 0 << 12 /* Table type 0b00 */
93 sw_w32(portmask
& 0x1fffffff, RTL838X_TBL_ACCESS_DATA_1(0));
94 rtl838x_exec_tbl1_cmd(cmd
);
97 static inline int rtl838x_mac_force_mode_ctrl(int p
)
99 return RTL838X_MAC_FORCE_MODE_CTRL
+ (p
<< 2);
102 static inline int rtl838x_mac_port_ctrl(int p
)
104 return RTL838X_MAC_PORT_CTRL(p
);
107 static inline int rtl838x_l2_port_new_salrn(int p
)
109 return RTL838X_L2_PORT_NEW_SALRN(p
);
112 static inline int rtl838x_l2_port_new_sa_fwd(int p
)
114 return RTL838X_L2_PORT_NEW_SA_FWD(p
);
117 static inline int rtl838x_mac_link_spd_sts(int p
)
119 return RTL838X_MAC_LINK_SPD_STS(p
);
122 inline static int rtl838x_trk_mbr_ctr(int group
)
124 return RTL838X_TRK_MBR_CTR
+ (group
<< 2);
127 static u64
rtl838x_read_l2_entry_using_hash(u32 hash
, u32 position
, struct rtl838x_l2_entry
*e
)
132 /* Search in SRAM, with hash and at position in hash bucket (0-3) */
133 u32 idx
= (0 << 14) | (hash
<< 2) | position
;
135 u32 cmd
= BIT(16) /* Execute cmd */
137 | 0 << 13 /* Table type 0b00 */
140 sw_w32(cmd
, RTL838X_TBL_ACCESS_L2_CTRL
);
141 do { } while (sw_r32(RTL838X_TBL_ACCESS_L2_CTRL
) & BIT(16));
142 r
[0] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(0));
143 r
[1] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(1));
144 r
[2] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(2));
146 e
->mac
[0] = (r
[1] >> 20);
147 e
->mac
[1] = (r
[1] >> 12);
148 e
->mac
[2] = (r
[1] >> 4);
149 e
->mac
[3] = (r
[1] & 0xf) << 4 | (r
[2] >> 28);
150 e
->mac
[4] = (r
[2] >> 20);
151 e
->mac
[5] = (r
[2] >> 12);
152 e
->is_static
= !!((r
[0] >> 19) & 1);
153 e
->vid
= r
[0] & 0xfff;
154 e
->rvid
= r
[2] & 0xfff;
155 e
->port
= (r
[0] >> 12) & 0x1f;
158 if (!(r
[0] >> 17)) /* Check for invalid entry */
162 pr_debug("Found in Hash: R1 %x R2 %x R3 %x\n", r
[0], r
[1], r
[2]);
164 entry
= (((u64
) r
[1]) << 32) | (r
[2] & 0xfffff000) | (r
[0] & 0xfff);
168 static u64
rtl838x_read_cam(int idx
, struct rtl838x_l2_entry
*e
)
173 u32 cmd
= BIT(16) /* Execute cmd */
175 | BIT(13) /* Table type 0b01 */
177 sw_w32(cmd
, RTL838X_TBL_ACCESS_L2_CTRL
);
178 do { } while (sw_r32(RTL838X_TBL_ACCESS_L2_CTRL
) & BIT(16));
179 r
[0] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(0));
180 r
[1] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(1));
181 r
[2] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(2));
183 e
->mac
[0] = (r
[1] >> 20);
184 e
->mac
[1] = (r
[1] >> 12);
185 e
->mac
[2] = (r
[1] >> 4);
186 e
->mac
[3] = (r
[1] & 0xf) << 4 | (r
[2] >> 28);
187 e
->mac
[4] = (r
[2] >> 20);
188 e
->mac
[5] = (r
[2] >> 12);
189 e
->is_static
= !!((r
[0] >> 19) & 1);
190 e
->vid
= r
[0] & 0xfff;
191 e
->rvid
= r
[2] & 0xfff;
192 e
->port
= (r
[0] >> 12) & 0x1f;
195 if (!(r
[0] >> 17)) /* Check for invalid entry */
199 pr_debug("Found in CAM: R1 %x R2 %x R3 %x\n", r
[0], r
[1], r
[2]);
201 entry
= (((u64
) r
[1]) << 32) | (r
[2] & 0xfffff000) | (r
[0] & 0xfff);
205 static inline int rtl838x_vlan_profile(int profile
)
207 return RTL838X_VLAN_PROFILE(profile
);
210 static inline int rtl838x_vlan_port_egr_filter(int port
)
212 return RTL838X_VLAN_PORT_EGR_FLTR
;
215 static inline int rtl838x_vlan_port_igr_filter(int port
)
217 return RTL838X_VLAN_PORT_IGR_FLTR(port
);
220 static void rtl838x_stp_get(struct rtl838x_switch_priv
*priv
, u16 msti
, u32 port_state
[])
223 u32 cmd
= 1 << 15 /* Execute cmd */
225 | 2 << 12 /* Table type 0b10 */
227 priv
->r
->exec_tbl0_cmd(cmd
);
229 for (i
= 0; i
< 2; i
++)
230 port_state
[i
] = sw_r32(priv
->r
->tbl_access_data_0(i
));
233 static void rtl838x_stp_set(struct rtl838x_switch_priv
*priv
, u16 msti
, u32 port_state
[])
236 u32 cmd
= 1 << 15 /* Execute cmd */
237 | 0 << 14 /* Write */
238 | 2 << 12 /* Table type 0b10 */
241 for (i
= 0; i
< 2; i
++)
242 sw_w32(port_state
[i
], priv
->r
->tbl_access_data_0(i
));
243 priv
->r
->exec_tbl0_cmd(cmd
);
246 u64
rtl838x_traffic_get(int source
)
248 return rtl838x_get_port_reg(rtl838x_port_iso_ctrl(source
));
251 void rtl838x_traffic_set(int source
, u64 dest_matrix
)
253 rtl838x_set_port_reg(dest_matrix
, rtl838x_port_iso_ctrl(source
));
256 void rtl838x_traffic_enable(int source
, int dest
)
258 rtl838x_mask_port_reg(0, BIT(dest
), rtl838x_port_iso_ctrl(source
));
261 void rtl838x_traffic_disable(int source
, int dest
)
263 rtl838x_mask_port_reg(BIT(dest
), 0, rtl838x_port_iso_ctrl(source
));
266 const struct rtl838x_reg rtl838x_reg
= {
267 .mask_port_reg_be
= rtl838x_mask_port_reg
,
268 .set_port_reg_be
= rtl838x_set_port_reg
,
269 .get_port_reg_be
= rtl838x_get_port_reg
,
270 .mask_port_reg_le
= rtl838x_mask_port_reg
,
271 .set_port_reg_le
= rtl838x_set_port_reg
,
272 .get_port_reg_le
= rtl838x_get_port_reg
,
273 .stat_port_rst
= RTL838X_STAT_PORT_RST
,
274 .stat_rst
= RTL838X_STAT_RST
,
275 .stat_port_std_mib
= RTL838X_STAT_PORT_STD_MIB
,
276 .port_iso_ctrl
= rtl838x_port_iso_ctrl
,
277 .traffic_enable
= rtl838x_traffic_enable
,
278 .traffic_disable
= rtl838x_traffic_disable
,
279 .traffic_get
= rtl838x_traffic_get
,
280 .traffic_set
= rtl838x_traffic_set
,
281 .l2_ctrl_0
= RTL838X_L2_CTRL_0
,
282 .l2_ctrl_1
= RTL838X_L2_CTRL_1
,
283 .l2_port_aging_out
= RTL838X_L2_PORT_AGING_OUT
,
284 .smi_poll_ctrl
= RTL838X_SMI_POLL_CTRL
,
285 .l2_tbl_flush_ctrl
= RTL838X_L2_TBL_FLUSH_CTRL
,
286 .exec_tbl0_cmd
= rtl838x_exec_tbl0_cmd
,
287 .exec_tbl1_cmd
= rtl838x_exec_tbl1_cmd
,
288 .tbl_access_data_0
= rtl838x_tbl_access_data_0
,
289 .isr_glb_src
= RTL838X_ISR_GLB_SRC
,
290 .isr_port_link_sts_chg
= RTL838X_ISR_PORT_LINK_STS_CHG
,
291 .imr_port_link_sts_chg
= RTL838X_IMR_PORT_LINK_STS_CHG
,
292 .imr_glb
= RTL838X_IMR_GLB
,
293 .vlan_tables_read
= rtl838x_vlan_tables_read
,
294 .vlan_set_tagged
= rtl838x_vlan_set_tagged
,
295 .vlan_set_untagged
= rtl838x_vlan_set_untagged
,
296 .mac_force_mode_ctrl
= rtl838x_mac_force_mode_ctrl
,
297 .vlan_profile_dump
= rtl838x_vlan_profile_dump
,
298 .stp_get
= rtl838x_stp_get
,
299 .stp_set
= rtl838x_stp_set
,
300 .mac_port_ctrl
= rtl838x_mac_port_ctrl
,
301 .l2_port_new_salrn
= rtl838x_l2_port_new_salrn
,
302 .l2_port_new_sa_fwd
= rtl838x_l2_port_new_sa_fwd
,
303 .mir_ctrl
= RTL838X_MIR_CTRL
,
304 .mir_dpm
= RTL838X_MIR_DPM_CTRL
,
305 .mir_spm
= RTL838X_MIR_SPM_CTRL
,
306 .mac_link_sts
= RTL838X_MAC_LINK_STS
,
307 .mac_link_dup_sts
= RTL838X_MAC_LINK_DUP_STS
,
308 .mac_link_spd_sts
= rtl838x_mac_link_spd_sts
,
309 .mac_rx_pause_sts
= RTL838X_MAC_RX_PAUSE_STS
,
310 .mac_tx_pause_sts
= RTL838X_MAC_TX_PAUSE_STS
,
311 .read_l2_entry_using_hash
= rtl838x_read_l2_entry_using_hash
,
312 .read_cam
= rtl838x_read_cam
,
313 .vlan_port_egr_filter
= RTL838X_VLAN_PORT_EGR_FLTR
,
314 .vlan_port_igr_filter
= RTL838X_VLAN_PORT_IGR_FLTR(0),
315 .vlan_port_pb
= RTL838X_VLAN_PORT_PB_VLAN
,
316 .vlan_port_tag_sts_ctrl
= RTL838X_VLAN_PORT_TAG_STS_CTRL
,
317 .trk_mbr_ctr
= rtl838x_trk_mbr_ctr
,
318 .rma_bpdu_fld_pmask
= RTL838X_RMA_BPDU_FLD_PMSK
,
319 .spcl_trap_eapol_ctrl
= RTL838X_SPCL_TRAP_EAPOL_CTRL
,
322 irqreturn_t
rtl838x_switch_irq(int irq
, void *dev_id
)
324 struct dsa_switch
*ds
= dev_id
;
325 u32 status
= sw_r32(RTL838X_ISR_GLB_SRC
);
326 u32 ports
= sw_r32(RTL838X_ISR_PORT_LINK_STS_CHG
);
331 sw_w32(ports
, RTL838X_ISR_PORT_LINK_STS_CHG
);
332 pr_info("RTL8380 Link change: status: %x, ports %x\n", status
, ports
);
334 for (i
= 0; i
< 28; i
++) {
335 if (ports
& BIT(i
)) {
336 link
= sw_r32(RTL838X_MAC_LINK_STS
);
338 dsa_port_phylink_mac_change(ds
, i
, true);
340 dsa_port_phylink_mac_change(ds
, i
, false);
346 int rtl838x_smi_wait_op(int timeout
)
351 } while ((sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_1
) & 0x1) && (timeout
>= 0));
358 * Reads a register in a page from the PHY
360 int rtl838x_read_phy(u32 port
, u32 page
, u32 reg
, u32
*val
)
370 if (page
> 4095 || reg
> 31)
373 mutex_lock(&smi_lock
);
375 if (rtl838x_smi_wait_op(10000))
378 sw_w32_mask(0xffff0000, port
<< 16, RTL838X_SMI_ACCESS_PHY_CTRL_2
);
380 park_page
= sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_1
) & ((0x1f << 15) | 0x2);
381 v
= reg
<< 20 | page
<< 3;
382 sw_w32(v
| park_page
, RTL838X_SMI_ACCESS_PHY_CTRL_1
);
383 sw_w32_mask(0, 1, RTL838X_SMI_ACCESS_PHY_CTRL_1
);
385 if (rtl838x_smi_wait_op(10000))
388 *val
= sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_2
) & 0xffff;
390 mutex_unlock(&smi_lock
);
394 mutex_unlock(&smi_lock
);
399 * Write to a register in a page of the PHY
401 int rtl838x_write_phy(u32 port
, u32 page
, u32 reg
, u32 val
)
407 if (port
> 31 || page
> 4095 || reg
> 31)
410 mutex_lock(&smi_lock
);
411 if (rtl838x_smi_wait_op(10000))
414 sw_w32(BIT(port
), RTL838X_SMI_ACCESS_PHY_CTRL_0
);
417 sw_w32_mask(0xffff0000, val
<< 16, RTL838X_SMI_ACCESS_PHY_CTRL_2
);
419 park_page
= sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_1
) & ((0x1f << 15) | 0x2);
420 v
= reg
<< 20 | page
<< 3 | 0x4;
421 sw_w32(v
| park_page
, RTL838X_SMI_ACCESS_PHY_CTRL_1
);
422 sw_w32_mask(0, 1, RTL838X_SMI_ACCESS_PHY_CTRL_1
);
424 if (rtl838x_smi_wait_op(10000))
427 mutex_unlock(&smi_lock
);
431 mutex_unlock(&smi_lock
);
435 void rtl8380_get_version(struct rtl838x_switch_priv
*priv
)
437 u32 rw_save
, info_save
;
440 rw_save
= sw_r32(RTL838X_INT_RW_CTRL
);
441 sw_w32(rw_save
| 0x3, RTL838X_INT_RW_CTRL
);
443 info_save
= sw_r32(RTL838X_CHIP_INFO
);
444 sw_w32(info_save
| 0xA0000000, RTL838X_CHIP_INFO
);
446 info
= sw_r32(RTL838X_CHIP_INFO
);
447 sw_w32(info_save
, RTL838X_CHIP_INFO
);
448 sw_w32(rw_save
, RTL838X_INT_RW_CTRL
);
450 if ((info
& 0xFFFF) == 0x6275) {
451 if (((info
>> 16) & 0x1F) == 0x1)
452 priv
->version
= RTL8380_VERSION_A
;
453 else if (((info
>> 16) & 0x1F) == 0x2)
454 priv
->version
= RTL8380_VERSION_B
;
456 priv
->version
= RTL8380_VERSION_B
;
463 * Applies the same hash algorithm as the one used currently by the ASIC
465 u32
rtl838x_hash(struct rtl838x_switch_priv
*priv
, u64 seed
)
469 if (sw_r32(priv
->r
->l2_ctrl_0
) & 1) {
470 h1
= (seed
>> 11) & 0x7ff;
471 h1
= ((h1
& 0x1f) << 6) | ((h1
>> 5) & 0x3f);
473 h2
= (seed
>> 33) & 0x7ff;
474 h2
= ((h2
& 0x3f) << 5) | ((h2
>> 6) & 0x1f);
476 h3
= (seed
>> 44) & 0x7ff;
477 h3
= ((h3
& 0x7f) << 4) | ((h3
>> 7) & 0xf);
479 h
= h1
^ h2
^ h3
^ ((seed
>> 55) & 0x1ff);
480 h
^= ((seed
>> 22) & 0x7ff) ^ (seed
& 0x7ff);
482 h
= ((seed
>> 55) & 0x1ff) ^ ((seed
>> 44) & 0x7ff)
483 ^ ((seed
>> 33) & 0x7ff) ^ ((seed
>> 22) & 0x7ff)
484 ^ ((seed
>> 11) & 0x7ff) ^ (seed
& 0x7ff);
490 void rtl838x_vlan_profile_dump(int index
)
494 if (index
< 0 || index
> 7)
497 profile
= sw_r32(RTL838X_VLAN_PROFILE(index
));
499 pr_info("VLAN %d: L2 learning: %d, L2 Unknown MultiCast Field %x, \
500 IPv4 Unknown MultiCast Field %x, IPv6 Unknown MultiCast Field: %x",
501 index
, profile
& 1, (profile
>> 1) & 0x1ff, (profile
>> 10) & 0x1ff,
502 (profile
>> 19) & 0x1ff);
505 void rtl8380_sds_rst(int mac
)
507 u32 offset
= (mac
== 24) ? 0 : 0x100;
509 sw_w32_mask(1 << 11, 0, RTL838X_SDS4_FIB_REG0
+ offset
);
510 sw_w32_mask(0x3, 0, RTL838X_SDS4_REG28
+ offset
);
511 sw_w32_mask(0x3, 0x3, RTL838X_SDS4_REG28
+ offset
);
512 sw_w32_mask(0, 0x1 << 6, RTL838X_SDS4_DUMMY0
+ offset
);
513 sw_w32_mask(0x1 << 6, 0, RTL838X_SDS4_DUMMY0
+ offset
);
514 pr_debug("SERDES reset: %d\n", mac
);
517 int rtl8380_sds_power(int mac
, int val
)
519 u32 mode
= (val
== 1) ? 0x4 : 0x9;
520 u32 offset
= (mac
== 24) ? 5 : 0;
522 if ((mac
!= 24) && (mac
!= 26)) {
523 pr_err("%s: not a fibre port: %d\n", __func__
, mac
);
527 sw_w32_mask(0x1f << offset
, mode
<< offset
, RTL838X_SDS_MODE_SEL
);
529 rtl8380_sds_rst(mac
);