target/linux/realtek/files-5.4/drivers/net/dsa/rtl83xx/rtl838x.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #ifndef _RTL838X_H
   4 #define _RTL838X_H
   5
   6 #include <net/dsa.h>
   7
   8 /*
   9  * Register definition
  10  */
  11 #define RTL838X_CPU_PORT                        28
  12 #define RTL839X_CPU_PORT                        52
  13
  14 #define RTL838X_MAC_PORT_CTRL(port)             (0xd560 + (((port) << 7)))
  15 #define RTL839X_MAC_PORT_CTRL(port)             (0x8004 + (((port) << 7)))
  16 #define RTL838X_RST_GLB_CTRL_0                  (0x003c)
  17 #define RTL838X_MAC_FORCE_MODE_CTRL             (0xa104)
  18 #define RTL839X_MAC_FORCE_MODE_CTRL             (0x02bc)
  19
  20 #define RTL838X_DMY_REG31                       (0x3b28)
  21 #define RTL838X_SDS_MODE_SEL                    (0x0028)
  22 #define RTL838X_SDS_CFG_REG                     (0x0034)
  23 #define RTL838X_INT_MODE_CTRL                   (0x005c)
  24 #define RTL838X_CHIP_INFO                       (0x00d8)
  25 #define RTL839X_CHIP_INFO                       (0x0ff4)
  26 #define RTL838X_SDS4_REG28                      (0xef80)
  27 #define RTL838X_SDS4_DUMMY0                     (0xef8c)
  28 #define RTL838X_SDS5_EXT_REG6                   (0xf18c)
  29 #define RTL838X_PORT_ISO_CTRL(port)             (0x4100 + ((port) << 2))
  30 #define RTL839X_PORT_ISO_CTRL(port)             (0x1400 + ((port) << 3))
  31 #define RTL8380_SDS4_FIB_REG0                   (0xF800)
  32 #define RTL838X_STAT_PORT_STD_MIB               (0x1200)
  33 #define RTL839X_STAT_PORT_STD_MIB               (0xC000)
  34 #define RTL838X_STAT_RST                        (0x3100)
  35 #define RTL839X_STAT_RST                        (0xF504)
  36 #define RTL838X_STAT_PORT_RST                   (0x3104)
  37 #define RTL839X_STAT_PORT_RST                   (0xF508)
  38 #define RTL838X_STAT_CTRL                       (0x3108)
  39 #define RTL839X_STAT_CTRL                       (0x04cc)
  40
  41 /* Registers of the internal Serdes of the 8390 */
  42 #define RTL8390_SDS0_1_XSG0                     (0xA000)
  43 #define RTL8390_SDS0_1_XSG1                     (0xA100)
  44 #define RTL839X_SDS12_13_XSG0                   (0xB800)
  45 #define RTL839X_SDS12_13_XSG1                   (0xB900)
  46 #define RTL839X_SDS12_13_PWR0                   (0xb880)
  47 #define RTL839X_SDS12_13_PWR1                   (0xb980)
  48
  49 /* Registers of the internal Serdes of the 8380 */
  50 #define MAPLE_SDS4_REG0r                        RTL838X_SDS4_REG28
  51 #define MAPLE_SDS5_REG0r                        (RTL838X_SDS4_REG28 + 0x100)
  52 #define MAPLE_SDS4_REG3r                        RTL838X_SDS4_DUMMY0
  53 #define MAPLE_SDS5_REG3r                        (RTL838X_SDS4_REG28 + 0x100)
  54 #define MAPLE_SDS4_FIB_REG0r                    (RTL838X_SDS4_REG28 + 0x880)
  55 #define MAPLE_SDS5_FIB_REG0r                    (RTL838X_SDS4_REG28 + 0x980)
  56
  57 /* VLAN registers */
  58 #define RTL838X_VLAN_PROFILE(idx)               (0x3A88 + ((idx) << 2))
  59 #define RTL838X_VLAN_PORT_EGR_FLTR              (0x3A84)
  60 #define RTL838X_VLAN_PORT_PB_VLAN(port)         (0x3C00 + ((port) << 2))
  61 #define RTL838X_VLAN_PORT_IGR_FLTR(port)        (0x3A7C + (((port >> 4) << 2)))
  62 #define RTL838X_VLAN_PORT_IGR_FLTR_0            (0x3A7C)
  63 #define RTL838X_VLAN_PORT_IGR_FLTR_1            (0x3A7C + 4)
  64 #define RTL838X_VLAN_PORT_TAG_STS_CTRL(port)    (0xA530 + (((port) << 2)))
  65 #define RTL839X_VLAN_PROFILE(idx)               (0x25C0 + (((idx) << 3)))
  66 #define RTL839X_VLAN_CTRL                       (0x26D4)
  67 #define RTL839X_VLAN_PORT_PB_VLAN(port)         (0x26D8 + (((port) << 2)))
  68 #define RTL839X_VLAN_PORT_IGR_FLTR(port)        (0x27B4 + (((port >> 4) << 2)))
  69 #define RTL839X_VLAN_PORT_EGR_FLTR(port)        (0x27C4 + (((port >> 5) << 2)))
  70 #define RTL839X_VLAN_PORT_TAG_STS_CTRL(port)    (0x6828 + (((port) << 2)))
  71
  72 /* Table 0/1 access registers */
  73 #define RTL838X_TBL_ACCESS_CTRL_0               (0x6914)
  74 #define RTL838X_TBL_ACCESS_DATA_0(idx)          (0x6918 + ((idx) << 2))
  75 #define RTL838X_TBL_ACCESS_CTRL_1               (0xA4C8)
  76 #define RTL838X_TBL_ACCESS_DATA_1(idx)          (0xA4CC + ((idx) << 2))
  77 #define RTL839X_TBL_ACCESS_CTRL_0               (0x1190)
  78 #define RTL839X_TBL_ACCESS_DATA_0(idx)          (0x1194 + ((idx) << 2))
  79 #define RTL839X_TBL_ACCESS_CTRL_1               (0x6b80)
  80 #define RTL839X_TBL_ACCESS_DATA_1(idx)          (0x6b84 + ((idx) << 2))
  81
  82 /* MAC handling */
  83 #define RTL838X_MAC_LINK_STS                    (0xa188)
  84 #define RTL839X_MAC_LINK_STS                    (0x0390)
  85 #define RTL838X_MAC_LINK_SPD_STS(port)          (0xa190 + (((port >> 4) << 2)))
  86 #define RTL839X_MAC_LINK_SPD_STS(port)          (0x03a0 + (((port >> 4) << 2)))
  87 #define RTL838X_MAC_LINK_DUP_STS                (0xa19c)
  88 #define RTL839X_MAC_LINK_DUP_STS                (0x03b0)
  89 #define RTL838X_MAC_TX_PAUSE_STS                (0xa1a0)
  90 #define RTL839X_MAC_TX_PAUSE_STS                (0x03b8)
  91 #define RTL838X_MAC_RX_PAUSE_STS                (0xa1a4)
  92 #define RTL839X_MAC_RX_PAUSE_STS                (0x03c0)
  93 #define RTL838X_EEE_TX_TIMER_GIGA_CTRL          (0xaa04)
  94 #define RTL838X_EEE_TX_TIMER_GELITE_CTRL        (0xaa08)
  95
  96 #define RTL838X_DMA_IF_CTRL                     (0x9f58)
  97
  98 /* MAC link state bits */
  99 #define FORCE_EN                                (1 << 0)
 100 #define FORCE_LINK_EN                           (1 << 1)
 101 #define NWAY_EN                                 (1 << 2)
 102 #define DUPLX_MODE                              (1 << 3)
 103 #define TX_PAUSE_EN                             (1 << 6)
 104 #define RX_PAUSE_EN                             (1 << 7)
 105
 106 /* EEE */
 107 #define RTL838X_MAC_EEE_ABLTY                   (0xa1a8)
 108 #define RTL838X_EEE_PORT_TX_EN                  (0x014c)
 109 #define RTL838X_EEE_PORT_RX_EN                  (0x0150)
 110 #define RTL838X_EEE_CLK_STOP_CTRL               (0x0148)
 111
 112 /* L2 functionality */
 113 #define RTL838X_L2_CTRL_0                       (0x3200)
 114 #define RTL839X_L2_CTRL_0                       (0x3800)
 115 #define RTL838X_L2_CTRL_1                       (0x3204)
 116 #define RTL839X_L2_CTRL_1                       (0x3804)
 117 #define RTL838X_L2_PORT_AGING_OUT               (0x3358)
 118 #define RTL839X_L2_PORT_AGING_OUT               (0x3b74)
 119 #define RTL838X_TBL_ACCESS_L2_CTRL              (0x6900)
 120 #define RTL839X_TBL_ACCESS_L2_CTRL              (0x1180)
 121 #define RTL838X_TBL_ACCESS_L2_DATA(idx)         (0x6908 + ((idx) << 2))
 122 #define RTL839X_TBL_ACCESS_L2_DATA(idx)         (0x1184 + ((idx) << 2))
 123 #define RTL838X_L2_TBL_FLUSH_CTRL               (0x3370)
 124 #define RTL839X_L2_TBL_FLUSH_CTRL               (0x3ba0)
 125 #define RTL838X_L2_PORT_NEW_SALRN(p)            (0x328c + (((p >> 4) << 2)))
 126 #define RTL839X_L2_PORT_NEW_SALRN(p)            (0x38F0 + (((p >> 4) << 2)))
 127 #define RTL838X_L2_PORT_NEW_SA_FWD(p)           (0x3294 + (((p >> 4) << 2)))
 128 #define RTL839X_L2_PORT_NEW_SA_FWD(p)           (0x3900 + (((p >> 4) << 2)))
 129 #define RTL838X_L2_PORT_SALRN(p)                (0x328c + (((p >> 4) << 2)))
 130 #define RTL839X_L2_PORT_SALRN(p)                (0x38F0 + (((p >> 4) << 2)))
 131
 132 /* Port Mirroring */
 133 #define RTL838X_MIR_CTRL(grp)                   (0x5D00 + (((grp) << 2)))
 134 #define RTL838X_MIR_DPM_CTRL(grp)               (0x5D20 + (((grp) << 2)))
 135 #define RTL838X_MIR_SPM_CTRL(grp)               (0x5D10 + (((grp) << 2)))
 136 #define RTL839X_MIR_CTRL(grp)                   (0x2500 + (((grp) << 2)))
 137 #define RTL839X_MIR_DPM_CTRL(grp)               (0x2530 + (((grp) << 2)))
 138 #define RTL839X_MIR_SPM_CTRL(grp)               (0x2510 + (((grp) << 2)))
 139
 140 /* Storm control */
 141 #define RTL838X_STORM_CTRL                      (0x4700)
 142 #define RTL839X_STORM_CTRL                      (0x1800)
 143 #define RTL838X_STORM_CTRL_LB_CTRL(p)           (0x4884 + (((p) << 2)))
 144 #define RTL838X_STORM_CTRL_BURST_PPS_0          (0x4874)
 145 #define RTL838X_STORM_CTRL_BURST_PPS_1          (0x4878)
 146 #define RTL838X_STORM_CTRL_BURST_0              (0x487c)
 147 #define RTL838X_STORM_CTRL_BURST_1              (0x4880)
 148 #define RTL838X_SCHED_CTRL                      (0xB980)
 149 #define RTL838X_SCHED_LB_TICK_TKN_CTRL_0        (0xAD58)
 150 #define RTL838X_SCHED_LB_TICK_TKN_CTRL_1        (0xAD5C)
 151 #define RTL839X_SCHED_LB_TICK_TKN_CTRL_0        (0x1804)
 152 #define RTL839X_SCHED_LB_TICK_TKN_CTRL_1        (0x1808)
 153 #define RTL838X_SCHED_LB_THR                    (0xB984)
 154 #define RTL838X_STORM_CTRL_PORT_BC_EXCEED       (0x470C)
 155 #define RTL838X_STORM_CTRL_PORT_MC_EXCEED       (0x4710)
 156 #define RTL838X_STORM_CTRL_PORT_UC_EXCEED       (0x4714)
 157 #define RTL839X_STORM_CTRL_PORT_BC_EXCEED(p)    (0x180c + (((p >> 5) << 2)))
 158 #define RTL839X_STORM_CTRL_PORT_MC_EXCEED(p)    (0x1814 + (((p >> 5) << 2)))
 159 #define RTL839X_STORM_CTRL_PORT_UC_EXCEED(p)    (0x181c + (((p >> 5) << 2)))
 160 #define RTL838X_STORM_CTRL_PORT_UC(p)           (0x4718 + (((p) << 2)))
 161 #define RTL838X_STORM_CTRL_PORT_MC(p)           (0x478c + (((p) << 2)))
 162 #define RTL838X_STORM_CTRL_PORT_BC(p)           (0x4800 + (((p) << 2)))
 163
 164 /* Attack prevention */
 165 #define RTL838X_ATK_PRVNT_PORT_EN               (0x5B00)
 166 #define RTL838X_ATK_PRVNT_CTRL                  (0x5B04)
 167 #define RTL838X_ATK_PRVNT_ACT                   (0x5B08)
 168 #define RTL838X_ATK_PRVNT_STS                   (0x5B1C)
 169
 170 enum phy_type {
 171         PHY_NONE = 0,
 172         PHY_RTL838X_SDS = 1,
 173         PHY_RTL8218B_INT = 2,
 174         PHY_RTL8218B_EXT = 3,
 175         PHY_RTL8214FC = 4,
 176         PHY_RTL839X_SDS = 5,
 177 };
 178
 179 struct rtl838x_port {
 180         bool enable;
 181         u64 pm;
 182         u16 pvid;
 183         bool eee_enabled;
 184         enum phy_type phy;
 185         const struct dsa_port *dp;
 186 };
 187
 188 struct rtl838x_vlan_info {
 189         u64 untagged_ports;
 190         u64 tagged_ports;
 191         u8 profile_id;
 192         bool hash_mc_fid;
 193         bool hash_uc_fid;
 194         u8 fid;
 195 };
 196
 197 enum l2_entry_type {
 198         L2_INVALID = 0,
 199         L2_UNICAST = 1,
 200         L2_MULTICAST = 2,
 201         IP4_MULTICAST = 3,
 202         IP6_MULTICAST = 4,
 203 };
 204
 205 struct rtl838x_l2_entry {
 206         u8 mac[6];
 207         u16 vid;
 208         u16 rvid;
 209         u8 port;
 210         bool valid;
 211         enum l2_entry_type type;
 212         bool is_static;
 213         bool is_ip_mc;
 214         bool is_ipv6_mc;
 215         bool block_da;
 216         bool block_sa;
 217         bool suspended;
 218         bool next_hop;
 219         int age;
 220         u16 mc_portmask_index;
 221 };
 222
 223 struct rtl838x_switch_priv;
 224
 225 struct rtl838x_reg {
 226         void (*mask_port_reg_be)(u64 clear, u64 set, int reg);
 227         void (*set_port_reg_be)(u64 set, int reg);
 228         u64 (*get_port_reg_be)(int reg);
 229         void (*mask_port_reg_le)(u64 clear, u64 set, int reg);
 230         void (*set_port_reg_le)(u64 set, int reg);
 231         u64 (*get_port_reg_le)(int reg);
 232         int stat_port_rst;
 233         int stat_rst;
 234         int (*stat_port_std_mib)(int p);
 235         int (*port_iso_ctrl)(int p);
 236         int l2_ctrl_0;
 237         int l2_ctrl_1;
 238         int l2_port_aging_out;
 239         int smi_poll_ctrl;
 240         int l2_tbl_flush_ctrl;
 241         void (*exec_tbl0_cmd)(u32 cmd);
 242         void (*exec_tbl1_cmd)(u32 cmd);
 243         int (*tbl_access_data_0)(int i);
 244         int isr_glb_src;
 245         int isr_port_link_sts_chg;
 246         int imr_port_link_sts_chg;
 247         int imr_glb;
 248         void (*vlan_tables_read)(u32 vlan, struct rtl838x_vlan_info *info);
 249         void (*vlan_set_tagged)(u32 vlan, struct rtl838x_vlan_info *info);
 250         void (*vlan_set_untagged)(u32 vlan, u64 portmask);
 251         int  (*mac_force_mode_ctrl)(int port);
 252         int  (*mac_port_ctrl)(int port);
 253         int  (*l2_port_new_salrn)(int port);
 254         int  (*l2_port_new_sa_fwd)(int port);
 255         int  (*mir_ctrl)(int group);
 256         int  (*mir_dpm)(int group);
 257         int  (*mir_spm)(int group);
 258         int mac_link_sts;
 259         int mac_link_dup_sts;
 260         int  (*mac_link_spd_sts)(int port);
 261         int mac_rx_pause_sts;
 262         int mac_tx_pause_sts;
 263         u64 (*read_l2_entry_using_hash)(u32 hash, u32 position, struct rtl838x_l2_entry *e);
 264         u64 (*read_cam)(int idx, struct rtl838x_l2_entry *e);
 265         int (*vlan_profile)(int profile);
 266         int (*vlan_port_egr_filter)(int port);
 267         int (*vlan_port_igr_filter)(int port);
 268         int (*vlan_port_pb)(int port);
 269         int (*vlan_port_tag_sts_ctrl)(int port);
 270 };
 271
 272 struct rtl838x_switch_priv {
 273         /* Switch operation */
 274         struct dsa_switch *ds;
 275         struct device *dev;
 276         u16 id;
 277         u16 family_id;
 278         char version;
 279         struct rtl838x_port ports[54]; /* TODO: correct size! */
 280         struct mutex reg_mutex;
 281         int link_state_irq;
 282         int mirror_group_ports[4];
 283         struct mii_bus *mii_bus;
 284         const struct rtl838x_reg *r;
 285         u8 cpu_port;
 286         u8 port_mask;
 287         u32 fib_entries;
 288         struct dentry *dbgfs_dir;
 289 };
 290
 291 void rtl838x_dbgfs_init(struct rtl838x_switch_priv *priv);
 292
 293 #endif /* _RTL838X_H */