1 // SPDX-License-Identifier: GPL-2.0-only
3 #include <asm/mach-rtl838x/mach-rtl83xx.h>
6 extern struct mutex smi_lock
;
7 extern struct rtl83xx_soc_info soc_info
;
9 void rtl839x_print_matrix(void)
14 ptr9
= RTL838X_SW_BASE
+ RTL839X_PORT_ISO_CTRL(0);
15 for (i
= 0; i
< 52; i
+= 4)
16 pr_debug("> %16llx %16llx %16llx %16llx\n",
17 ptr9
[i
+ 0], ptr9
[i
+ 1], ptr9
[i
+ 2], ptr9
[i
+ 3]);
18 pr_debug("CPU_PORT> %16llx\n", ptr9
[52]);
21 static inline int rtl839x_port_iso_ctrl(int p
)
23 return RTL839X_PORT_ISO_CTRL(p
);
26 static inline void rtl839x_exec_tbl0_cmd(u32 cmd
)
28 sw_w32(cmd
, RTL839X_TBL_ACCESS_CTRL_0
);
29 do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_0
) & BIT(16));
32 static inline void rtl839x_exec_tbl1_cmd(u32 cmd
)
34 sw_w32(cmd
, RTL839X_TBL_ACCESS_CTRL_1
);
35 do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_1
) & BIT(16));
38 inline void rtl839x_exec_tbl2_cmd(u32 cmd
)
40 sw_w32(cmd
, RTL839X_TBL_ACCESS_CTRL_2
);
41 do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_2
) & (1 << 9));
44 static inline int rtl839x_tbl_access_data_0(int i
)
46 return RTL839X_TBL_ACCESS_DATA_0(i
);
49 static void rtl839x_vlan_tables_read(u32 vlan
, struct rtl838x_vlan_info
*info
)
52 // Read VLAN table (0) via register 0
53 struct table_reg
*r
= rtl_table_get(RTL8390_TBL_0
, 0);
55 rtl_table_read(r
, vlan
);
56 u
= sw_r32(rtl_table_data(r
, 0));
57 v
= sw_r32(rtl_table_data(r
, 1));
58 w
= sw_r32(rtl_table_data(r
, 2));
61 info
->tagged_ports
= u
;
62 info
->tagged_ports
= (info
->tagged_ports
<< 21) | ((v
>> 11) & 0x1fffff);
63 info
->profile_id
= w
>> 30 | ((v
& 1) << 2);
64 info
->hash_mc_fid
= !!(w
& BIT(2));
65 info
->hash_uc_fid
= !!(w
& BIT(3));
66 info
->fid
= (v
>> 3) & 0xff;
68 // Read UNTAG table (0) via table register 1
69 r
= rtl_table_get(RTL8390_TBL_1
, 0);
70 rtl_table_read(r
, vlan
);
71 u
= sw_r32(rtl_table_data(r
, 0));
72 v
= sw_r32(rtl_table_data(r
, 1));
75 info
->untagged_ports
= u
;
76 info
->untagged_ports
= (info
->untagged_ports
<< 21) | ((v
>> 11) & 0x1fffff);
79 static void rtl839x_vlan_set_tagged(u32 vlan
, struct rtl838x_vlan_info
*info
)
82 // Access VLAN table (0) via register 0
83 struct table_reg
*r
= rtl_table_get(RTL8390_TBL_0
, 0);
85 u
= info
->tagged_ports
>> 21;
86 v
= info
->tagged_ports
<< 11;
87 v
|= ((u32
)info
->fid
) << 3;
88 v
|= info
->hash_uc_fid
? BIT(2) : 0;
89 v
|= info
->hash_mc_fid
? BIT(1) : 0;
90 v
|= (info
->profile_id
& 0x4) ? 1 : 0;
91 w
= ((u32
)(info
->profile_id
& 3)) << 30;
93 sw_w32(u
, rtl_table_data(r
, 0));
94 sw_w32(v
, rtl_table_data(r
, 1));
95 sw_w32(w
, rtl_table_data(r
, 2));
97 rtl_table_write(r
, vlan
);
101 static void rtl839x_vlan_set_untagged(u32 vlan
, u64 portmask
)
105 // Access UNTAG table (0) via table register 1
106 struct table_reg
*r
= rtl_table_get(RTL8390_TBL_1
, 0);
111 sw_w32(u
, rtl_table_data(r
, 0));
112 sw_w32(v
, rtl_table_data(r
, 1));
113 rtl_table_write(r
, vlan
);
115 rtl_table_release(r
);
118 /* Sets the L2 forwarding to be based on either the inner VLAN tag or the outer
120 static void rtl839x_vlan_fwd_on_inner(int port
, bool is_set
)
123 rtl839x_mask_port_reg_be(BIT_ULL(port
), 0ULL, RTL839X_VLAN_PORT_FWD
);
125 rtl839x_mask_port_reg_be(0ULL, BIT_ULL(port
), RTL839X_VLAN_PORT_FWD
);
129 * Hash seed is vid (actually rvid) concatenated with the MAC address
131 static u64
rtl839x_l2_hash_seed(u64 mac
, u32 vid
)
142 * Applies the same hash algorithm as the one used currently by the ASIC to the seed
143 * and returns a key into the L2 hash table
145 static u32
rtl839x_l2_hash_key(struct rtl838x_switch_priv
*priv
, u64 seed
)
149 if (sw_r32(priv
->r
->l2_ctrl_0
) & 1) {
150 h1
= (u32
) (((seed
>> 60) & 0x3f) ^ ((seed
>> 54) & 0x3f)
151 ^ ((seed
>> 36) & 0x3f) ^ ((seed
>> 30) & 0x3f)
152 ^ ((seed
>> 12) & 0x3f) ^ ((seed
>> 6) & 0x3f));
153 h2
= (u32
) (((seed
>> 48) & 0x3f) ^ ((seed
>> 42) & 0x3f)
154 ^ ((seed
>> 24) & 0x3f) ^ ((seed
>> 18) & 0x3f)
159 ^ ((((seed
>> 48) & 0x3f) << 6) | ((seed
>> 54) & 0x3f))
160 ^ ((seed
>> 36) & 0xfff) ^ ((seed
>> 24) & 0xfff)
161 ^ ((seed
>> 12) & 0xfff) ^ (seed
& 0xfff);
167 static inline int rtl839x_mac_force_mode_ctrl(int p
)
169 return RTL839X_MAC_FORCE_MODE_CTRL
+ (p
<< 2);
172 static inline int rtl839x_mac_port_ctrl(int p
)
174 return RTL839X_MAC_PORT_CTRL(p
);
177 static inline int rtl839x_l2_port_new_salrn(int p
)
179 return RTL839X_L2_PORT_NEW_SALRN(p
);
182 static inline int rtl839x_l2_port_new_sa_fwd(int p
)
184 return RTL839X_L2_PORT_NEW_SA_FWD(p
);
187 static inline int rtl839x_mac_link_spd_sts(int p
)
189 return RTL839X_MAC_LINK_SPD_STS(p
);
192 static inline int rtl839x_trk_mbr_ctr(int group
)
194 return RTL839X_TRK_MBR_CTR
+ (group
<< 3);
197 static void rtl839x_fill_l2_entry(u32 r
[], struct rtl838x_l2_entry
*e
)
199 /* Table contains different entry types, we need to identify the right one:
200 * Check for MC entries, first
202 e
->is_ip_mc
= !!(r
[2] & BIT(31));
203 e
->is_ipv6_mc
= !!(r
[2] & BIT(30));
204 e
->type
= L2_INVALID
;
206 e
->mac
[0] = (r
[0] >> 12);
207 e
->mac
[1] = (r
[0] >> 4);
208 e
->mac
[2] = ((r
[1] >> 28) | (r
[0] << 4));
209 e
->mac
[3] = (r
[1] >> 20);
210 e
->mac
[4] = (r
[1] >> 12);
211 e
->mac
[5] = (r
[1] >> 4);
213 /* Is it a unicast entry? check multicast bit */
214 if (!(e
->mac
[0] & 1)) {
215 e
->is_static
= !!((r
[2] >> 18) & 1);
216 e
->vid
= (r
[2] >> 4) & 0xfff;
217 e
->rvid
= (r
[0] >> 20) & 0xfff;
218 e
->port
= (r
[2] >> 24) & 0x3f;
219 e
->block_da
= !!(r
[2] & (1 << 19));
220 e
->block_sa
= !!(r
[2] & (1 << 20));
221 e
->suspended
= !!(r
[2] & (1 << 17));
222 e
->next_hop
= !!(r
[2] & (1 << 16));
224 pr_info("Found next hop entry, need to read data\n");
225 e
->age
= (r
[2] >> 21) & 3;
227 if (!(r
[2] & 0xc0fd0000)) /* Check for valid entry */
230 e
->type
= L2_UNICAST
;
233 e
->type
= L2_MULTICAST
;
234 e
->mc_portmask_index
= (r
[2]>>6) & 0xfff;
239 e
->type
= IP4_MULTICAST
;
243 e
->type
= IP6_MULTICAST
;
248 * Fills the 3 SoC table registers r[] with the information of in the rtl838x_l2_entry
250 static void rtl839x_fill_l2_row(u32 r
[], struct rtl838x_l2_entry
*e
)
253 r
[0] = r
[1] = r
[2] = 0;
257 r
[2] = e
->is_ip_mc
? BIT(31) : 0;
258 r
[2] |= e
->is_ipv6_mc
? BIT(30) : 0;
260 if (!e
->is_ip_mc
&& !e
->is_ipv6_mc
) {
261 r
[0] = ((u32
)e
->mac
[0]) << 12;
262 r
[0] |= ((u32
)e
->mac
[1]) << 4;
263 r
[0] |= ((u32
)e
->mac
[2]) >> 4;
264 r
[1] = ((u32
)e
->mac
[2]) << 28;
265 r
[1] |= ((u32
)e
->mac
[3]) << 20;
266 r
[1] |= ((u32
)e
->mac
[4]) << 12;
267 r
[1] |= ((u32
)e
->mac
[5]) << 4;
269 if (!(e
->mac
[0] & 1)) { // Not multicast
270 r
[2] |= e
->is_static
? BIT(18) : 0;
272 r
[0] |= ((u32
)e
->rvid
) << 20;
273 r
[2] |= e
->port
<< 24;
274 r
[2] |= e
->block_da
? BIT(19) : 0;
275 r
[2] |= e
->block_sa
? BIT(20) : 0;
276 r
[2] |= e
->suspended
? BIT(17) : 0;
279 r
[2] |= e
->nh_vlan_target
? BIT(15) : 0;
280 r
[2] |= (e
->nh_route_id
& 0x7ff) << 4;
282 r
[2] |= ((u32
)e
->age
) << 21;
283 } else { // L2 Multicast
284 r
[0] |= ((u32
)e
->rvid
) << 20;
285 r
[2] |= ((u32
)e
->mc_portmask_index
) << 6;
286 pr_debug("Write L2 MC entry: %08x %08x %08x\n", r
[0], r
[1], r
[2]);
288 } else { // IPv4 or IPv6 MC entry
289 r
[0] = ((u32
)e
->rvid
) << 20;
290 r
[2] |= ((u32
)e
->mc_portmask_index
) << 6;
296 * Read an L2 UC or MC entry out of a hash bucket of the L2 forwarding table
297 * hash is the id of the bucket and pos is the position of the entry in that bucket
298 * The data read from the SoC is filled into rtl838x_l2_entry
300 static u64
rtl839x_read_l2_entry_using_hash(u32 hash
, u32 pos
, struct rtl838x_l2_entry
*e
)
303 struct table_reg
*q
= rtl_table_get(RTL8390_TBL_L2
, 0);
304 u32 idx
= (0 << 14) | (hash
<< 2) | pos
; // Search SRAM, with hash and at pos in bucket
307 rtl_table_read(q
, idx
);
308 for (i
= 0; i
< 3; i
++)
309 r
[i
] = sw_r32(rtl_table_data(q
, i
));
311 rtl_table_release(q
);
313 rtl839x_fill_l2_entry(r
, e
);
317 return rtl839x_l2_hash_seed(ether_addr_to_u64(&e
->mac
[0]), e
->rvid
);
320 static void rtl839x_write_l2_entry_using_hash(u32 hash
, u32 pos
, struct rtl838x_l2_entry
*e
)
323 struct table_reg
*q
= rtl_table_get(RTL8390_TBL_L2
, 0);
326 u32 idx
= (0 << 14) | (hash
<< 2) | pos
; // Access SRAM, with hash and at pos in bucket
328 rtl839x_fill_l2_row(r
, e
);
330 for (i
= 0; i
< 3; i
++)
331 sw_w32(r
[i
], rtl_table_data(q
, i
));
333 rtl_table_write(q
, idx
);
334 rtl_table_release(q
);
337 static u64
rtl839x_read_cam(int idx
, struct rtl838x_l2_entry
*e
)
340 struct table_reg
*q
= rtl_table_get(RTL8390_TBL_L2
, 1); // Access L2 Table 1
343 rtl_table_read(q
, idx
);
344 for (i
= 0; i
< 3; i
++)
345 r
[i
] = sw_r32(rtl_table_data(q
, i
));
347 rtl_table_release(q
);
349 rtl839x_fill_l2_entry(r
, e
);
353 pr_debug("Found in CAM: R1 %x R2 %x R3 %x\n", r
[0], r
[1], r
[2]);
355 // Return MAC with concatenated VID ac concatenated ID
356 return rtl839x_l2_hash_seed(ether_addr_to_u64(&e
->mac
[0]), e
->rvid
);
359 static void rtl839x_write_cam(int idx
, struct rtl838x_l2_entry
*e
)
362 struct table_reg
*q
= rtl_table_get(RTL8390_TBL_L2
, 1); // Access L2 Table 1
365 rtl839x_fill_l2_row(r
, e
);
367 for (i
= 0; i
< 3; i
++)
368 sw_w32(r
[i
], rtl_table_data(q
, i
));
370 rtl_table_write(q
, idx
);
371 rtl_table_release(q
);
374 static u64
rtl839x_read_mcast_pmask(int idx
)
377 // Read MC_PMSK (2) via register RTL8390_TBL_L2
378 struct table_reg
*q
= rtl_table_get(RTL8390_TBL_L2
, 2);
380 rtl_table_read(q
, idx
);
381 portmask
= sw_r32(rtl_table_data(q
, 0));
383 portmask
|= sw_r32(rtl_table_data(q
, 1));
384 portmask
>>= 11; // LSB is bit 11 in data registers
385 rtl_table_release(q
);
390 static void rtl839x_write_mcast_pmask(int idx
, u64 portmask
)
392 // Access MC_PMSK (2) via register RTL8380_TBL_L2
393 struct table_reg
*q
= rtl_table_get(RTL8390_TBL_L2
, 2);
395 portmask
<<= 11; // LSB is bit 11 in data registers
396 sw_w32((u32
)(portmask
>> 32), rtl_table_data(q
, 0));
397 sw_w32((u32
)((portmask
& 0xfffff800)), rtl_table_data(q
, 1));
398 rtl_table_write(q
, idx
);
399 rtl_table_release(q
);
402 static void rtl839x_vlan_profile_setup(int profile
)
405 u32 pmask_id
= UNKNOWN_MC_PMASK
;
407 p
[0] = pmask_id
; // Use portmaks 0xfff for unknown IPv6 MC flooding
408 // Enable L2 Learning BIT 0, portmask UNKNOWN_MC_PMASK for IP/L2-MC traffic flooding
409 p
[1] = 1 | pmask_id
<< 1 | pmask_id
<< 13;
411 sw_w32(p
[0], RTL839X_VLAN_PROFILE(profile
));
412 sw_w32(p
[1], RTL839X_VLAN_PROFILE(profile
) + 4);
414 rtl839x_write_mcast_pmask(UNKNOWN_MC_PMASK
, 0x000fffffffffffff);
417 static inline int rtl839x_vlan_port_egr_filter(int port
)
419 return RTL839X_VLAN_PORT_EGR_FLTR(port
);
422 static inline int rtl839x_vlan_port_igr_filter(int port
)
424 return RTL839X_VLAN_PORT_IGR_FLTR(port
);
427 u64
rtl839x_traffic_get(int source
)
429 return rtl839x_get_port_reg_be(rtl839x_port_iso_ctrl(source
));
432 void rtl839x_traffic_set(int source
, u64 dest_matrix
)
434 rtl839x_set_port_reg_be(dest_matrix
, rtl839x_port_iso_ctrl(source
));
437 void rtl839x_traffic_enable(int source
, int dest
)
439 rtl839x_mask_port_reg_be(0, BIT_ULL(dest
), rtl839x_port_iso_ctrl(source
));
442 void rtl839x_traffic_disable(int source
, int dest
)
444 rtl839x_mask_port_reg_be(BIT_ULL(dest
), 0, rtl839x_port_iso_ctrl(source
));
447 irqreturn_t
rtl839x_switch_irq(int irq
, void *dev_id
)
449 struct dsa_switch
*ds
= dev_id
;
450 u32 status
= sw_r32(RTL839X_ISR_GLB_SRC
);
451 u64 ports
= rtl839x_get_port_reg_le(RTL839X_ISR_PORT_LINK_STS_CHG
);
456 rtl839x_set_port_reg_le(ports
, RTL839X_ISR_PORT_LINK_STS_CHG
);
457 pr_debug("RTL8390 Link change: status: %x, ports %llx\n", status
, ports
);
459 for (i
= 0; i
< RTL839X_CPU_PORT
; i
++) {
460 if (ports
& BIT_ULL(i
)) {
461 link
= rtl839x_get_port_reg_le(RTL839X_MAC_LINK_STS
);
462 if (link
& BIT_ULL(i
))
463 dsa_port_phylink_mac_change(ds
, i
, true);
465 dsa_port_phylink_mac_change(ds
, i
, false);
472 int rtl8390_sds_power(int mac
, int val
)
474 u32 offset
= (mac
== 48) ? 0x0 : 0x100;
475 u32 mode
= val
? 0 : 1;
477 pr_debug("In %s: mac %d, set %d\n", __func__
, mac
, val
);
479 if ((mac
!= 48) && (mac
!= 49)) {
480 pr_err("%s: not an SFP port: %d\n", __func__
, mac
);
484 // Set bit 1003. 1000 starts at 7c
485 sw_w32_mask(BIT(11), mode
<< 11, RTL839X_SDS12_13_PWR0
+ offset
);
490 int rtl839x_read_phy(u32 port
, u32 page
, u32 reg
, u32
*val
)
494 if (port
> 63 || page
> 4095 || reg
> 31)
497 mutex_lock(&smi_lock
);
499 sw_w32_mask(0xffff0000, port
<< 16, RTL839X_PHYREG_DATA_CTRL
);
500 v
= reg
<< 5 | page
<< 10 | ((page
== 0x1fff) ? 0x1f : 0) << 23;
501 sw_w32(v
, RTL839X_PHYREG_ACCESS_CTRL
);
503 sw_w32(0x1ff, RTL839X_PHYREG_CTRL
);
506 sw_w32(v
, RTL839X_PHYREG_ACCESS_CTRL
);
509 } while (sw_r32(RTL839X_PHYREG_ACCESS_CTRL
) & 0x1);
511 *val
= sw_r32(RTL839X_PHYREG_DATA_CTRL
) & 0xffff;
513 mutex_unlock(&smi_lock
);
517 int rtl839x_write_phy(u32 port
, u32 page
, u32 reg
, u32 val
)
523 if (port
> 63 || page
> 4095 || reg
> 31)
526 mutex_lock(&smi_lock
);
529 rtl839x_set_port_reg_le(BIT_ULL(port
), RTL839X_PHYREG_PORT_CTRL
);
531 sw_w32_mask(0xffff0000, val
<< 16, RTL839X_PHYREG_DATA_CTRL
);
533 v
= reg
<< 5 | page
<< 10 | ((page
== 0x1fff) ? 0x1f : 0) << 23;
534 sw_w32(v
, RTL839X_PHYREG_ACCESS_CTRL
);
536 sw_w32(0x1ff, RTL839X_PHYREG_CTRL
);
538 v
|= BIT(3) | 1; /* Write operation and execute */
539 sw_w32(v
, RTL839X_PHYREG_ACCESS_CTRL
);
542 } while (sw_r32(RTL839X_PHYREG_ACCESS_CTRL
) & 0x1);
544 if (sw_r32(RTL839X_PHYREG_ACCESS_CTRL
) & 0x2)
547 mutex_unlock(&smi_lock
);
552 * Read an mmd register of the PHY
554 int rtl839x_read_mmd_phy(u32 port
, u32 devnum
, u32 regnum
, u32
*val
)
559 mutex_lock(&smi_lock
);
562 sw_w32_mask(0xffff << 16, port
<< 16, RTL839X_PHYREG_DATA_CTRL
);
564 // Set MMD device number and register to write to
565 sw_w32(devnum
<< 16 | (regnum
& 0xffff), RTL839X_PHYREG_MMD_CTRL
);
567 v
= BIT(2) | BIT(0); // MMD-access | EXEC
568 sw_w32(v
, RTL839X_PHYREG_ACCESS_CTRL
);
571 v
= sw_r32(RTL839X_PHYREG_ACCESS_CTRL
);
572 } while (v
& BIT(0));
573 // There is no error-checking via BIT 1 of v, as it does not seem to be set correctly
574 *val
= (sw_r32(RTL839X_PHYREG_DATA_CTRL
) & 0xffff);
575 pr_debug("%s: port %d, regnum: %x, val: %x (err %d)\n", __func__
, port
, regnum
, *val
, err
);
577 mutex_unlock(&smi_lock
);
583 * Write to an mmd register of the PHY
585 int rtl839x_write_mmd_phy(u32 port
, u32 devnum
, u32 regnum
, u32 val
)
590 mutex_lock(&smi_lock
);
593 rtl839x_set_port_reg_le(BIT_ULL(port
), RTL839X_PHYREG_PORT_CTRL
);
596 sw_w32_mask(0xffff << 16, val
<< 16, RTL839X_PHYREG_DATA_CTRL
);
598 // Set MMD device number and register to write to
599 sw_w32(devnum
<< 16 | (regnum
& 0xffff), RTL839X_PHYREG_MMD_CTRL
);
601 v
= BIT(3) | BIT(2) | BIT(0); // WRITE | MMD-access | EXEC
602 sw_w32(v
, RTL839X_PHYREG_ACCESS_CTRL
);
605 v
= sw_r32(RTL839X_PHYREG_ACCESS_CTRL
);
606 } while (v
& BIT(0));
608 pr_debug("%s: port %d, regnum: %x, val: %x (err %d)\n", __func__
, port
, regnum
, val
, err
);
609 mutex_unlock(&smi_lock
);
613 void rtl8390_get_version(struct rtl838x_switch_priv
*priv
)
617 sw_w32_mask(0xf << 28, 0xa << 28, RTL839X_CHIP_INFO
);
618 info
= sw_r32(RTL839X_CHIP_INFO
);
619 pr_debug("Chip-Info: %x\n", info
);
620 priv
->version
= RTL8390_VERSION_A
;
623 void rtl839x_vlan_profile_dump(int profile
)
627 if (profile
< 0 || profile
> 7)
630 p
[0] = sw_r32(RTL839X_VLAN_PROFILE(profile
));
631 p
[1] = sw_r32(RTL839X_VLAN_PROFILE(profile
) + 4);
633 pr_info("VLAN profile %d: L2 learning: %d, UNKN L2MC FLD PMSK %d, \
634 UNKN IPMC FLD PMSK %d, UNKN IPv6MC FLD PMSK: %d",
635 profile
, p
[1] & 1, (p
[1] >> 1) & 0xfff, (p
[1] >> 13) & 0xfff,
637 pr_info("VLAN profile %d: raw %08x, %08x\n", profile
, p
[0], p
[1]);
640 static void rtl839x_stp_get(struct rtl838x_switch_priv
*priv
, u16 msti
, u32 port_state
[])
643 u32 cmd
= 1 << 16 /* Execute cmd */
645 | 5 << 12 /* Table type 0b101 */
647 priv
->r
->exec_tbl0_cmd(cmd
);
649 for (i
= 0; i
< 4; i
++)
650 port_state
[i
] = sw_r32(priv
->r
->tbl_access_data_0(i
));
653 static void rtl839x_stp_set(struct rtl838x_switch_priv
*priv
, u16 msti
, u32 port_state
[])
656 u32 cmd
= 1 << 16 /* Execute cmd */
657 | 1 << 15 /* Write */
658 | 5 << 12 /* Table type 0b101 */
660 for (i
= 0; i
< 4; i
++)
661 sw_w32(port_state
[i
], priv
->r
->tbl_access_data_0(i
));
662 priv
->r
->exec_tbl0_cmd(cmd
);
666 * Enables or disables the EEE/EEEP capability of a port
668 void rtl839x_port_eee_set(struct rtl838x_switch_priv
*priv
, int port
, bool enable
)
672 // This works only for Ethernet ports, and on the RTL839X, ports above 47 are SFP
677 pr_debug("In %s: setting port %d to %d\n", __func__
, port
, enable
);
678 v
= enable
? 0xf : 0x0;
680 // Set EEE for 100, 500, 1000MBit and 10GBit
681 sw_w32_mask(0xf << 8, v
<< 8, rtl839x_mac_force_mode_ctrl(port
));
683 // Set TX/RX EEE state
684 v
= enable
? 0x3 : 0x0;
685 sw_w32(v
, RTL839X_EEE_CTRL(port
));
687 priv
->ports
[port
].eee_enabled
= enable
;
691 * Get EEE own capabilities and negotiation result
693 int rtl839x_eee_port_ability(struct rtl838x_switch_priv
*priv
, struct ethtool_eee
*e
, int port
)
700 link
= rtl839x_get_port_reg_le(RTL839X_MAC_LINK_STS
);
701 if (!(link
& BIT_ULL(port
)))
704 if (sw_r32(rtl839x_mac_force_mode_ctrl(port
)) & BIT(8))
705 e
->advertised
|= ADVERTISED_100baseT_Full
;
707 if (sw_r32(rtl839x_mac_force_mode_ctrl(port
)) & BIT(10))
708 e
->advertised
|= ADVERTISED_1000baseT_Full
;
710 a
= rtl839x_get_port_reg_le(RTL839X_MAC_EEE_ABLTY
);
711 pr_info("Link partner: %016llx\n", a
);
712 if (rtl839x_get_port_reg_le(RTL839X_MAC_EEE_ABLTY
) & BIT_ULL(port
)) {
713 e
->lp_advertised
= ADVERTISED_100baseT_Full
;
714 e
->lp_advertised
|= ADVERTISED_1000baseT_Full
;
721 static void rtl839x_init_eee(struct rtl838x_switch_priv
*priv
, bool enable
)
725 pr_info("Setting up EEE, state: %d\n", enable
);
727 // Set wake timer for TX and pause timer both to 0x21
728 sw_w32_mask(0xff << 20| 0xff, 0x21 << 20| 0x21, RTL839X_EEE_TX_TIMER_GELITE_CTRL
);
729 // Set pause wake timer for GIGA-EEE to 0x11
730 sw_w32_mask(0xff << 20, 0x11 << 20, RTL839X_EEE_TX_TIMER_GIGA_CTRL
);
731 // Set pause wake timer for 10GBit ports to 0x11
732 sw_w32_mask(0xff << 20, 0x11 << 20, RTL839X_EEE_TX_TIMER_10G_CTRL
);
734 // Setup EEE on all ports
735 for (i
= 0; i
< priv
->cpu_port
; i
++) {
736 if (priv
->ports
[i
].phy
)
737 rtl839x_port_eee_set(priv
, i
, enable
);
739 priv
->eee_enabled
= enable
;
742 const struct rtl838x_reg rtl839x_reg
= {
743 .mask_port_reg_be
= rtl839x_mask_port_reg_be
,
744 .set_port_reg_be
= rtl839x_set_port_reg_be
,
745 .get_port_reg_be
= rtl839x_get_port_reg_be
,
746 .mask_port_reg_le
= rtl839x_mask_port_reg_le
,
747 .set_port_reg_le
= rtl839x_set_port_reg_le
,
748 .get_port_reg_le
= rtl839x_get_port_reg_le
,
749 .stat_port_rst
= RTL839X_STAT_PORT_RST
,
750 .stat_rst
= RTL839X_STAT_RST
,
751 .stat_port_std_mib
= RTL839X_STAT_PORT_STD_MIB
,
752 .traffic_enable
= rtl839x_traffic_enable
,
753 .traffic_disable
= rtl839x_traffic_disable
,
754 .traffic_get
= rtl839x_traffic_get
,
755 .traffic_set
= rtl839x_traffic_set
,
756 .port_iso_ctrl
= rtl839x_port_iso_ctrl
,
757 .l2_ctrl_0
= RTL839X_L2_CTRL_0
,
758 .l2_ctrl_1
= RTL839X_L2_CTRL_1
,
759 .l2_port_aging_out
= RTL839X_L2_PORT_AGING_OUT
,
760 .smi_poll_ctrl
= RTL839X_SMI_PORT_POLLING_CTRL
,
761 .l2_tbl_flush_ctrl
= RTL839X_L2_TBL_FLUSH_CTRL
,
762 .exec_tbl0_cmd
= rtl839x_exec_tbl0_cmd
,
763 .exec_tbl1_cmd
= rtl839x_exec_tbl1_cmd
,
764 .tbl_access_data_0
= rtl839x_tbl_access_data_0
,
765 .isr_glb_src
= RTL839X_ISR_GLB_SRC
,
766 .isr_port_link_sts_chg
= RTL839X_ISR_PORT_LINK_STS_CHG
,
767 .imr_port_link_sts_chg
= RTL839X_IMR_PORT_LINK_STS_CHG
,
768 .imr_glb
= RTL839X_IMR_GLB
,
769 .vlan_tables_read
= rtl839x_vlan_tables_read
,
770 .vlan_set_tagged
= rtl839x_vlan_set_tagged
,
771 .vlan_set_untagged
= rtl839x_vlan_set_untagged
,
772 .vlan_profile_dump
= rtl839x_vlan_profile_dump
,
773 .vlan_profile_setup
= rtl839x_vlan_profile_setup
,
774 .vlan_fwd_on_inner
= rtl839x_vlan_fwd_on_inner
,
775 .stp_get
= rtl839x_stp_get
,
776 .stp_set
= rtl839x_stp_set
,
777 .mac_force_mode_ctrl
= rtl839x_mac_force_mode_ctrl
,
778 .mac_port_ctrl
= rtl839x_mac_port_ctrl
,
779 .l2_port_new_salrn
= rtl839x_l2_port_new_salrn
,
780 .l2_port_new_sa_fwd
= rtl839x_l2_port_new_sa_fwd
,
781 .mir_ctrl
= RTL839X_MIR_CTRL
,
782 .mir_dpm
= RTL839X_MIR_DPM_CTRL
,
783 .mir_spm
= RTL839X_MIR_SPM_CTRL
,
784 .mac_link_sts
= RTL839X_MAC_LINK_STS
,
785 .mac_link_dup_sts
= RTL839X_MAC_LINK_DUP_STS
,
786 .mac_link_spd_sts
= rtl839x_mac_link_spd_sts
,
787 .mac_rx_pause_sts
= RTL839X_MAC_RX_PAUSE_STS
,
788 .mac_tx_pause_sts
= RTL839X_MAC_TX_PAUSE_STS
,
789 .read_l2_entry_using_hash
= rtl839x_read_l2_entry_using_hash
,
790 .write_l2_entry_using_hash
= rtl839x_write_l2_entry_using_hash
,
791 .read_cam
= rtl839x_read_cam
,
792 .write_cam
= rtl839x_write_cam
,
793 .vlan_port_egr_filter
= RTL839X_VLAN_PORT_EGR_FLTR(0),
794 .vlan_port_igr_filter
= RTL839X_VLAN_PORT_IGR_FLTR(0),
795 .vlan_port_pb
= RTL839X_VLAN_PORT_PB_VLAN
,
796 .vlan_port_tag_sts_ctrl
= RTL839X_VLAN_PORT_TAG_STS_CTRL
,
797 .trk_mbr_ctr
= rtl839x_trk_mbr_ctr
,
798 .rma_bpdu_fld_pmask
= RTL839X_RMA_BPDU_FLD_PMSK
,
799 .spcl_trap_eapol_ctrl
= RTL839X_SPCL_TRAP_EAPOL_CTRL
,
800 .init_eee
= rtl839x_init_eee
,
801 .port_eee_set
= rtl839x_port_eee_set
,
802 .eee_port_ability
= rtl839x_eee_port_ability
,
803 .l2_hash_seed
= rtl839x_l2_hash_seed
,
804 .l2_hash_key
= rtl839x_l2_hash_key
,
805 .read_mcast_pmask
= rtl839x_read_mcast_pmask
,
806 .write_mcast_pmask
= rtl839x_write_mcast_pmask
,