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[openwrt/staging/jow.git] / target / linux / realtek / files-5.4 / drivers / net / dsa / rtl83xx / rtl839x.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <asm/mach-rtl838x/mach-rtl83xx.h>
4 #include "rtl83xx.h"
5
6 extern struct mutex smi_lock;
7 extern struct rtl83xx_soc_info soc_info;
8
9 void rtl839x_print_matrix(void)
10 {
11 volatile u64 *ptr9;
12 int i;
13
14 ptr9 = RTL838X_SW_BASE + RTL839X_PORT_ISO_CTRL(0);
15 for (i = 0; i < 52; i += 4)
16 pr_debug("> %16llx %16llx %16llx %16llx\n",
17 ptr9[i + 0], ptr9[i + 1], ptr9[i + 2], ptr9[i + 3]);
18 pr_debug("CPU_PORT> %16llx\n", ptr9[52]);
19 }
20
21 static inline int rtl839x_port_iso_ctrl(int p)
22 {
23 return RTL839X_PORT_ISO_CTRL(p);
24 }
25
26 static inline void rtl839x_exec_tbl0_cmd(u32 cmd)
27 {
28 sw_w32(cmd, RTL839X_TBL_ACCESS_CTRL_0);
29 do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_0) & BIT(16));
30 }
31
32 static inline void rtl839x_exec_tbl1_cmd(u32 cmd)
33 {
34 sw_w32(cmd, RTL839X_TBL_ACCESS_CTRL_1);
35 do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_1) & BIT(16));
36 }
37
38 inline void rtl839x_exec_tbl2_cmd(u32 cmd)
39 {
40 sw_w32(cmd, RTL839X_TBL_ACCESS_CTRL_2);
41 do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_2) & (1 << 9));
42 }
43
44 static inline int rtl839x_tbl_access_data_0(int i)
45 {
46 return RTL839X_TBL_ACCESS_DATA_0(i);
47 }
48
49 static void rtl839x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info)
50 {
51 u32 u, v, w;
52 // Read VLAN table (0) via register 0
53 struct table_reg *r = rtl_table_get(RTL8390_TBL_0, 0);
54
55 rtl_table_read(r, vlan);
56 u = sw_r32(rtl_table_data(r, 0));
57 v = sw_r32(rtl_table_data(r, 1));
58 w = sw_r32(rtl_table_data(r, 2));
59 rtl_table_release(r);
60
61 info->tagged_ports = u;
62 info->tagged_ports = (info->tagged_ports << 21) | ((v >> 11) & 0x1fffff);
63 info->profile_id = w >> 30 | ((v & 1) << 2);
64 info->hash_mc_fid = !!(w & BIT(2));
65 info->hash_uc_fid = !!(w & BIT(3));
66 info->fid = (v >> 3) & 0xff;
67
68 // Read UNTAG table (0) via table register 1
69 r = rtl_table_get(RTL8390_TBL_1, 0);
70 rtl_table_read(r, vlan);
71 u = sw_r32(rtl_table_data(r, 0));
72 v = sw_r32(rtl_table_data(r, 1));
73 rtl_table_release(r);
74
75 info->untagged_ports = u;
76 info->untagged_ports = (info->untagged_ports << 21) | ((v >> 11) & 0x1fffff);
77 }
78
79 static void rtl839x_vlan_set_tagged(u32 vlan, struct rtl838x_vlan_info *info)
80 {
81 u32 u, v, w;
82 // Access VLAN table (0) via register 0
83 struct table_reg *r = rtl_table_get(RTL8390_TBL_0, 0);
84
85 u = info->tagged_ports >> 21;
86 v = info->tagged_ports << 11;
87 v |= ((u32)info->fid) << 3;
88 v |= info->hash_uc_fid ? BIT(2) : 0;
89 v |= info->hash_mc_fid ? BIT(1) : 0;
90 v |= (info->profile_id & 0x4) ? 1 : 0;
91 w = ((u32)(info->profile_id & 3)) << 30;
92
93 sw_w32(u, rtl_table_data(r, 0));
94 sw_w32(v, rtl_table_data(r, 1));
95 sw_w32(w, rtl_table_data(r, 2));
96
97 rtl_table_write(r, vlan);
98 rtl_table_release(r);
99 }
100
101 static void rtl839x_vlan_set_untagged(u32 vlan, u64 portmask)
102 {
103 u32 u, v;
104
105 // Access UNTAG table (0) via table register 1
106 struct table_reg *r = rtl_table_get(RTL8390_TBL_1, 0);
107
108 u = portmask >> 21;
109 v = portmask << 11;
110
111 sw_w32(u, rtl_table_data(r, 0));
112 sw_w32(v, rtl_table_data(r, 1));
113 rtl_table_write(r, vlan);
114
115 rtl_table_release(r);
116 }
117
118 static inline int rtl839x_mac_force_mode_ctrl(int p)
119 {
120 return RTL839X_MAC_FORCE_MODE_CTRL + (p << 2);
121 }
122
123 static inline int rtl839x_mac_port_ctrl(int p)
124 {
125 return RTL839X_MAC_PORT_CTRL(p);
126 }
127
128 static inline int rtl839x_l2_port_new_salrn(int p)
129 {
130 return RTL839X_L2_PORT_NEW_SALRN(p);
131 }
132
133 static inline int rtl839x_l2_port_new_sa_fwd(int p)
134 {
135 return RTL839X_L2_PORT_NEW_SA_FWD(p);
136 }
137
138 static inline int rtl839x_mac_link_spd_sts(int p)
139 {
140 return RTL839X_MAC_LINK_SPD_STS(p);
141 }
142
143 static inline int rtl839x_trk_mbr_ctr(int group)
144 {
145 return RTL839X_TRK_MBR_CTR + (group << 3);
146 }
147
148 static void rtl839x_fill_l2_entry(u32 r[], struct rtl838x_l2_entry *e)
149 {
150 /* Table contains different entry types, we need to identify the right one:
151 * Check for MC entries, first
152 */
153 e->is_ip_mc = !!(r[2] & BIT(31));
154 e->is_ipv6_mc = !!(r[2] & BIT(30));
155 e->type = L2_INVALID;
156 if (!e->is_ip_mc) {
157 e->mac[0] = (r[0] >> 12);
158 e->mac[1] = (r[0] >> 4);
159 e->mac[2] = ((r[1] >> 28) | (r[0] << 4));
160 e->mac[3] = (r[1] >> 20);
161 e->mac[4] = (r[1] >> 12);
162 e->mac[5] = (r[1] >> 4);
163
164 /* Is it a unicast entry? check multicast bit */
165 if (!(e->mac[0] & 1)) {
166 e->is_static = !!((r[2] >> 18) & 1);
167 e->vid = (r[2] >> 4) & 0xfff;
168 e->rvid = (r[0] >> 20) & 0xfff;
169 e->port = (r[2] >> 24) & 0x3f;
170 e->block_da = !!(r[2] & (1 << 19));
171 e->block_sa = !!(r[2] & (1 << 20));
172 e->suspended = !!(r[2] & (1 << 17));
173 e->next_hop = !!(r[2] & (1 << 16));
174 if (e->next_hop)
175 pr_info("Found next hop entry, need to read data\n");
176 e->age = (r[2] >> 21) & 3;
177 e->valid = true;
178 if (!(r[2] & 0xc0fd0000)) /* Check for valid entry */
179 e->valid = false;
180 else
181 e->type = L2_UNICAST;
182 } else {
183 e->valid = true;
184 e->type = L2_MULTICAST;
185 e->mc_portmask_index = (r[2]>>6) & 0xfff;
186 }
187 }
188 if (e->is_ip_mc) {
189 e->valid = true;
190 e->type = IP4_MULTICAST;
191 }
192 if (e->is_ipv6_mc) {
193 e->valid = true;
194 e->type = IP6_MULTICAST;
195 }
196 }
197
198 static u64 rtl839x_read_l2_entry_using_hash(u32 hash, u32 position, struct rtl838x_l2_entry *e)
199 {
200 u64 entry;
201 u32 r[3];
202
203 /* Search in SRAM, with hash and at position in hash bucket (0-3) */
204 u32 idx = (0 << 14) | (hash << 2) | position;
205
206 u32 cmd = 1 << 17 /* Execute cmd */
207 | 0 << 16 /* Read */
208 | 0 << 14 /* Table type 0b00 */
209 | (idx & 0x3fff);
210
211 sw_w32(cmd, RTL839X_TBL_ACCESS_L2_CTRL);
212 do { } while (sw_r32(RTL839X_TBL_ACCESS_L2_CTRL) & (1 << 17));
213 r[0] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(0));
214 r[1] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(1));
215 r[2] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(2));
216
217 rtl839x_fill_l2_entry(r, e);
218
219 entry = (((u64) r[0]) << 12) | ((r[1] & 0xfffffff0) << 12) | ((r[2] >> 4) & 0xfff);
220 return entry;
221 }
222
223 static u64 rtl839x_read_cam(int idx, struct rtl838x_l2_entry *e)
224 {
225 u64 entry;
226 u32 r[3];
227
228 u32 cmd = 1 << 17 /* Execute cmd */
229 | 0 << 16 /* Read */
230 | 1 << 14 /* Table type 0b01 */
231 | (idx & 0x3f);
232 sw_w32(cmd, RTL839X_TBL_ACCESS_L2_CTRL);
233 do { } while (sw_r32(RTL839X_TBL_ACCESS_L2_CTRL) & (1 << 17));
234 r[0] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(0));
235 r[1] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(1));
236 r[2] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(2));
237
238
239 rtl839x_fill_l2_entry(r, e);
240 if (e->valid)
241 pr_info("Found in CAM: R1 %x R2 %x R3 %x\n", r[0], r[1], r[2]);
242 else
243 return 0;
244
245 entry = (((u64) r[0]) << 12) | ((r[1] & 0xfffffff0) << 12) | ((r[2] >> 4) & 0xfff);
246 return entry;
247 }
248
249 static u64 rtl839x_read_mcast_pmask(int idx)
250 {
251 u64 portmask;
252 // Read MC_PMSK (2) via register RTL8390_TBL_L2
253 struct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 2);
254
255 rtl_table_read(q, idx);
256 portmask = sw_r32(rtl_table_data(q, 0));
257 portmask <<= 32;
258 portmask |= sw_r32(rtl_table_data(q, 1));
259 portmask >>= 11; // LSB is bit 11 in data registers
260 rtl_table_release(q);
261
262 return portmask;
263 }
264
265 static void rtl839x_write_mcast_pmask(int idx, u64 portmask)
266 {
267 // Access MC_PMSK (2) via register RTL8380_TBL_L2
268 struct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 2);
269
270 portmask <<= 11; // LSB is bit 11 in data registers
271 sw_w32((u32)(portmask >> 32), rtl_table_data(q, 0));
272 sw_w32((u32)((portmask & 0xfffff800)), rtl_table_data(q, 1));
273 rtl_table_write(q, idx);
274 rtl_table_release(q);
275 }
276
277 static void rtl839x_vlan_profile_setup(int profile)
278 {
279 u32 p[2];
280 u32 pmask_id = UNKNOWN_MC_PMASK;
281
282 p[0] = pmask_id; // Use portmaks 0xfff for unknown IPv6 MC flooding
283 // Enable L2 Learning BIT 0, portmask UNKNOWN_MC_PMASK for IP/L2-MC traffic flooding
284 p[1] = 1 | pmask_id << 1 | pmask_id << 13;
285
286 sw_w32(p[0], RTL839X_VLAN_PROFILE(profile));
287 sw_w32(p[1], RTL839X_VLAN_PROFILE(profile) + 4);
288
289 rtl839x_write_mcast_pmask(UNKNOWN_MC_PMASK, 0x000fffffffffffff);
290 }
291
292 static inline int rtl839x_vlan_port_egr_filter(int port)
293 {
294 return RTL839X_VLAN_PORT_EGR_FLTR(port);
295 }
296
297 static inline int rtl839x_vlan_port_igr_filter(int port)
298 {
299 return RTL839X_VLAN_PORT_IGR_FLTR(port);
300 }
301
302 u64 rtl839x_traffic_get(int source)
303 {
304 return rtl839x_get_port_reg_be(rtl839x_port_iso_ctrl(source));
305 }
306
307 void rtl839x_traffic_set(int source, u64 dest_matrix)
308 {
309 rtl839x_set_port_reg_be(dest_matrix, rtl839x_port_iso_ctrl(source));
310 }
311
312 void rtl839x_traffic_enable(int source, int dest)
313 {
314 rtl839x_mask_port_reg_be(0, BIT_ULL(dest), rtl839x_port_iso_ctrl(source));
315 }
316
317 void rtl839x_traffic_disable(int source, int dest)
318 {
319 rtl839x_mask_port_reg_be(BIT(dest), 0, rtl839x_port_iso_ctrl(source));
320 }
321
322 irqreturn_t rtl839x_switch_irq(int irq, void *dev_id)
323 {
324 struct dsa_switch *ds = dev_id;
325 u32 status = sw_r32(RTL839X_ISR_GLB_SRC);
326 u64 ports = rtl839x_get_port_reg_le(RTL839X_ISR_PORT_LINK_STS_CHG);
327 u64 link;
328 int i;
329
330 /* Clear status */
331 rtl839x_set_port_reg_le(ports, RTL839X_ISR_PORT_LINK_STS_CHG);
332 pr_debug("RTL8390 Link change: status: %x, ports %llx\n", status, ports);
333
334 for (i = 0; i < 52; i++) {
335 if (ports & (1ULL << i)) {
336 link = rtl839x_get_port_reg_le(RTL839X_MAC_LINK_STS);
337 if (link & (1ULL << i))
338 dsa_port_phylink_mac_change(ds, i, true);
339 else
340 dsa_port_phylink_mac_change(ds, i, false);
341 }
342 }
343 return IRQ_HANDLED;
344 }
345
346 // TODO: unused
347 int rtl8390_sds_power(int mac, int val)
348 {
349 u32 offset = (mac == 48) ? 0x0 : 0x100;
350 u32 mode = val ? 0 : 1;
351
352 pr_debug("In %s: mac %d, set %d\n", __func__, mac, val);
353
354 if ((mac != 48) && (mac != 49)) {
355 pr_err("%s: not an SFP port: %d\n", __func__, mac);
356 return -1;
357 }
358
359 // Set bit 1003. 1000 starts at 7c
360 sw_w32_mask(BIT(11), mode << 11, RTL839X_SDS12_13_PWR0 + offset);
361
362 return 0;
363 }
364
365
366 int rtl839x_read_phy(u32 port, u32 page, u32 reg, u32 *val)
367 {
368 u32 v;
369
370 if (port > 63 || page > 4095 || reg > 31)
371 return -ENOTSUPP;
372
373 mutex_lock(&smi_lock);
374
375 sw_w32_mask(0xffff0000, port << 16, RTL839X_PHYREG_DATA_CTRL);
376 v = reg << 5 | page << 10 | ((page == 0x1fff) ? 0x1f : 0) << 23;
377 sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
378
379 sw_w32(0x1ff, RTL839X_PHYREG_CTRL);
380
381 v |= 1;
382 sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
383
384 do {
385 } while (sw_r32(RTL839X_PHYREG_ACCESS_CTRL) & 0x1);
386
387 *val = sw_r32(RTL839X_PHYREG_DATA_CTRL) & 0xffff;
388
389 mutex_unlock(&smi_lock);
390 return 0;
391 }
392
393 int rtl839x_write_phy(u32 port, u32 page, u32 reg, u32 val)
394 {
395 u32 v;
396 int err = 0;
397
398 val &= 0xffff;
399 if (port > 63 || page > 4095 || reg > 31)
400 return -ENOTSUPP;
401
402 mutex_lock(&smi_lock);
403
404 // Set PHY to access
405 rtl839x_set_port_reg_le(BIT_ULL(port), RTL839X_PHYREG_PORT_CTRL);
406
407 sw_w32_mask(0xffff0000, val << 16, RTL839X_PHYREG_DATA_CTRL);
408
409 v = reg << 5 | page << 10 | ((page == 0x1fff) ? 0x1f : 0) << 23;
410 sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
411
412 sw_w32(0x1ff, RTL839X_PHYREG_CTRL);
413
414 v |= BIT(3) | 1; /* Write operation and execute */
415 sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
416
417 do {
418 } while (sw_r32(RTL839X_PHYREG_ACCESS_CTRL) & 0x1);
419
420 if (sw_r32(RTL839X_PHYREG_ACCESS_CTRL) & 0x2)
421 err = -EIO;
422
423 mutex_unlock(&smi_lock);
424 return err;
425 }
426
427 /*
428 * Read an mmd register of the PHY
429 */
430 int rtl839x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val)
431 {
432 int err = 0;
433 u32 v;
434
435 mutex_lock(&smi_lock);
436
437 // Set PHY to access
438 sw_w32_mask(0xffff << 16, port << 16, RTL839X_PHYREG_DATA_CTRL);
439
440 // Set MMD device number and register to write to
441 sw_w32(devnum << 16 | (regnum & 0xffff), RTL839X_PHYREG_MMD_CTRL);
442
443 v = BIT(2) | BIT(0); // MMD-access | EXEC
444 sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
445
446 do {
447 v = sw_r32(RTL839X_PHYREG_ACCESS_CTRL);
448 } while (v & BIT(0));
449 // There is no error-checking via BIT 1 of v, as it does not seem to be set correctly
450 *val = (sw_r32(RTL839X_PHYREG_DATA_CTRL) & 0xffff);
451 pr_debug("%s: port %d, regnum: %x, val: %x (err %d)\n", __func__, port, regnum, *val, err);
452
453 mutex_unlock(&smi_lock);
454
455 return err;
456 }
457
458 /*
459 * Write to an mmd register of the PHY
460 */
461 int rtl839x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val)
462 {
463 int err = 0;
464 u32 v;
465
466 mutex_lock(&smi_lock);
467
468 // Set PHY to access
469 rtl839x_set_port_reg_le(BIT_ULL(port), RTL839X_PHYREG_PORT_CTRL);
470
471 // Set data to write
472 sw_w32_mask(0xffff << 16, val << 16, RTL839X_PHYREG_DATA_CTRL);
473
474 // Set MMD device number and register to write to
475 sw_w32(devnum << 16 | (regnum & 0xffff), RTL839X_PHYREG_MMD_CTRL);
476
477 v = BIT(3) | BIT(2) | BIT(0); // WRITE | MMD-access | EXEC
478 sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
479
480 do {
481 v = sw_r32(RTL839X_PHYREG_ACCESS_CTRL);
482 } while (v & BIT(0));
483
484 pr_debug("%s: port %d, regnum: %x, val: %x (err %d)\n", __func__, port, regnum, val, err);
485 mutex_unlock(&smi_lock);
486 return err;
487 }
488
489 void rtl8390_get_version(struct rtl838x_switch_priv *priv)
490 {
491 u32 info;
492
493 sw_w32_mask(0xf << 28, 0xa << 28, RTL839X_CHIP_INFO);
494 info = sw_r32(RTL839X_CHIP_INFO);
495 pr_debug("Chip-Info: %x\n", info);
496 priv->version = RTL8390_VERSION_A;
497 }
498
499 u32 rtl839x_hash(struct rtl838x_switch_priv *priv, u64 seed)
500 {
501 u32 h1, h2, h;
502
503 if (sw_r32(priv->r->l2_ctrl_0) & 1) {
504 h1 = (u32) (((seed >> 60) & 0x3f) ^ ((seed >> 54) & 0x3f)
505 ^ ((seed >> 36) & 0x3f) ^ ((seed >> 30) & 0x3f)
506 ^ ((seed >> 12) & 0x3f) ^ ((seed >> 6) & 0x3f));
507 h2 = (u32) (((seed >> 48) & 0x3f) ^ ((seed >> 42) & 0x3f)
508 ^ ((seed >> 24) & 0x3f) ^ ((seed >> 18) & 0x3f)
509 ^ (seed & 0x3f));
510 h = (h1 << 6) | h2;
511 } else {
512 h = (seed >> 60)
513 ^ ((((seed >> 48) & 0x3f) << 6) | ((seed >> 54) & 0x3f))
514 ^ ((seed >> 36) & 0xfff) ^ ((seed >> 24) & 0xfff)
515 ^ ((seed >> 12) & 0xfff) ^ (seed & 0xfff);
516 }
517
518 return h;
519 }
520
521 void rtl839x_vlan_profile_dump(int profile)
522 {
523 u32 p[2];
524
525 if (profile < 0 || profile > 7)
526 return;
527
528 p[0] = sw_r32(RTL839X_VLAN_PROFILE(profile));
529 p[1] = sw_r32(RTL839X_VLAN_PROFILE(profile) + 4);
530
531 pr_info("VLAN profile %d: L2 learning: %d, UNKN L2MC FLD PMSK %d, \
532 UNKN IPMC FLD PMSK %d, UNKN IPv6MC FLD PMSK: %d",
533 profile, p[1] & 1, (p[1] >> 1) & 0xfff, (p[1] >> 13) & 0xfff,
534 (p[0]) & 0xfff);
535 pr_info("VLAN profile %d: raw %08x, %08x\n", profile, p[0], p[1]);
536 }
537
538 static void rtl839x_stp_get(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])
539 {
540 int i;
541 u32 cmd = 1 << 16 /* Execute cmd */
542 | 0 << 15 /* Read */
543 | 5 << 12 /* Table type 0b101 */
544 | (msti & 0xfff);
545 priv->r->exec_tbl0_cmd(cmd);
546
547 for (i = 0; i < 4; i++)
548 port_state[i] = sw_r32(priv->r->tbl_access_data_0(i));
549 }
550
551 static void rtl839x_stp_set(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])
552 {
553 int i;
554 u32 cmd = 1 << 16 /* Execute cmd */
555 | 1 << 15 /* Write */
556 | 5 << 12 /* Table type 0b101 */
557 | (msti & 0xfff);
558 for (i = 0; i < 4; i++)
559 sw_w32(port_state[i], priv->r->tbl_access_data_0(i));
560 priv->r->exec_tbl0_cmd(cmd);
561 }
562
563 /*
564 * Enables or disables the EEE/EEEP capability of a port
565 */
566 void rtl839x_port_eee_set(struct rtl838x_switch_priv *priv, int port, bool enable)
567 {
568 u32 v;
569
570 // This works only for Ethernet ports, and on the RTL839X, ports above 47 are SFP
571 if (port >= 48)
572 return;
573
574 enable = true;
575 pr_debug("In %s: setting port %d to %d\n", __func__, port, enable);
576 v = enable ? 0xf : 0x0;
577
578 // Set EEE for 100, 500, 1000MBit and 10GBit
579 sw_w32_mask(0xf << 8, v << 8, rtl839x_mac_force_mode_ctrl(port));
580
581 // Set TX/RX EEE state
582 v = enable ? 0x3 : 0x0;
583 sw_w32(v, RTL839X_EEE_CTRL(port));
584
585 priv->ports[port].eee_enabled = enable;
586 }
587
588 /*
589 * Get EEE own capabilities and negotiation result
590 */
591 int rtl839x_eee_port_ability(struct rtl838x_switch_priv *priv, struct ethtool_eee *e, int port)
592 {
593 u64 link, a;
594
595 if (port >= 48)
596 return 0;
597
598 link = rtl839x_get_port_reg_le(RTL839X_MAC_LINK_STS);
599 if (!(link & BIT_ULL(port)))
600 return 0;
601
602 if (sw_r32(rtl839x_mac_force_mode_ctrl(port)) & BIT(8))
603 e->advertised |= ADVERTISED_100baseT_Full;
604
605 if (sw_r32(rtl839x_mac_force_mode_ctrl(port)) & BIT(10))
606 e->advertised |= ADVERTISED_1000baseT_Full;
607
608 a = rtl839x_get_port_reg_le(RTL839X_MAC_EEE_ABLTY);
609 pr_info("Link partner: %016llx\n", a);
610 if (rtl839x_get_port_reg_le(RTL839X_MAC_EEE_ABLTY) & BIT_ULL(port)) {
611 e->lp_advertised = ADVERTISED_100baseT_Full;
612 e->lp_advertised |= ADVERTISED_1000baseT_Full;
613 return 1;
614 }
615
616 return 0;
617 }
618
619 static void rtl839x_init_eee(struct rtl838x_switch_priv *priv, bool enable)
620 {
621 int i;
622
623 pr_info("Setting up EEE, state: %d\n", enable);
624
625 // Set wake timer for TX and pause timer both to 0x21
626 sw_w32_mask(0xff << 20| 0xff, 0x21 << 20| 0x21, RTL839X_EEE_TX_TIMER_GELITE_CTRL);
627 // Set pause wake timer for GIGA-EEE to 0x11
628 sw_w32_mask(0xff << 20, 0x11 << 20, RTL839X_EEE_TX_TIMER_GIGA_CTRL);
629 // Set pause wake timer for 10GBit ports to 0x11
630 sw_w32_mask(0xff << 20, 0x11 << 20, RTL839X_EEE_TX_TIMER_10G_CTRL);
631
632 // Setup EEE on all ports
633 for (i = 0; i < priv->cpu_port; i++) {
634 if (priv->ports[i].phy)
635 rtl839x_port_eee_set(priv, i, enable);
636 }
637 priv->eee_enabled = enable;
638 }
639
640 const struct rtl838x_reg rtl839x_reg = {
641 .mask_port_reg_be = rtl839x_mask_port_reg_be,
642 .set_port_reg_be = rtl839x_set_port_reg_be,
643 .get_port_reg_be = rtl839x_get_port_reg_be,
644 .mask_port_reg_le = rtl839x_mask_port_reg_le,
645 .set_port_reg_le = rtl839x_set_port_reg_le,
646 .get_port_reg_le = rtl839x_get_port_reg_le,
647 .stat_port_rst = RTL839X_STAT_PORT_RST,
648 .stat_rst = RTL839X_STAT_RST,
649 .stat_port_std_mib = RTL839X_STAT_PORT_STD_MIB,
650 .traffic_enable = rtl839x_traffic_enable,
651 .traffic_disable = rtl839x_traffic_disable,
652 .traffic_get = rtl839x_traffic_get,
653 .traffic_set = rtl839x_traffic_set,
654 .port_iso_ctrl = rtl839x_port_iso_ctrl,
655 .l2_ctrl_0 = RTL839X_L2_CTRL_0,
656 .l2_ctrl_1 = RTL839X_L2_CTRL_1,
657 .l2_port_aging_out = RTL839X_L2_PORT_AGING_OUT,
658 .smi_poll_ctrl = RTL839X_SMI_PORT_POLLING_CTRL,
659 .l2_tbl_flush_ctrl = RTL839X_L2_TBL_FLUSH_CTRL,
660 .exec_tbl0_cmd = rtl839x_exec_tbl0_cmd,
661 .exec_tbl1_cmd = rtl839x_exec_tbl1_cmd,
662 .tbl_access_data_0 = rtl839x_tbl_access_data_0,
663 .isr_glb_src = RTL839X_ISR_GLB_SRC,
664 .isr_port_link_sts_chg = RTL839X_ISR_PORT_LINK_STS_CHG,
665 .imr_port_link_sts_chg = RTL839X_IMR_PORT_LINK_STS_CHG,
666 .imr_glb = RTL839X_IMR_GLB,
667 .vlan_tables_read = rtl839x_vlan_tables_read,
668 .vlan_set_tagged = rtl839x_vlan_set_tagged,
669 .vlan_set_untagged = rtl839x_vlan_set_untagged,
670 .vlan_profile_dump = rtl839x_vlan_profile_dump,
671 .vlan_profile_setup = rtl839x_vlan_profile_setup,
672 .stp_get = rtl839x_stp_get,
673 .stp_set = rtl839x_stp_set,
674 .mac_force_mode_ctrl = rtl839x_mac_force_mode_ctrl,
675 .mac_port_ctrl = rtl839x_mac_port_ctrl,
676 .l2_port_new_salrn = rtl839x_l2_port_new_salrn,
677 .l2_port_new_sa_fwd = rtl839x_l2_port_new_sa_fwd,
678 .mir_ctrl = RTL839X_MIR_CTRL,
679 .mir_dpm = RTL839X_MIR_DPM_CTRL,
680 .mir_spm = RTL839X_MIR_SPM_CTRL,
681 .mac_link_sts = RTL839X_MAC_LINK_STS,
682 .mac_link_dup_sts = RTL839X_MAC_LINK_DUP_STS,
683 .mac_link_spd_sts = rtl839x_mac_link_spd_sts,
684 .mac_rx_pause_sts = RTL839X_MAC_RX_PAUSE_STS,
685 .mac_tx_pause_sts = RTL839X_MAC_TX_PAUSE_STS,
686 .read_l2_entry_using_hash = rtl839x_read_l2_entry_using_hash,
687 .read_cam = rtl839x_read_cam,
688 .vlan_port_egr_filter = RTL839X_VLAN_PORT_EGR_FLTR(0),
689 .vlan_port_igr_filter = RTL839X_VLAN_PORT_IGR_FLTR(0),
690 .vlan_port_pb = RTL839X_VLAN_PORT_PB_VLAN,
691 .vlan_port_tag_sts_ctrl = RTL839X_VLAN_PORT_TAG_STS_CTRL,
692 .trk_mbr_ctr = rtl839x_trk_mbr_ctr,
693 .rma_bpdu_fld_pmask = RTL839X_RMA_BPDU_FLD_PMSK,
694 .spcl_trap_eapol_ctrl = RTL839X_SPCL_TRAP_EAPOL_CTRL,
695 .init_eee = rtl839x_init_eee,
696 .port_eee_set = rtl839x_port_eee_set,
697 .eee_port_ability = rtl839x_eee_port_ability,
698 .read_mcast_pmask = rtl839x_read_mcast_pmask,
699 .write_mcast_pmask = rtl839x_write_mcast_pmask,
700 };
Staging tree of Jo-Philipp Wich