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realtek: update the tree to the latest refactored version
[openwrt/staging/ynezz.git] / target / linux / realtek / files-5.4 / drivers / net / dsa / rtl83xx / rtl839x.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <asm/mach-rtl838x/mach-rtl83xx.h>
4 #include "rtl83xx.h"
5
6 extern struct mutex smi_lock;
7
8
9 static inline void rtl839x_mask_port_reg_be(u64 clear, u64 set, int reg)
10 {
11 sw_w32_mask((u32)(clear >> 32), (u32)(set >> 32), reg);
12 sw_w32_mask((u32)(clear & 0xffffffff), (u32)(set & 0xffffffff), reg + 4);
13 }
14
15 static inline u64 rtl839x_get_port_reg_be(int reg)
16 {
17 u64 v = sw_r32(reg);
18
19 v <<= 32;
20 v |= sw_r32(reg + 4);
21 return v;
22 }
23
24 static inline void rtl839x_set_port_reg_be(u64 set, int reg)
25 {
26 sw_w32(set >> 32, reg);
27 sw_w32(set & 0xffffffff, reg + 4);
28 }
29
30 static inline void rtl839x_mask_port_reg_le(u64 clear, u64 set, int reg)
31 {
32 sw_w32_mask((u32)clear, (u32)set, reg);
33 sw_w32_mask((u32)(clear >> 32), (u32)(set >> 32), reg + 4);
34 }
35
36 static inline void rtl839x_set_port_reg_le(u64 set, int reg)
37 {
38 sw_w32(set, reg);
39 sw_w32(set >> 32, reg + 4);
40 }
41
42 static inline u64 rtl839x_get_port_reg_le(int reg)
43 {
44 u64 v = sw_r32(reg + 4);
45
46 v <<= 32;
47 v |= sw_r32(reg);
48 return v;
49 }
50
51 static inline int rtl839x_stat_port_std_mib(int p)
52 {
53 return RTL839X_STAT_PORT_STD_MIB + (p << 8);
54 }
55
56 static inline int rtl839x_port_iso_ctrl(int p)
57 {
58 return RTL839X_PORT_ISO_CTRL(p);
59 }
60
61 static inline void rtl839x_exec_tbl0_cmd(u32 cmd)
62 {
63 sw_w32(cmd, RTL839X_TBL_ACCESS_CTRL_0);
64 do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_0) & BIT(16));
65 }
66
67 static inline void rtl839x_exec_tbl1_cmd(u32 cmd)
68 {
69 sw_w32(cmd, RTL839X_TBL_ACCESS_CTRL_1);
70 do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_1) & BIT(16));
71 }
72
73 static inline int rtl839x_tbl_access_data_0(int i)
74 {
75 return RTL839X_TBL_ACCESS_DATA_0(i);
76 }
77
78 static void rtl839x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info)
79 {
80 u32 cmd;
81 u64 v;
82 u32 u, w;
83
84 cmd = BIT(16) /* Execute cmd */
85 | 0 << 15 /* Read */
86 | 0 << 12 /* Table type 0b000 */
87 | (vlan & 0xfff);
88 rtl839x_exec_tbl0_cmd(cmd);
89
90 v = sw_r32(RTL838X_TBL_ACCESS_DATA_0(0));
91 v <<= 32;
92 u = sw_r32(RTL838X_TBL_ACCESS_DATA_0(1));
93 v |= u;
94 info->tagged_ports = v >> 11;
95
96 w = sw_r32(RTL838X_TBL_ACCESS_DATA_0(2));
97
98 info->profile_id = w >> 30 | ((u & 1) << 2);
99 info->hash_mc_fid = !!(u & 2);
100 info->hash_uc_fid = !!(u & 4);
101 info->fid = (u >> 3) & 0xff;
102
103 cmd = BIT(16) /* Execute cmd */
104 | 0 << 15 /* Read */
105 | 0 << 12 /* Table type 0b000 */
106 | (vlan & 0xfff);
107 rtl839x_exec_tbl1_cmd(cmd);
108 v = sw_r32(RTL838X_TBL_ACCESS_DATA_1(0));
109 v <<= 32;
110 v |= sw_r32(RTL838X_TBL_ACCESS_DATA_1(1));
111 info->untagged_ports = v >> 11;
112 }
113
114 static void rtl839x_vlan_set_tagged(u32 vlan, struct rtl838x_vlan_info *info)
115 {
116 u32 cmd = BIT(16) /* Execute cmd */
117 | BIT(15) /* Write */
118 | 0 << 12 /* Table type 0b00 */
119 | (vlan & 0xfff);
120 u32 w;
121 u64 v = info->tagged_ports << 11;
122
123 v |= info->profile_id >> 2;
124 v |= info->hash_mc_fid ? 2 : 0;
125 v |= info->hash_uc_fid ? 4 : 0;
126 v |= ((u32)info->fid) << 3;
127 rtl839x_set_port_reg_be(v, RTL838X_TBL_ACCESS_DATA_0(0));
128
129 w = info->profile_id;
130 sw_w32(w << 30, RTL838X_TBL_ACCESS_DATA_0(2));
131 rtl839x_exec_tbl0_cmd(cmd);
132 }
133
134 static void rtl839x_vlan_set_untagged(u32 vlan, u64 portmask)
135 {
136 u32 cmd = BIT(16) /* Execute cmd */
137 | BIT(15) /* Write */
138 | 0 << 12 /* Table type 0b00 */
139 | (vlan & 0xfff);
140 rtl839x_set_port_reg_be(portmask << 11, RTL838X_TBL_ACCESS_DATA_1(0));
141 rtl839x_exec_tbl1_cmd(cmd);
142 }
143
144 static inline int rtl839x_mac_force_mode_ctrl(int p)
145 {
146 return RTL839X_MAC_FORCE_MODE_CTRL + (p << 2);
147 }
148
149 static inline int rtl839x_mac_port_ctrl(int p)
150 {
151 return RTL839X_MAC_PORT_CTRL(p);
152 }
153
154 static inline int rtl839x_l2_port_new_salrn(int p)
155 {
156 return RTL839X_L2_PORT_NEW_SALRN(p);
157 }
158
159 static inline int rtl839x_l2_port_new_sa_fwd(int p)
160 {
161 return RTL839X_L2_PORT_NEW_SA_FWD(p);
162 }
163
164 static inline int rtl839x_mir_ctrl(int group)
165 {
166 return RTL839X_MIR_CTRL(group);
167 }
168
169 static inline int rtl839x_mir_dpm(int group)
170 {
171 return RTL839X_MIR_DPM_CTRL(group);
172 }
173
174 static inline int rtl839x_mir_spm(int group)
175 {
176 return RTL839X_MIR_SPM_CTRL(group);
177 }
178
179 static inline int rtl839x_mac_link_spd_sts(int p)
180 {
181 return RTL839X_MAC_LINK_SPD_STS(p);
182 }
183
184 static u64 rtl839x_read_l2_entry_using_hash(u32 hash, u32 position, struct rtl838x_l2_entry *e)
185 {
186 u64 entry;
187 u32 r[3];
188
189 /* Search in SRAM, with hash and at position in hash bucket (0-3) */
190 u32 idx = (0 << 14) | (hash << 2) | position;
191
192 u32 cmd = BIT(17) /* Execute cmd */
193 | 0 << 16 /* Read */
194 | 0 << 14 /* Table type 0b00 */
195 | (idx & 0x3fff);
196
197 sw_w32(cmd, RTL839X_TBL_ACCESS_L2_CTRL);
198 do { } while (sw_r32(RTL839X_TBL_ACCESS_L2_CTRL) & BIT(17));
199 r[0] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(0));
200 r[1] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(1));
201 r[2] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(2));
202
203 /* Table contains different entry types, we need to identify the right one:
204 * Check for MC entries, first
205 */
206 e->is_ip_mc = !!(r[2] & BIT(31));
207 e->is_ipv6_mc = !!(r[2] & BIT(30));
208 e->type = L2_INVALID;
209 if (!e->is_ip_mc) {
210 e->mac[0] = (r[0] >> 12);
211 e->mac[1] = (r[0] >> 4);
212 e->mac[2] = ((r[1] >> 28) | (r[0] << 4));
213 e->mac[3] = (r[1] >> 20);
214 e->mac[4] = (r[1] >> 12);
215 e->mac[5] = (r[1] >> 4);
216
217 /* Is it a unicast entry? check multicast bit */
218 if (!(e->mac[0] & 1)) {
219 e->is_static = !!((r[2] >> 18) & 1);
220 e->vid = (r[2] >> 4) & 0xfff;
221 e->rvid = (r[0] >> 20) & 0xfff;
222 e->port = (r[2] >> 24) & 0x3f;
223 e->block_da = !!(r[2] & BIT(19));
224 e->block_sa = !!(r[2] & BIT(20));
225 e->suspended = !!(r[2] & BIT(17));
226 e->next_hop = !!(r[2] & BIT(16));
227 if (e->next_hop)
228 pr_debug("Found next hop entry, need to read data\n");
229 e->age = (r[2] >> 21) & 3;
230 e->valid = true;
231 if (!(r[2] & 0xc0fd0000)) /* Check for valid entry */
232 e->valid = false;
233 else
234 e->type = L2_UNICAST;
235 } else {
236 e->valid = true;
237 e->type = L2_MULTICAST;
238 e->mc_portmask_index = (r[2]>>6) & 0xfff;
239 }
240 }
241 if (e->is_ip_mc) {
242 e->valid = true;
243 e->type = IP4_MULTICAST;
244 }
245 if (e->is_ipv6_mc) {
246 e->valid = true;
247 e->type = IP6_MULTICAST;
248 }
249
250 entry = (((u64) r[0]) << 12) | ((r[1] & 0xfffffff0) << 12) | ((r[2] >> 4) & 0xfff);
251 return entry;
252 }
253
254 static u64 rtl839x_read_cam(int idx, struct rtl838x_l2_entry *e)
255 {
256 u64 entry;
257 u32 r[3];
258
259 u32 cmd = BIT(17) /* Execute cmd */
260 | 0 << 16 /* Read */
261 | BIT(14) /* Table type 0b01 */
262 | (idx & 0x3f);
263 sw_w32(cmd, RTL839X_TBL_ACCESS_L2_CTRL);
264 do { } while (sw_r32(RTL839X_TBL_ACCESS_L2_CTRL) & BIT(17));
265 r[0] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(0));
266 r[1] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(1));
267 r[2] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(2));
268
269 e->mac[0] = (r[0] >> 12);
270 e->mac[1] = (r[0] >> 4);
271 e->mac[2] = ((r[1] >> 28) | (r[0] << 4));
272 e->mac[3] = (r[1] >> 20);
273 e->mac[4] = (r[1] >> 12);
274 e->mac[5] = (r[1] >> 4);
275 e->is_static = !!((r[2] >> 18) & 1);
276 e->vid = (r[2] >> 4) & 0xfff;
277 e->rvid = (r[0] >> 20) & 0xfff;
278 e->port = (r[2] >> 24) & 0x3f;
279
280 e->valid = true;
281 if (!(r[2] & 0x10fd0000)) /* Check for invalid entry */
282 e->valid = false;
283
284 if (e->valid)
285 pr_debug("Found in CAM: R1 %x R2 %x R3 %x\n", r[0], r[1], r[2]);
286
287 entry = (((u64) r[0]) << 12) | ((r[1] & 0xfffffff0) << 12) | ((r[2] >> 4) & 0xfff);
288 return entry;
289 }
290
291 static inline int rtl839x_vlan_profile(int profile)
292 {
293 return RTL839X_VLAN_PROFILE(profile);
294 }
295
296 static inline int rtl839x_vlan_port_egr_filter(int port)
297 {
298 return RTL839X_VLAN_PORT_EGR_FLTR(port);
299 }
300
301 static inline int rtl839x_vlan_port_igr_filter(int port)
302 {
303 return RTL839X_VLAN_PORT_IGR_FLTR(port);
304 }
305
306 static inline int rtl839x_vlan_port_pb(int port)
307 {
308 return RTL839X_VLAN_PORT_PB_VLAN(port);
309 }
310
311 static inline int rtl839x_vlan_port_tag_sts_ctrl(int port)
312 {
313 return RTL839X_VLAN_PORT_TAG_STS_CTRL(port);
314 }
315
316 const struct rtl838x_reg rtl839x_reg = {
317 .mask_port_reg_be = rtl839x_mask_port_reg_be,
318 .set_port_reg_be = rtl839x_set_port_reg_be,
319 .get_port_reg_be = rtl839x_get_port_reg_be,
320 .mask_port_reg_le = rtl839x_mask_port_reg_le,
321 .set_port_reg_le = rtl839x_set_port_reg_le,
322 .get_port_reg_le = rtl839x_get_port_reg_le,
323 .stat_port_rst = RTL839X_STAT_PORT_RST,
324 .stat_rst = RTL839X_STAT_RST,
325 .stat_port_std_mib = rtl839x_stat_port_std_mib,
326 .port_iso_ctrl = rtl839x_port_iso_ctrl,
327 .l2_ctrl_0 = RTL839X_L2_CTRL_0,
328 .l2_ctrl_1 = RTL839X_L2_CTRL_1,
329 .l2_port_aging_out = RTL839X_L2_PORT_AGING_OUT,
330 .smi_poll_ctrl = RTL839X_SMI_PORT_POLLING_CTRL,
331 .l2_tbl_flush_ctrl = RTL839X_L2_TBL_FLUSH_CTRL,
332 .exec_tbl0_cmd = rtl839x_exec_tbl0_cmd,
333 .exec_tbl1_cmd = rtl839x_exec_tbl1_cmd,
334 .tbl_access_data_0 = rtl839x_tbl_access_data_0,
335 .isr_glb_src = RTL839X_ISR_GLB_SRC,
336 .isr_port_link_sts_chg = RTL839X_ISR_PORT_LINK_STS_CHG,
337 .imr_port_link_sts_chg = RTL839X_IMR_PORT_LINK_STS_CHG,
338 .imr_glb = RTL839X_IMR_GLB,
339 .vlan_tables_read = rtl839x_vlan_tables_read,
340 .vlan_set_tagged = rtl839x_vlan_set_tagged,
341 .vlan_set_untagged = rtl839x_vlan_set_untagged,
342 .mac_force_mode_ctrl = rtl839x_mac_force_mode_ctrl,
343 .mac_port_ctrl = rtl839x_mac_port_ctrl,
344 .l2_port_new_salrn = rtl839x_l2_port_new_salrn,
345 .l2_port_new_sa_fwd = rtl839x_l2_port_new_sa_fwd,
346 .mir_ctrl = rtl839x_mir_ctrl,
347 .mir_dpm = rtl839x_mir_dpm,
348 .mir_spm = rtl839x_mir_spm,
349 .mac_link_sts = RTL839X_MAC_LINK_STS,
350 .mac_link_dup_sts = RTL839X_MAC_LINK_DUP_STS,
351 .mac_link_spd_sts = rtl839x_mac_link_spd_sts,
352 .mac_rx_pause_sts = RTL839X_MAC_RX_PAUSE_STS,
353 .mac_tx_pause_sts = RTL839X_MAC_TX_PAUSE_STS,
354 .read_l2_entry_using_hash = rtl839x_read_l2_entry_using_hash,
355 .read_cam = rtl839x_read_cam,
356 .vlan_profile = rtl839x_vlan_profile,
357 .vlan_port_egr_filter = rtl839x_vlan_port_egr_filter,
358 .vlan_port_igr_filter = rtl839x_vlan_port_igr_filter,
359 .vlan_port_pb = rtl839x_vlan_port_pb,
360 .vlan_port_tag_sts_ctrl = rtl839x_vlan_port_tag_sts_ctrl,
361 };
362
363 irqreturn_t rtl839x_switch_irq(int irq, void *dev_id)
364 {
365 struct dsa_switch *ds = dev_id;
366 u32 status = sw_r32(RTL839X_ISR_GLB_SRC);
367 u64 ports = rtl839x_get_port_reg_le(RTL839X_ISR_PORT_LINK_STS_CHG);
368 u64 link;
369 int i;
370
371 /* Clear status */
372 rtl839x_set_port_reg_le(ports, RTL839X_ISR_PORT_LINK_STS_CHG);
373 pr_debug("RTL8390 Link change: status: %x, ports %llx\n", status, ports);
374
375 for (i = 0; i < 52; i++) {
376 if (ports & (1ULL << i)) {
377 link = rtl839x_get_port_reg_le(RTL839X_MAC_LINK_STS);
378 if (link & (1ULL << i))
379 dsa_port_phylink_mac_change(ds, i, true);
380 else
381 dsa_port_phylink_mac_change(ds, i, false);
382 }
383 }
384 return IRQ_HANDLED;
385 }
386
387 // TODO: unused
388 int rtl8390_sds_power(int mac, int val)
389 {
390 u32 offset = (mac == 48) ? 0x0 : 0x100;
391 u32 mode = val ? 0 : 1;
392
393 pr_debug("In %s: mac %d, set %d\n", __func__, mac, val);
394
395 if ((mac != 48) && (mac != 49)) {
396 pr_err("%s: not an SFP port: %d\n", __func__, mac);
397 return -1;
398 }
399
400 // Set bit 1003. 1000 starts at 7c
401 sw_w32_mask(BIT(11), mode << 11, RTL839X_SDS12_13_PWR0 + offset);
402
403 return 0;
404 }
405
406 int rtl839x_read_phy(u32 port, u32 page, u32 reg, u32 *val)
407 {
408 u32 v;
409
410 if (port > 63 || page > 4095 || reg > 31)
411 return -ENOTSUPP;
412
413 mutex_lock(&smi_lock);
414
415 sw_w32_mask(0xffff0000, port << 16, RTL839X_PHYREG_DATA_CTRL);
416 v = reg << 5 | page << 10 | ((page == 0x1fff) ? 0x1f : 0) << 23;
417 sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
418
419 sw_w32(0x1ff, RTL839X_PHYREG_CTRL);
420
421 v |= 1;
422 sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
423
424 do {
425 } while (sw_r32(RTL839X_PHYREG_ACCESS_CTRL) & 0x1);
426
427 *val = sw_r32(RTL839X_PHYREG_DATA_CTRL) & 0xffff;
428
429 mutex_unlock(&smi_lock);
430 return 0;
431 }
432
433 int rtl839x_write_phy(u32 port, u32 page, u32 reg, u32 val)
434 {
435 u32 v;
436 int err = 0;
437
438 val &= 0xffff;
439 if (port > 63 || page > 4095 || reg > 31)
440 return -ENOTSUPP;
441
442 mutex_lock(&smi_lock);
443 /* Clear both port registers */
444 sw_w32(0, RTL839X_PHYREG_PORT_CTRL(0));
445 sw_w32(0, RTL839X_PHYREG_PORT_CTRL(0) + 4);
446 sw_w32_mask(0, BIT(port), RTL839X_PHYREG_PORT_CTRL(port));
447
448 sw_w32_mask(0xffff0000, val << 16, RTL839X_PHYREG_DATA_CTRL);
449
450 v = reg << 5 | page << 10 | ((page == 0x1fff) ? 0x1f : 0) << 23;
451 sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
452
453 sw_w32(0x1ff, RTL839X_PHYREG_CTRL);
454
455 v |= BIT(3) | 1; /* Write operation and execute */
456 sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
457
458 do {
459 } while (sw_r32(RTL839X_PHYREG_ACCESS_CTRL) & 0x1);
460
461 if (sw_r32(RTL839X_PHYREG_ACCESS_CTRL) & 0x2)
462 err = -EIO;
463
464 mutex_unlock(&smi_lock);
465 return err;
466 }
467
468 void rtl8390_get_version(struct rtl838x_switch_priv *priv)
469 {
470 u32 info;
471
472 sw_w32_mask(0xf << 28, 0xa << 28, RTL839X_CHIP_INFO);
473 info = sw_r32(RTL839X_CHIP_INFO);
474 pr_debug("Chip-Info: %x\n", info);
475 priv->version = RTL8390_VERSION_A;
476 }
477
478 u32 rtl839x_hash(struct rtl838x_switch_priv *priv, u64 seed)
479 {
480 u32 h1, h2, h;
481
482 if (sw_r32(priv->r->l2_ctrl_0) & 1) {
483 h1 = (u32) (((seed >> 60) & 0x3f) ^ ((seed >> 54) & 0x3f)
484 ^ ((seed >> 36) & 0x3f) ^ ((seed >> 30) & 0x3f)
485 ^ ((seed >> 12) & 0x3f) ^ ((seed >> 6) & 0x3f));
486 h2 = (u32) (((seed >> 48) & 0x3f) ^ ((seed >> 42) & 0x3f)
487 ^ ((seed >> 24) & 0x3f) ^ ((seed >> 18) & 0x3f)
488 ^ (seed & 0x3f));
489 h = (h1 << 6) | h2;
490 } else {
491 h = (seed >> 60)
492 ^ ((((seed >> 48) & 0x3f) << 6) | ((seed >> 54) & 0x3f))
493 ^ ((seed >> 36) & 0xfff) ^ ((seed >> 24) & 0xfff)
494 ^ ((seed >> 12) & 0xfff) ^ (seed & 0xfff);
495 }
496
497 return h;
498 }
499
500 void rtl839x_vlan_profile_dump(int index)
501 {
502 u32 profile, profile1;
503
504 if (index < 0 || index > 7)
505 return;
506
507 profile1 = sw_r32(RTL839X_VLAN_PROFILE(index) + 4);
508 profile = sw_r32(RTL839X_VLAN_PROFILE(index));
509
510 pr_debug("VLAN %d: L2 learning: %d, L2 Unknown MultiCast Field %x, \
511 IPv4 Unknown MultiCast Field %x, IPv6 Unknown MultiCast Field: %x",
512 index, profile & 1, (profile >> 1) & 0xfff, (profile >> 13) & 0xfff,
513 (profile1) & 0xfff);
514 }
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