1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/drivers/net/ethernet/rtl838x_eth.c
4 * Copyright (C) 2020 B. Koblitz
7 #include <linux/dma-mapping.h>
8 #include <linux/etherdevice.h>
9 #include <linux/interrupt.h>
11 #include <linux/platform_device.h>
12 #include <linux/sched.h>
13 #include <linux/slab.h>
15 #include <linux/of_net.h>
16 #include <linux/of_mdio.h>
17 #include <linux/module.h>
18 #include <linux/phylink.h>
19 #include <linux/pkt_sched.h>
21 #include <net/switchdev.h>
22 #include <asm/cacheflush.h>
24 #include <asm/mach-rtl838x/mach-rtl83xx.h>
25 #include "rtl838x_eth.h"
27 extern struct rtl83xx_soc_info soc_info
;
30 * Maximum number of RX rings is 8 on RTL83XX and 32 on the 93XX
31 * The ring is assigned by switch based on packet/port priortity
32 * Maximum number of TX rings is 2, Ring 2 being the high priority
33 * ring on the RTL93xx SoCs. MAX_RING_SIZE * RING_BUFFER gives
34 * the memory used for the ring buffer.
36 #define MAX_RXRINGS 32
38 #define MAX_ENTRIES (200 * 8)
40 // BUG: TXRINGLEN can be 160
42 #define NOTIFY_EVENTS 10
43 #define NOTIFY_BLOCKS 10
46 #define TX_EN_93XX 0x20
47 #define RX_EN_93XX 0x10
51 #define RING_BUFFER 1600
53 #define RTL838X_STORM_CTRL_PORT_BC_EXCEED (0x470C)
54 #define RTL838X_STORM_CTRL_PORT_MC_EXCEED (0x4710)
55 #define RTL838X_STORM_CTRL_PORT_UC_EXCEED (0x4714)
56 #define RTL838X_ATK_PRVNT_STS (0x5B1C)
61 uint16_t size
; /* buffer size */
63 uint16_t len
; /* pkt len */
65 } __packed
__aligned(1);
74 } __packed
__aligned(1);
77 uint32_t rx_r
[MAX_RXRINGS
][MAX_RXLEN
];
78 uint32_t tx_r
[TXRINGS
][TXRINGLEN
];
79 struct p_hdr rx_header
[MAX_RXRINGS
][MAX_RXLEN
];
80 struct p_hdr tx_header
[TXRINGS
][TXRINGLEN
];
81 uint32_t c_rx
[MAX_RXRINGS
];
82 uint32_t c_tx
[TXRINGS
];
83 uint8_t tx_space
[TXRINGS
* TXRINGLEN
* RING_BUFFER
];
88 struct n_event events
[NOTIFY_EVENTS
];
92 struct notify_block blocks
[NOTIFY_BLOCKS
];
94 u32 ring
[NOTIFY_BLOCKS
];
98 void rtl838x_create_tx_header(struct p_hdr
*h
, int dest_port
, int prio
)
103 // cpu_tag[0] is reserved on the RTL83XX SoCs
104 h
->cpu_tag
[1] = 0x0400;
105 h
->cpu_tag
[2] = 0x0200;
106 h
->cpu_tag
[3] = 0x0000;
107 h
->cpu_tag
[4] = BIT(dest_port
) >> 16;
108 h
->cpu_tag
[5] = BIT(dest_port
) & 0xffff;
109 // Set internal priority and AS_PRIO
111 h
->cpu_tag
[2] |= (prio
| 0x8) << 12;
115 void rtl839x_create_tx_header(struct p_hdr
*h
, int dest_port
, int prio
)
120 // cpu_tag[0] is reserved on the RTL83XX SoCs
121 h
->cpu_tag
[1] = 0x0100;
122 h
->cpu_tag
[2] = h
->cpu_tag
[3] = h
->cpu_tag
[4] = h
->cpu_tag
[5] = 0;
123 if (dest_port
>= 32) {
125 h
->cpu_tag
[2] = BIT(dest_port
) >> 16;
126 h
->cpu_tag
[3] = BIT(dest_port
) & 0xffff;
128 h
->cpu_tag
[4] = BIT(dest_port
) >> 16;
129 h
->cpu_tag
[5] = BIT(dest_port
) & 0xffff;
131 h
->cpu_tag
[6] |= BIT(21); // Enable destination port mask use
132 // Set internal priority and AS_PRIO
134 h
->cpu_tag
[1] |= prio
| BIT(3);
138 void rtl930x_create_tx_header(struct p_hdr
*h
, int dest_port
, int prio
)
140 h
->cpu_tag
[0] = 0x8000;
141 h
->cpu_tag
[1] = 0; // TODO: Fill port and prio
147 h
->cpu_tag
[7] = 0xffff;
150 void rtl931x_create_tx_header(struct p_hdr
*h
, int dest_port
, int prio
)
152 h
->cpu_tag
[0] = 0x8000;
153 h
->cpu_tag
[1] = 0; // TODO: Fill port and prio
159 h
->cpu_tag
[7] = 0xffff;
162 struct rtl838x_rx_q
{
164 struct rtl838x_eth_priv
*priv
;
165 struct napi_struct napi
;
168 struct rtl838x_eth_priv
{
169 struct net_device
*netdev
;
170 struct platform_device
*pdev
;
173 struct mii_bus
*mii_bus
;
174 struct rtl838x_rx_q rx_qs
[MAX_RXRINGS
];
175 struct phylink
*phylink
;
176 struct phylink_config phylink_config
;
179 const struct rtl838x_reg
*r
;
186 extern int rtl838x_phy_init(struct rtl838x_eth_priv
*priv
);
187 extern int rtl838x_read_sds_phy(int phy_addr
, int phy_reg
);
188 extern int rtl839x_read_sds_phy(int phy_addr
, int phy_reg
);
189 extern int rtl839x_write_sds_phy(int phy_addr
, int phy_reg
, u16 v
);
190 extern int rtl930x_read_sds_phy(int phy_addr
, int page
, int phy_reg
);
191 extern int rtl930x_write_sds_phy(int phy_addr
, int page
, int phy_reg
, u16 v
);
192 extern int rtl930x_read_mmd_phy(u32 port
, u32 devnum
, u32 regnum
, u32
*val
);
193 extern int rtl930x_write_mmd_phy(u32 port
, u32 devnum
, u32 regnum
, u32 val
);
196 * On the RTL93XX, the RTL93XX_DMA_IF_RX_RING_CNTR track the fill level of
197 * the rings. Writing x into these registers substracts x from its content.
198 * When the content reaches the ring size, the ASIC no longer adds
199 * packets to this receive queue.
201 void rtl838x_update_cntr(int r
, int released
)
203 // This feature is not available on RTL838x SoCs
206 void rtl839x_update_cntr(int r
, int released
)
208 // This feature is not available on RTL839x SoCs
211 void rtl930x_update_cntr(int r
, int released
)
213 int pos
= (r
% 3) * 10;
214 u32 reg
= RTL930X_DMA_IF_RX_RING_CNTR
+ ((r
/ 3) << 2);
217 v
= (v
>> pos
) & 0x3ff;
218 pr_debug("RX: Work done %d, old value: %d, pos %d, reg %04x\n", released
, v
, pos
, reg
);
219 sw_w32_mask(0x3ff << pos
, released
<< pos
, reg
);
223 void rtl931x_update_cntr(int r
, int released
)
225 int pos
= (r
% 3) * 10;
226 u32 reg
= RTL931X_DMA_IF_RX_RING_CNTR
+ ((r
/ 3) << 2);
228 sw_w32_mask(0x3ff << pos
, released
<< pos
, reg
);
240 bool rtl838x_decode_tag(struct p_hdr
*h
, struct dsa_tag
*t
)
242 t
->reason
= h
->cpu_tag
[3] & 0xf;
243 t
->queue
= (h
->cpu_tag
[0] & 0xe0) >> 5;
244 t
->port
= h
->cpu_tag
[1] & 0x1f;
245 t
->crc_error
= t
->reason
== 13;
247 pr_debug("Reason: %d\n", t
->reason
);
248 if (t
->reason
!= 4) // NIC_RX_REASON_SPECIAL_TRAP
253 return t
->l2_offloaded
;
256 bool rtl839x_decode_tag(struct p_hdr
*h
, struct dsa_tag
*t
)
258 t
->reason
= h
->cpu_tag
[4] & 0x1f;
259 t
->queue
= (h
->cpu_tag
[3] & 0xe000) >> 13;
260 t
->port
= h
->cpu_tag
[1] & 0x3f;
261 t
->crc_error
= h
->cpu_tag
[3] & BIT(2);
263 pr_debug("Reason: %d\n", t
->reason
);
264 if ((t
->reason
!= 7) && (t
->reason
!= 8)) // NIC_RX_REASON_RMA_USR
269 return t
->l2_offloaded
;
272 bool rtl930x_decode_tag(struct p_hdr
*h
, struct dsa_tag
*t
)
274 t
->reason
= h
->cpu_tag
[7] & 0x3f;
275 t
->queue
= (h
->cpu_tag
[2] >> 11) & 0x1f;
276 t
->port
= (h
->cpu_tag
[0] >> 8) & 0x1f;
277 t
->crc_error
= h
->cpu_tag
[1] & BIT(6);
279 pr_debug("Reason %d, port %d, queue %d\n", t
->reason
, t
->port
, t
->queue
);
280 if (t
->reason
>= 19 && t
->reason
<= 27)
285 return t
->l2_offloaded
;
288 bool rtl931x_decode_tag(struct p_hdr
*h
, struct dsa_tag
*t
)
290 t
->reason
= h
->cpu_tag
[7] & 0x3f;
291 t
->queue
= (h
->cpu_tag
[2] >> 11) & 0x1f;
292 t
->port
= (h
->cpu_tag
[0] >> 8) & 0x3f;
293 t
->crc_error
= h
->cpu_tag
[1] & BIT(6);
295 pr_debug("Reason %d, port %d, queue %d\n", t
->reason
, t
->port
, t
->queue
);
296 if (t
->reason
>= 19 && t
->reason
<= 27)
301 return t
->l2_offloaded
;
305 * Discard the RX ring-buffers, called as part of the net-ISR
306 * when the buffer runs over
307 * Caller needs to hold priv->lock
309 static void rtl838x_rb_cleanup(struct rtl838x_eth_priv
*priv
, int status
)
314 struct ring_b
*ring
= priv
->membase
;
316 for (r
= 0; r
< priv
->rxrings
; r
++) {
317 pr_debug("In %s working on r: %d\n", __func__
, r
);
318 last
= (u32
*)KSEG1ADDR(sw_r32(priv
->r
->dma_if_rx_cur
+ r
* 4));
320 if ((ring
->rx_r
[r
][ring
->c_rx
[r
]] & 0x1))
322 pr_debug("Got something: %d\n", ring
->c_rx
[r
]);
323 h
= &ring
->rx_header
[r
][ring
->c_rx
[r
]];
324 memset(h
, 0, sizeof(struct p_hdr
));
325 h
->buf
= (u8
*)KSEG1ADDR(ring
->rx_space
326 + r
* priv
->rxringlen
* RING_BUFFER
327 + ring
->c_rx
[r
] * RING_BUFFER
);
328 h
->size
= RING_BUFFER
;
329 /* make sure the header is visible to the ASIC */
332 ring
->rx_r
[r
][ring
->c_rx
[r
]] = KSEG1ADDR(h
) | 0x1
333 | (ring
->c_rx
[r
] == (priv
->rxringlen
- 1) ? WRAP
: 0x1);
334 ring
->c_rx
[r
] = (ring
->c_rx
[r
] + 1) % priv
->rxringlen
;
335 } while (&ring
->rx_r
[r
][ring
->c_rx
[r
]] != last
);
339 struct fdb_update_work
{
340 struct work_struct work
;
341 struct net_device
*ndev
;
342 u64 macs
[NOTIFY_EVENTS
+ 1];
345 void rtl838x_fdb_sync(struct work_struct
*work
)
347 const struct fdb_update_work
*uw
=
348 container_of(work
, struct fdb_update_work
, work
);
349 struct switchdev_notifier_fdb_info info
;
354 while (uw
->macs
[i
]) {
355 action
= (uw
->macs
[i
] & (1ULL << 63)) ? SWITCHDEV_FDB_ADD_TO_BRIDGE
356 : SWITCHDEV_FDB_DEL_TO_BRIDGE
;
357 u64_to_ether_addr(uw
->macs
[i
] & 0xffffffffffffULL
, addr
);
358 info
.addr
= &addr
[0];
361 pr_debug("FDB entry %d: %llx, action %d\n", i
, uw
->macs
[0], action
);
362 call_switchdev_notifiers(action
, uw
->ndev
, &info
.info
, NULL
);
368 static void rtl839x_l2_notification_handler(struct rtl838x_eth_priv
*priv
)
370 struct notify_b
*nb
= priv
->membase
+ sizeof(struct ring_b
);
371 u32 e
= priv
->lastEvent
;
372 struct n_event
*event
;
375 struct fdb_update_work
*w
;
377 while (!(nb
->ring
[e
] & 1)) {
378 w
= kzalloc(sizeof(*w
), GFP_ATOMIC
);
380 pr_err("Out of memory: %s", __func__
);
383 INIT_WORK(&w
->work
, rtl838x_fdb_sync
);
385 for (i
= 0; i
< NOTIFY_EVENTS
; i
++) {
386 event
= &nb
->blocks
[e
].events
[i
];
392 w
->ndev
= priv
->netdev
;
396 /* Hand the ring entry back to the switch */
397 nb
->ring
[e
] = nb
->ring
[e
] | 1;
398 e
= (e
+ 1) % NOTIFY_BLOCKS
;
401 schedule_work(&w
->work
);
406 static irqreturn_t
rtl83xx_net_irq(int irq
, void *dev_id
)
408 struct net_device
*dev
= dev_id
;
409 struct rtl838x_eth_priv
*priv
= netdev_priv(dev
);
410 u32 status
= sw_r32(priv
->r
->dma_if_intr_sts
);
411 bool triggered
= false;
412 u32 atk
= sw_r32(RTL838X_ATK_PRVNT_STS
);
414 u32 storm_uc
= sw_r32(RTL838X_STORM_CTRL_PORT_UC_EXCEED
);
415 u32 storm_mc
= sw_r32(RTL838X_STORM_CTRL_PORT_MC_EXCEED
);
416 u32 storm_bc
= sw_r32(RTL838X_STORM_CTRL_PORT_BC_EXCEED
);
418 pr_debug("IRQ: %08x\n", status
);
419 if (storm_uc
|| storm_mc
|| storm_bc
) {
420 pr_warn("Storm control UC: %08x, MC: %08x, BC: %08x\n",
421 storm_uc
, storm_mc
, storm_bc
);
423 sw_w32(storm_uc
, RTL838X_STORM_CTRL_PORT_UC_EXCEED
);
424 sw_w32(storm_mc
, RTL838X_STORM_CTRL_PORT_MC_EXCEED
);
425 sw_w32(storm_bc
, RTL838X_STORM_CTRL_PORT_BC_EXCEED
);
431 pr_debug("Attack prevention triggered: %08x\n", atk
);
432 sw_w32(atk
, RTL838X_ATK_PRVNT_STS
);
435 spin_lock(&priv
->lock
);
436 /* Ignore TX interrupt */
437 if ((status
& 0xf0000)) {
439 sw_w32(0x000f0000, priv
->r
->dma_if_intr_sts
);
443 if (status
& 0x0ff00) {
444 /* ACK and disable RX interrupt for this ring */
445 sw_w32_mask(0xff00 & status
, 0, priv
->r
->dma_if_intr_msk
);
446 sw_w32(0x0000ff00 & status
, priv
->r
->dma_if_intr_sts
);
447 for (i
= 0; i
< priv
->rxrings
; i
++) {
448 if (status
& BIT(i
+ 8)) {
449 pr_debug("Scheduling queue: %d\n", i
);
450 napi_schedule(&priv
->rx_qs
[i
].napi
);
455 /* RX buffer overrun */
456 if (status
& 0x000ff) {
457 pr_info("RX buffer overrun: status %x, mask: %x\n",
458 status
, sw_r32(priv
->r
->dma_if_intr_msk
));
459 sw_w32(status
, priv
->r
->dma_if_intr_sts
);
460 rtl838x_rb_cleanup(priv
, status
& 0xff);
463 if (priv
->family_id
== RTL8390_FAMILY_ID
&& status
& 0x00100000) {
464 sw_w32(0x00100000, priv
->r
->dma_if_intr_sts
);
465 rtl839x_l2_notification_handler(priv
);
468 if (priv
->family_id
== RTL8390_FAMILY_ID
&& status
& 0x00200000) {
469 sw_w32(0x00200000, priv
->r
->dma_if_intr_sts
);
470 rtl839x_l2_notification_handler(priv
);
473 if (priv
->family_id
== RTL8390_FAMILY_ID
&& status
& 0x00400000) {
474 sw_w32(0x00400000, priv
->r
->dma_if_intr_sts
);
475 rtl839x_l2_notification_handler(priv
);
478 spin_unlock(&priv
->lock
);
482 static irqreturn_t
rtl93xx_net_irq(int irq
, void *dev_id
)
484 struct net_device
*dev
= dev_id
;
485 struct rtl838x_eth_priv
*priv
= netdev_priv(dev
);
486 u32 status_rx_r
= sw_r32(priv
->r
->dma_if_intr_rx_runout_sts
);
487 u32 status_rx
= sw_r32(priv
->r
->dma_if_intr_rx_done_sts
);
488 u32 status_tx
= sw_r32(priv
->r
->dma_if_intr_tx_done_sts
);
491 pr_debug("In %s, status_tx: %08x, status_rx: %08x, status_rx_r: %08x\n",
492 __func__
, status_tx
, status_rx
, status_rx_r
);
493 spin_lock(&priv
->lock
);
495 /* Ignore TX interrupt */
498 pr_debug("TX done\n");
499 sw_w32(status_tx
, priv
->r
->dma_if_intr_tx_done_sts
);
504 pr_debug("RX IRQ\n");
505 /* ACK and disable RX interrupt for given rings */
506 sw_w32(status_rx
, priv
->r
->dma_if_intr_rx_done_sts
);
507 sw_w32_mask(status_rx
, 0, priv
->r
->dma_if_intr_rx_done_msk
);
508 for (i
= 0; i
< priv
->rxrings
; i
++) {
509 if (status_rx
& BIT(i
)) {
510 pr_debug("Scheduling queue: %d\n", i
);
511 napi_schedule(&priv
->rx_qs
[i
].napi
);
516 /* RX buffer overrun */
518 pr_debug("RX buffer overrun: status %x, mask: %x\n",
519 status_rx_r
, sw_r32(priv
->r
->dma_if_intr_rx_runout_msk
));
520 sw_w32(status_rx_r
, priv
->r
->dma_if_intr_rx_runout_sts
);
521 rtl838x_rb_cleanup(priv
, status_rx_r
);
524 spin_unlock(&priv
->lock
);
528 static const struct rtl838x_reg rtl838x_reg
= {
529 .net_irq
= rtl83xx_net_irq
,
530 .mac_port_ctrl
= rtl838x_mac_port_ctrl
,
531 .dma_if_intr_sts
= RTL838X_DMA_IF_INTR_STS
,
532 .dma_if_intr_msk
= RTL838X_DMA_IF_INTR_MSK
,
533 .dma_if_ctrl
= RTL838X_DMA_IF_CTRL
,
534 .mac_force_mode_ctrl
= RTL838X_MAC_FORCE_MODE_CTRL
,
535 .dma_rx_base
= RTL838X_DMA_RX_BASE
,
536 .dma_tx_base
= RTL838X_DMA_TX_BASE
,
537 .dma_if_rx_ring_size
= rtl838x_dma_if_rx_ring_size
,
538 .dma_if_rx_ring_cntr
= rtl838x_dma_if_rx_ring_cntr
,
539 .dma_if_rx_cur
= RTL838X_DMA_IF_RX_CUR
,
540 .rst_glb_ctrl
= RTL838X_RST_GLB_CTRL_0
,
541 .get_mac_link_sts
= rtl838x_get_mac_link_sts
,
542 .get_mac_link_dup_sts
= rtl838x_get_mac_link_dup_sts
,
543 .get_mac_link_spd_sts
= rtl838x_get_mac_link_spd_sts
,
544 .get_mac_rx_pause_sts
= rtl838x_get_mac_rx_pause_sts
,
545 .get_mac_tx_pause_sts
= rtl838x_get_mac_tx_pause_sts
,
547 .l2_tbl_flush_ctrl
= RTL838X_L2_TBL_FLUSH_CTRL
,
548 .update_cntr
= rtl838x_update_cntr
,
549 .create_tx_header
= rtl838x_create_tx_header
,
550 .decode_tag
= rtl838x_decode_tag
,
553 static const struct rtl838x_reg rtl839x_reg
= {
554 .net_irq
= rtl83xx_net_irq
,
555 .mac_port_ctrl
= rtl839x_mac_port_ctrl
,
556 .dma_if_intr_sts
= RTL839X_DMA_IF_INTR_STS
,
557 .dma_if_intr_msk
= RTL839X_DMA_IF_INTR_MSK
,
558 .dma_if_ctrl
= RTL839X_DMA_IF_CTRL
,
559 .mac_force_mode_ctrl
= RTL839X_MAC_FORCE_MODE_CTRL
,
560 .dma_rx_base
= RTL839X_DMA_RX_BASE
,
561 .dma_tx_base
= RTL839X_DMA_TX_BASE
,
562 .dma_if_rx_ring_size
= rtl839x_dma_if_rx_ring_size
,
563 .dma_if_rx_ring_cntr
= rtl839x_dma_if_rx_ring_cntr
,
564 .dma_if_rx_cur
= RTL839X_DMA_IF_RX_CUR
,
565 .rst_glb_ctrl
= RTL839X_RST_GLB_CTRL
,
566 .get_mac_link_sts
= rtl839x_get_mac_link_sts
,
567 .get_mac_link_dup_sts
= rtl839x_get_mac_link_dup_sts
,
568 .get_mac_link_spd_sts
= rtl839x_get_mac_link_spd_sts
,
569 .get_mac_rx_pause_sts
= rtl839x_get_mac_rx_pause_sts
,
570 .get_mac_tx_pause_sts
= rtl839x_get_mac_tx_pause_sts
,
572 .l2_tbl_flush_ctrl
= RTL839X_L2_TBL_FLUSH_CTRL
,
573 .update_cntr
= rtl839x_update_cntr
,
574 .create_tx_header
= rtl839x_create_tx_header
,
575 .decode_tag
= rtl839x_decode_tag
,
578 static const struct rtl838x_reg rtl930x_reg
= {
579 .net_irq
= rtl93xx_net_irq
,
580 .mac_port_ctrl
= rtl930x_mac_port_ctrl
,
581 .dma_if_intr_rx_runout_sts
= RTL930X_DMA_IF_INTR_RX_RUNOUT_STS
,
582 .dma_if_intr_rx_done_sts
= RTL930X_DMA_IF_INTR_RX_DONE_STS
,
583 .dma_if_intr_tx_done_sts
= RTL930X_DMA_IF_INTR_TX_DONE_STS
,
584 .dma_if_intr_rx_runout_msk
= RTL930X_DMA_IF_INTR_RX_RUNOUT_MSK
,
585 .dma_if_intr_rx_done_msk
= RTL930X_DMA_IF_INTR_RX_DONE_MSK
,
586 .dma_if_intr_tx_done_msk
= RTL930X_DMA_IF_INTR_TX_DONE_MSK
,
587 .l2_ntfy_if_intr_sts
= RTL930X_L2_NTFY_IF_INTR_STS
,
588 .l2_ntfy_if_intr_msk
= RTL930X_L2_NTFY_IF_INTR_MSK
,
589 .dma_if_ctrl
= RTL930X_DMA_IF_CTRL
,
590 .mac_force_mode_ctrl
= RTL930X_MAC_FORCE_MODE_CTRL
,
591 .dma_rx_base
= RTL930X_DMA_RX_BASE
,
592 .dma_tx_base
= RTL930X_DMA_TX_BASE
,
593 .dma_if_rx_ring_size
= rtl930x_dma_if_rx_ring_size
,
594 .dma_if_rx_ring_cntr
= rtl930x_dma_if_rx_ring_cntr
,
595 .dma_if_rx_cur
= RTL930X_DMA_IF_RX_CUR
,
596 .rst_glb_ctrl
= RTL930X_RST_GLB_CTRL_0
,
597 .get_mac_link_sts
= rtl930x_get_mac_link_sts
,
598 .get_mac_link_dup_sts
= rtl930x_get_mac_link_dup_sts
,
599 .get_mac_link_spd_sts
= rtl930x_get_mac_link_spd_sts
,
600 .get_mac_rx_pause_sts
= rtl930x_get_mac_rx_pause_sts
,
601 .get_mac_tx_pause_sts
= rtl930x_get_mac_tx_pause_sts
,
602 .mac
= RTL930X_MAC_L2_ADDR_CTRL
,
603 .l2_tbl_flush_ctrl
= RTL930X_L2_TBL_FLUSH_CTRL
,
604 .update_cntr
= rtl930x_update_cntr
,
605 .create_tx_header
= rtl930x_create_tx_header
,
606 .decode_tag
= rtl930x_decode_tag
,
609 static const struct rtl838x_reg rtl931x_reg
= {
610 .net_irq
= rtl93xx_net_irq
,
611 .mac_port_ctrl
= rtl931x_mac_port_ctrl
,
612 .dma_if_intr_rx_runout_sts
= RTL931X_DMA_IF_INTR_RX_RUNOUT_STS
,
613 .dma_if_intr_rx_done_sts
= RTL931X_DMA_IF_INTR_RX_DONE_STS
,
614 .dma_if_intr_tx_done_sts
= RTL931X_DMA_IF_INTR_TX_DONE_STS
,
615 .dma_if_intr_rx_runout_msk
= RTL931X_DMA_IF_INTR_RX_RUNOUT_MSK
,
616 .dma_if_intr_rx_done_msk
= RTL931X_DMA_IF_INTR_RX_DONE_MSK
,
617 .dma_if_intr_tx_done_msk
= RTL931X_DMA_IF_INTR_TX_DONE_MSK
,
618 .l2_ntfy_if_intr_sts
= RTL931X_L2_NTFY_IF_INTR_STS
,
619 .l2_ntfy_if_intr_msk
= RTL931X_L2_NTFY_IF_INTR_MSK
,
620 .dma_if_ctrl
= RTL931X_DMA_IF_CTRL
,
621 .mac_force_mode_ctrl
= RTL931X_MAC_FORCE_MODE_CTRL
,
622 .dma_rx_base
= RTL931X_DMA_RX_BASE
,
623 .dma_tx_base
= RTL931X_DMA_TX_BASE
,
624 .dma_if_rx_ring_size
= rtl931x_dma_if_rx_ring_size
,
625 .dma_if_rx_ring_cntr
= rtl931x_dma_if_rx_ring_cntr
,
626 .dma_if_rx_cur
= RTL931X_DMA_IF_RX_CUR
,
627 .rst_glb_ctrl
= RTL931X_RST_GLB_CTRL
,
628 .get_mac_link_sts
= rtl931x_get_mac_link_sts
,
629 .get_mac_link_dup_sts
= rtl931x_get_mac_link_dup_sts
,
630 .get_mac_link_spd_sts
= rtl931x_get_mac_link_spd_sts
,
631 .get_mac_rx_pause_sts
= rtl931x_get_mac_rx_pause_sts
,
632 .get_mac_tx_pause_sts
= rtl931x_get_mac_tx_pause_sts
,
633 .mac
= RTL931X_MAC_L2_ADDR_CTRL
,
634 .l2_tbl_flush_ctrl
= RTL931X_L2_TBL_FLUSH_CTRL
,
635 .update_cntr
= rtl931x_update_cntr
,
636 .create_tx_header
= rtl931x_create_tx_header
,
637 .decode_tag
= rtl931x_decode_tag
,
640 static void rtl838x_hw_reset(struct rtl838x_eth_priv
*priv
)
645 pr_info("RESETTING %x, CPU_PORT %d\n", priv
->family_id
, priv
->cpu_port
);
646 sw_w32_mask(0x3, 0, priv
->r
->mac_port_ctrl(priv
->cpu_port
));
649 /* Disable and clear interrupts */
650 if (priv
->family_id
== RTL9300_FAMILY_ID
|| priv
->family_id
== RTL9310_FAMILY_ID
) {
651 sw_w32(0x00000000, priv
->r
->dma_if_intr_rx_runout_msk
);
652 sw_w32(0xffffffff, priv
->r
->dma_if_intr_rx_runout_sts
);
653 sw_w32(0x00000000, priv
->r
->dma_if_intr_rx_done_msk
);
654 sw_w32(0xffffffff, priv
->r
->dma_if_intr_rx_done_sts
);
655 sw_w32(0x00000000, priv
->r
->dma_if_intr_tx_done_msk
);
656 sw_w32(0x0000000f, priv
->r
->dma_if_intr_tx_done_sts
);
658 sw_w32(0x00000000, priv
->r
->dma_if_intr_msk
);
659 sw_w32(0xffffffff, priv
->r
->dma_if_intr_sts
);
662 if (priv
->family_id
== RTL8390_FAMILY_ID
) {
663 /* Preserve L2 notification and NBUF settings */
664 int_saved
= sw_r32(priv
->r
->dma_if_intr_msk
);
665 nbuf
= sw_r32(RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL
);
667 /* Disable link change interrupt on RTL839x */
668 sw_w32(0, RTL839X_IMR_PORT_LINK_STS_CHG
);
669 sw_w32(0, RTL839X_IMR_PORT_LINK_STS_CHG
+ 4);
671 sw_w32(0x00000000, priv
->r
->dma_if_intr_msk
);
672 sw_w32(0xffffffff, priv
->r
->dma_if_intr_sts
);
676 if (priv
->family_id
== RTL9300_FAMILY_ID
|| priv
->family_id
== RTL9310_FAMILY_ID
)
677 sw_w32(0x4, priv
->r
->rst_glb_ctrl
);
679 sw_w32(0x8, priv
->r
->rst_glb_ctrl
);
681 do { /* Wait for reset of NIC and Queues done */
683 } while (sw_r32(priv
->r
->rst_glb_ctrl
) & 0xc);
686 /* Setup Head of Line */
687 if (priv
->family_id
== RTL8380_FAMILY_ID
)
688 sw_w32(0, RTL838X_DMA_IF_RX_RING_SIZE
); // Disabled on RTL8380
689 if (priv
->family_id
== RTL8390_FAMILY_ID
)
690 sw_w32(0xffffffff, RTL839X_DMA_IF_RX_RING_CNTR
);
691 if (priv
->family_id
== RTL9300_FAMILY_ID
) {
692 for (i
= 0; i
< priv
->rxrings
; i
++) {
694 sw_w32_mask(0x3ff << pos
, 0, priv
->r
->dma_if_rx_ring_size(i
));
695 sw_w32_mask(0x3ff << pos
, priv
->rxringlen
,
696 priv
->r
->dma_if_rx_ring_cntr(i
));
700 /* Re-enable link change interrupt */
701 if (priv
->family_id
== RTL8390_FAMILY_ID
) {
702 sw_w32(0xffffffff, RTL839X_ISR_PORT_LINK_STS_CHG
);
703 sw_w32(0xffffffff, RTL839X_ISR_PORT_LINK_STS_CHG
+ 4);
704 sw_w32(0xffffffff, RTL839X_IMR_PORT_LINK_STS_CHG
);
705 sw_w32(0xffffffff, RTL839X_IMR_PORT_LINK_STS_CHG
+ 4);
707 /* Restore notification settings: on RTL838x these bits are null */
708 sw_w32_mask(7 << 20, int_saved
& (7 << 20), priv
->r
->dma_if_intr_msk
);
709 sw_w32(nbuf
, RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL
);
713 static void rtl838x_hw_ring_setup(struct rtl838x_eth_priv
*priv
)
716 struct ring_b
*ring
= priv
->membase
;
718 for (i
= 0; i
< priv
->rxrings
; i
++)
719 sw_w32(KSEG1ADDR(&ring
->rx_r
[i
]), priv
->r
->dma_rx_base
+ i
* 4);
721 for (i
= 0; i
< TXRINGS
; i
++)
722 sw_w32(KSEG1ADDR(&ring
->tx_r
[i
]), priv
->r
->dma_tx_base
+ i
* 4);
725 static void rtl838x_hw_en_rxtx(struct rtl838x_eth_priv
*priv
)
727 /* Disable Head of Line features for all RX rings */
728 sw_w32(0xffffffff, priv
->r
->dma_if_rx_ring_size(0));
730 /* Truncate RX buffer to 0x640 (1600) bytes, pad TX */
731 sw_w32(0x06400020, priv
->r
->dma_if_ctrl
);
733 /* Enable RX done, RX overflow and TX done interrupts */
734 sw_w32(0xfffff, priv
->r
->dma_if_intr_msk
);
736 /* Enable DMA, engine expects empty FCS field */
737 sw_w32_mask(0, RX_EN
| TX_EN
, priv
->r
->dma_if_ctrl
);
739 /* Restart TX/RX to CPU port */
740 sw_w32_mask(0x0, 0x3, priv
->r
->mac_port_ctrl(priv
->cpu_port
));
741 /* Set Speed, duplex, flow control
742 * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL
743 * | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN
746 sw_w32(0x6192F, priv
->r
->mac_force_mode_ctrl
+ priv
->cpu_port
* 4);
748 /* Enable CRC checks on CPU-port */
749 sw_w32_mask(0, BIT(3), priv
->r
->mac_port_ctrl(priv
->cpu_port
));
752 static void rtl839x_hw_en_rxtx(struct rtl838x_eth_priv
*priv
)
754 /* Setup CPU-Port: RX Buffer */
755 sw_w32(0x0000c808, priv
->r
->dma_if_ctrl
);
757 /* Enable Notify, RX done, RX overflow and TX done interrupts */
758 sw_w32(0x007fffff, priv
->r
->dma_if_intr_msk
); // Notify IRQ!
761 sw_w32_mask(0, RX_EN
| TX_EN
, priv
->r
->dma_if_ctrl
);
763 /* Restart TX/RX to CPU port, enable CRC checking */
764 sw_w32_mask(0x0, 0x3 | BIT(3), priv
->r
->mac_port_ctrl(priv
->cpu_port
));
766 /* CPU port joins Lookup Miss Flooding Portmask */
767 // TODO: The code below should also work for the RTL838x
768 sw_w32(0x28000, RTL839X_TBL_ACCESS_L2_CTRL
);
769 sw_w32_mask(0, 0x80000000, RTL839X_TBL_ACCESS_L2_DATA(0));
770 sw_w32(0x38000, RTL839X_TBL_ACCESS_L2_CTRL
);
772 /* Force CPU port link up */
773 sw_w32_mask(0, 3, priv
->r
->mac_force_mode_ctrl
+ priv
->cpu_port
* 4);
776 static void rtl93xx_hw_en_rxtx(struct rtl838x_eth_priv
*priv
)
781 /* Setup CPU-Port: RX Buffer truncated at 1600 Bytes */
782 sw_w32(0x06400040, priv
->r
->dma_if_ctrl
);
784 for (i
= 0; i
< priv
->rxrings
; i
++) {
786 sw_w32_mask(0x3ff << pos
, priv
->rxringlen
<< pos
, priv
->r
->dma_if_rx_ring_size(i
));
788 // Some SoCs have issues with missing underflow protection
789 v
= (sw_r32(priv
->r
->dma_if_rx_ring_cntr(i
)) >> pos
) & 0x3ff;
790 sw_w32_mask(0x3ff << pos
, v
, priv
->r
->dma_if_rx_ring_cntr(i
));
793 /* Enable Notify, RX done, RX overflow and TX done interrupts */
794 sw_w32(0xffffffff, priv
->r
->dma_if_intr_rx_runout_msk
);
795 sw_w32(0xffffffff, priv
->r
->dma_if_intr_rx_done_msk
);
796 sw_w32(0x0000000f, priv
->r
->dma_if_intr_tx_done_msk
);
799 sw_w32_mask(0, RX_EN_93XX
| TX_EN_93XX
, priv
->r
->dma_if_ctrl
);
801 /* Restart TX/RX to CPU port, enable CRC checking */
802 sw_w32_mask(0x0, 0x3 | BIT(4), priv
->r
->mac_port_ctrl(priv
->cpu_port
));
804 sw_w32_mask(0, BIT(priv
->cpu_port
), RTL930X_L2_UNKN_UC_FLD_PMSK
);
805 sw_w32(0x217, priv
->r
->mac_force_mode_ctrl
+ priv
->cpu_port
* 4);
808 static void rtl838x_setup_ring_buffer(struct rtl838x_eth_priv
*priv
, struct ring_b
*ring
)
814 for (i
= 0; i
< priv
->rxrings
; i
++) {
815 for (j
= 0; j
< priv
->rxringlen
; j
++) {
816 h
= &ring
->rx_header
[i
][j
];
817 memset(h
, 0, sizeof(struct p_hdr
));
818 h
->buf
= (u8
*)KSEG1ADDR(ring
->rx_space
819 + i
* priv
->rxringlen
* RING_BUFFER
821 h
->size
= RING_BUFFER
;
822 /* All rings owned by switch, last one wraps */
823 ring
->rx_r
[i
][j
] = KSEG1ADDR(h
) | 1
824 | (j
== (priv
->rxringlen
- 1) ? WRAP
: 0);
829 for (i
= 0; i
< TXRINGS
; i
++) {
830 for (j
= 0; j
< TXRINGLEN
; j
++) {
831 h
= &ring
->tx_header
[i
][j
];
832 memset(h
, 0, sizeof(struct p_hdr
));
833 h
->buf
= (u8
*)KSEG1ADDR(ring
->tx_space
834 + i
* TXRINGLEN
* RING_BUFFER
836 h
->size
= RING_BUFFER
;
837 ring
->tx_r
[i
][j
] = KSEG1ADDR(&ring
->tx_header
[i
][j
]);
839 /* Last header is wrapping around */
840 ring
->tx_r
[i
][j
-1] |= WRAP
;
845 static void rtl839x_setup_notify_ring_buffer(struct rtl838x_eth_priv
*priv
)
848 struct notify_b
*b
= priv
->membase
+ sizeof(struct ring_b
);
850 for (i
= 0; i
< NOTIFY_BLOCKS
; i
++)
851 b
->ring
[i
] = KSEG1ADDR(&b
->blocks
[i
]) | 1 | (i
== (NOTIFY_BLOCKS
- 1) ? WRAP
: 0);
853 sw_w32((u32
) b
->ring
, RTL839X_DMA_IF_NBUF_BASE_DESC_ADDR_CTRL
);
854 sw_w32_mask(0x3ff << 2, 100 << 2, RTL839X_L2_NOTIFICATION_CTRL
);
856 /* Setup notification events */
857 sw_w32_mask(0, 1 << 14, RTL839X_L2_CTRL_0
); // RTL8390_L2_CTRL_0_FLUSH_NOTIFY_EN
858 sw_w32_mask(0, 1 << 12, RTL839X_L2_NOTIFICATION_CTRL
); // SUSPEND_NOTIFICATION_EN
860 /* Enable Notification */
861 sw_w32_mask(0, 1 << 0, RTL839X_L2_NOTIFICATION_CTRL
);
865 static int rtl838x_eth_open(struct net_device
*ndev
)
868 struct rtl838x_eth_priv
*priv
= netdev_priv(ndev
);
869 struct ring_b
*ring
= priv
->membase
;
872 pr_debug("%s called: RX rings %d(length %d), TX rings %d(length %d)\n",
873 __func__
, priv
->rxrings
, priv
->rxringlen
, TXRINGS
, TXRINGLEN
);
875 spin_lock_irqsave(&priv
->lock
, flags
);
876 rtl838x_hw_reset(priv
);
877 rtl838x_setup_ring_buffer(priv
, ring
);
878 if (priv
->family_id
== RTL8390_FAMILY_ID
) {
879 rtl839x_setup_notify_ring_buffer(priv
);
880 /* Make sure the ring structure is visible to the ASIC */
885 rtl838x_hw_ring_setup(priv
);
886 err
= request_irq(ndev
->irq
, priv
->r
->net_irq
, IRQF_SHARED
, ndev
->name
, ndev
);
888 netdev_err(ndev
, "%s: could not acquire interrupt: %d\n",
892 phylink_start(priv
->phylink
);
894 for (i
= 0; i
< priv
->rxrings
; i
++)
895 napi_enable(&priv
->rx_qs
[i
].napi
);
897 switch (priv
->family_id
) {
898 case RTL8380_FAMILY_ID
:
899 rtl838x_hw_en_rxtx(priv
);
900 /* Trap IGMP/MLD traffic to CPU-Port */
901 sw_w32(0x3, RTL838X_SPCL_TRAP_IGMP_CTRL
);
902 /* Flush learned FDB entries on link down of a port */
903 sw_w32_mask(0, BIT(7), RTL838X_L2_CTRL_0
);
906 case RTL8390_FAMILY_ID
:
907 rtl839x_hw_en_rxtx(priv
);
908 // Trap MLD and IGMP messages to CPU_PORT
909 sw_w32(0x3, RTL839X_SPCL_TRAP_IGMP_CTRL
);
910 /* Flush learned FDB entries on link down of a port */
911 sw_w32_mask(0, BIT(7), RTL839X_L2_CTRL_0
);
914 case RTL9300_FAMILY_ID
:
915 rtl93xx_hw_en_rxtx(priv
);
916 /* Flush learned FDB entries on link down of a port */
917 sw_w32_mask(0, BIT(7), RTL930X_L2_CTRL
);
918 // Trap MLD and IGMP messages to CPU_PORT
919 sw_w32((0x2 << 3) | 0x2, RTL930X_VLAN_APP_PKT_CTRL
);
922 case RTL9310_FAMILY_ID
:
923 rtl93xx_hw_en_rxtx(priv
);
927 netif_tx_start_all_queues(ndev
);
929 spin_unlock_irqrestore(&priv
->lock
, flags
);
934 static void rtl838x_hw_stop(struct rtl838x_eth_priv
*priv
)
936 u32 force_mac
= priv
->family_id
== RTL8380_FAMILY_ID
? 0x6192C : 0x75;
937 u32 clear_irq
= priv
->family_id
== RTL8380_FAMILY_ID
? 0x000fffff : 0x007fffff;
940 // Disable RX/TX from/to CPU-port
941 sw_w32_mask(0x3, 0, priv
->r
->mac_port_ctrl(priv
->cpu_port
));
943 /* Disable traffic */
944 if (priv
->family_id
== RTL9300_FAMILY_ID
|| priv
->family_id
== RTL9310_FAMILY_ID
)
945 sw_w32_mask(RX_EN_93XX
| TX_EN_93XX
, 0, priv
->r
->dma_if_ctrl
);
947 sw_w32_mask(RX_EN
| TX_EN
, 0, priv
->r
->dma_if_ctrl
);
948 mdelay(200); // Test, whether this is needed
950 /* Block all ports */
951 if (priv
->family_id
== RTL8380_FAMILY_ID
) {
952 sw_w32(0x03000000, RTL838X_TBL_ACCESS_DATA_0(0));
953 sw_w32(0x00000000, RTL838X_TBL_ACCESS_DATA_0(1));
954 sw_w32(1 << 15 | 2 << 12, RTL838X_TBL_ACCESS_CTRL_0
);
957 /* Flush L2 address cache */
958 if (priv
->family_id
== RTL8380_FAMILY_ID
) {
959 for (i
= 0; i
<= priv
->cpu_port
; i
++) {
960 sw_w32(1 << 26 | 1 << 23 | i
<< 5, priv
->r
->l2_tbl_flush_ctrl
);
961 do { } while (sw_r32(priv
->r
->l2_tbl_flush_ctrl
) & (1 << 26));
963 } else if (priv
->family_id
== RTL8390_FAMILY_ID
) {
964 for (i
= 0; i
<= priv
->cpu_port
; i
++) {
965 sw_w32(1 << 28 | 1 << 25 | i
<< 5, priv
->r
->l2_tbl_flush_ctrl
);
966 do { } while (sw_r32(priv
->r
->l2_tbl_flush_ctrl
) & (1 << 28));
969 // TODO: L2 flush register is 64 bit on RTL931X and 930X
971 /* CPU-Port: Link down */
972 if (priv
->family_id
== RTL8380_FAMILY_ID
|| priv
->family_id
== RTL8390_FAMILY_ID
)
973 sw_w32(force_mac
, priv
->r
->mac_force_mode_ctrl
+ priv
->cpu_port
* 4);
975 sw_w32_mask(0x3, 0, priv
->r
->mac_force_mode_ctrl
+ priv
->cpu_port
*4);
978 /* Disable all TX/RX interrupts */
979 if (priv
->family_id
== RTL9300_FAMILY_ID
|| priv
->family_id
== RTL9310_FAMILY_ID
) {
980 sw_w32(0x00000000, priv
->r
->dma_if_intr_rx_runout_msk
);
981 sw_w32(0xffffffff, priv
->r
->dma_if_intr_rx_runout_sts
);
982 sw_w32(0x00000000, priv
->r
->dma_if_intr_rx_done_msk
);
983 sw_w32(0xffffffff, priv
->r
->dma_if_intr_rx_done_sts
);
984 sw_w32(0x00000000, priv
->r
->dma_if_intr_tx_done_msk
);
985 sw_w32(0x0000000f, priv
->r
->dma_if_intr_tx_done_sts
);
987 sw_w32(0x00000000, priv
->r
->dma_if_intr_msk
);
988 sw_w32(clear_irq
, priv
->r
->dma_if_intr_sts
);
991 /* Disable TX/RX DMA */
992 sw_w32(0x00000000, priv
->r
->dma_if_ctrl
);
996 static int rtl838x_eth_stop(struct net_device
*ndev
)
1000 struct rtl838x_eth_priv
*priv
= netdev_priv(ndev
);
1002 pr_info("in %s\n", __func__
);
1004 spin_lock_irqsave(&priv
->lock
, flags
);
1005 phylink_stop(priv
->phylink
);
1006 rtl838x_hw_stop(priv
);
1007 free_irq(ndev
->irq
, ndev
);
1009 for (i
= 0; i
< priv
->rxrings
; i
++)
1010 napi_disable(&priv
->rx_qs
[i
].napi
);
1012 netif_tx_stop_all_queues(ndev
);
1014 spin_unlock_irqrestore(&priv
->lock
, flags
);
1019 static void rtl839x_eth_set_multicast_list(struct net_device
*ndev
)
1021 if (!(ndev
->flags
& (IFF_PROMISC
| IFF_ALLMULTI
))) {
1022 sw_w32(0x0, RTL839X_RMA_CTRL_0
);
1023 sw_w32(0x0, RTL839X_RMA_CTRL_1
);
1024 sw_w32(0x0, RTL839X_RMA_CTRL_2
);
1025 sw_w32(0x0, RTL839X_RMA_CTRL_3
);
1027 if (ndev
->flags
& IFF_ALLMULTI
) {
1028 sw_w32(0x7fffffff, RTL839X_RMA_CTRL_0
);
1029 sw_w32(0x7fffffff, RTL839X_RMA_CTRL_1
);
1030 sw_w32(0x7fffffff, RTL839X_RMA_CTRL_2
);
1032 if (ndev
->flags
& IFF_PROMISC
) {
1033 sw_w32(0x7fffffff, RTL839X_RMA_CTRL_0
);
1034 sw_w32(0x7fffffff, RTL839X_RMA_CTRL_1
);
1035 sw_w32(0x7fffffff, RTL839X_RMA_CTRL_2
);
1036 sw_w32(0x3ff, RTL839X_RMA_CTRL_3
);
1040 static void rtl838x_eth_set_multicast_list(struct net_device
*ndev
)
1042 struct rtl838x_eth_priv
*priv
= netdev_priv(ndev
);
1044 if (priv
->family_id
== RTL8390_FAMILY_ID
)
1045 return rtl839x_eth_set_multicast_list(ndev
);
1047 if (!(ndev
->flags
& (IFF_PROMISC
| IFF_ALLMULTI
))) {
1048 sw_w32(0x0, RTL838X_RMA_CTRL_0
);
1049 sw_w32(0x0, RTL838X_RMA_CTRL_1
);
1051 if (ndev
->flags
& IFF_ALLMULTI
)
1052 sw_w32(0x1fffff, RTL838X_RMA_CTRL_0
);
1053 if (ndev
->flags
& IFF_PROMISC
) {
1054 sw_w32(0x1fffff, RTL838X_RMA_CTRL_0
);
1055 sw_w32(0x7fff, RTL838X_RMA_CTRL_1
);
1059 static void rtl930x_eth_set_multicast_list(struct net_device
*ndev
)
1061 if (!(ndev
->flags
& (IFF_PROMISC
| IFF_ALLMULTI
))) {
1062 sw_w32(0x0, RTL930X_RMA_CTRL_0
);
1063 sw_w32(0x0, RTL930X_RMA_CTRL_1
);
1064 sw_w32(0x0, RTL930X_RMA_CTRL_2
);
1066 if (ndev
->flags
& IFF_ALLMULTI
) {
1067 sw_w32(0x7fffffff, RTL930X_RMA_CTRL_0
);
1068 sw_w32(0x7fffffff, RTL930X_RMA_CTRL_1
);
1069 sw_w32(0x7fffffff, RTL930X_RMA_CTRL_2
);
1071 if (ndev
->flags
& IFF_PROMISC
) {
1072 sw_w32(0x7fffffff, RTL930X_RMA_CTRL_0
);
1073 sw_w32(0x7fffffff, RTL930X_RMA_CTRL_1
);
1074 sw_w32(0x7fffffff, RTL930X_RMA_CTRL_2
);
1078 static void rtl931x_eth_set_multicast_list(struct net_device
*ndev
)
1080 if (!(ndev
->flags
& (IFF_PROMISC
| IFF_ALLMULTI
))) {
1081 sw_w32(0x0, RTL931X_RMA_CTRL_0
);
1082 sw_w32(0x0, RTL931X_RMA_CTRL_1
);
1083 sw_w32(0x0, RTL931X_RMA_CTRL_2
);
1085 if (ndev
->flags
& IFF_ALLMULTI
) {
1086 sw_w32(0x7fffffff, RTL931X_RMA_CTRL_0
);
1087 sw_w32(0x7fffffff, RTL931X_RMA_CTRL_1
);
1088 sw_w32(0x7fffffff, RTL931X_RMA_CTRL_2
);
1090 if (ndev
->flags
& IFF_PROMISC
) {
1091 sw_w32(0x7fffffff, RTL931X_RMA_CTRL_0
);
1092 sw_w32(0x7fffffff, RTL931X_RMA_CTRL_1
);
1093 sw_w32(0x7fffffff, RTL931X_RMA_CTRL_2
);
1097 static void rtl838x_eth_tx_timeout(struct net_device
*ndev
)
1099 unsigned long flags
;
1100 struct rtl838x_eth_priv
*priv
= netdev_priv(ndev
);
1102 pr_warn("%s\n", __func__
);
1103 spin_lock_irqsave(&priv
->lock
, flags
);
1104 rtl838x_hw_stop(priv
);
1105 rtl838x_hw_ring_setup(priv
);
1106 rtl838x_hw_en_rxtx(priv
);
1107 netif_trans_update(ndev
);
1108 netif_start_queue(ndev
);
1109 spin_unlock_irqrestore(&priv
->lock
, flags
);
1112 static int rtl838x_eth_tx(struct sk_buff
*skb
, struct net_device
*dev
)
1115 struct rtl838x_eth_priv
*priv
= netdev_priv(dev
);
1116 struct ring_b
*ring
= priv
->membase
;
1119 unsigned long flags
;
1122 int q
= skb_get_queue_mapping(skb
) % TXRINGS
;
1124 if (q
) // Check for high prio queue
1125 pr_debug("SKB priority: %d\n", skb
->priority
);
1127 spin_lock_irqsave(&priv
->lock
, flags
);
1130 /* Check for DSA tagging at the end of the buffer */
1131 if (netdev_uses_dsa(dev
) && skb
->data
[len
-4] == 0x80 && skb
->data
[len
-3] > 0
1132 && skb
->data
[len
-3] < priv
->cpu_port
&& skb
->data
[len
-2] == 0x10
1133 && skb
->data
[len
-1] == 0x00) {
1134 /* Reuse tag space for CRC if possible */
1135 dest_port
= skb
->data
[len
-3];
1136 skb
->data
[len
-4] = skb
->data
[len
-3] = skb
->data
[len
-2] = skb
->data
[len
-1] = 0x00;
1140 len
+= 4; // Add space for CRC
1142 if (skb_padto(skb
, len
)) {
1147 /* We can send this packet if CPU owns the descriptor */
1148 if (!(ring
->tx_r
[q
][ring
->c_tx
[q
]] & 0x1)) {
1150 /* Set descriptor for tx */
1151 h
= &ring
->tx_header
[q
][ring
->c_tx
[q
]];
1154 // On RTL8380 SoCs, small packet lengths being sent need adjustments
1155 if (priv
->family_id
== RTL8380_FAMILY_ID
) {
1156 if (len
< ETH_ZLEN
- 4)
1160 priv
->r
->create_tx_header(h
, dest_port
, skb
->priority
>> 1);
1162 /* Copy packet data to tx buffer */
1163 memcpy((void *)KSEG1ADDR(h
->buf
), skb
->data
, len
);
1164 /* Make sure packet data is visible to ASIC */
1167 /* Hand over to switch */
1168 ring
->tx_r
[q
][ring
->c_tx
[q
]] |= 1;
1170 // Before starting TX, prevent a Lextra bus bug on RTL8380 SoCs
1171 if (priv
->family_id
== RTL8380_FAMILY_ID
) {
1172 for (i
= 0; i
< 10; i
++) {
1173 val
= sw_r32(priv
->r
->dma_if_ctrl
);
1174 if ((val
& 0xc) == 0xc)
1179 /* Tell switch to send data */
1180 if (priv
->family_id
== RTL9310_FAMILY_ID
1181 || priv
->family_id
== RTL9300_FAMILY_ID
) {
1182 // Ring ID q == 0: Low priority, Ring ID = 1: High prio queue
1184 sw_w32_mask(0, BIT(2), priv
->r
->dma_if_ctrl
);
1186 sw_w32_mask(0, BIT(3), priv
->r
->dma_if_ctrl
);
1188 sw_w32_mask(0, TX_DO
, priv
->r
->dma_if_ctrl
);
1191 dev
->stats
.tx_packets
++;
1192 dev
->stats
.tx_bytes
+= len
;
1194 ring
->c_tx
[q
] = (ring
->c_tx
[q
] + 1) % TXRINGLEN
;
1197 dev_warn(&priv
->pdev
->dev
, "Data is owned by switch\n");
1198 ret
= NETDEV_TX_BUSY
;
1201 spin_unlock_irqrestore(&priv
->lock
, flags
);
1206 * Return queue number for TX. On the RTL83XX, these queues have equal priority
1207 * so we do round-robin
1209 u16
rtl83xx_pick_tx_queue(struct net_device
*dev
, struct sk_buff
*skb
,
1210 struct net_device
*sb_dev
)
1215 return last
% TXRINGS
;
1219 * Return queue number for TX. On the RTL93XX, queue 1 is the high priority queue
1221 u16
rtl93xx_pick_tx_queue(struct net_device
*dev
, struct sk_buff
*skb
,
1222 struct net_device
*sb_dev
)
1224 if (skb
->priority
>= TC_PRIO_CONTROL
)
1229 static int rtl838x_hw_receive(struct net_device
*dev
, int r
, int budget
)
1231 struct rtl838x_eth_priv
*priv
= netdev_priv(dev
);
1232 struct ring_b
*ring
= priv
->membase
;
1233 struct sk_buff
*skb
;
1234 unsigned long flags
;
1235 int i
, len
, work_done
= 0;
1236 u8
*data
, *skb_data
;
1240 bool dsa
= netdev_uses_dsa(dev
);
1243 spin_lock_irqsave(&priv
->lock
, flags
);
1244 last
= (u32
*)KSEG1ADDR(sw_r32(priv
->r
->dma_if_rx_cur
+ r
* 4));
1245 pr_debug("---------------------------------------------------------- RX - %d\n", r
);
1248 if ((ring
->rx_r
[r
][ring
->c_rx
[r
]] & 0x1)) {
1249 if (&ring
->rx_r
[r
][ring
->c_rx
[r
]] != last
) {
1250 netdev_warn(dev
, "Ring contention: r: %x, last %x, cur %x\n",
1251 r
, (uint32_t)last
, (u32
) &ring
->rx_r
[r
][ring
->c_rx
[r
]]);
1256 h
= &ring
->rx_header
[r
][ring
->c_rx
[r
]];
1257 data
= (u8
*)KSEG1ADDR(h
->buf
);
1263 len
-= 4; /* strip the CRC */
1264 /* Add 4 bytes for cpu_tag */
1268 skb
= alloc_skb(len
+ 4, GFP_KERNEL
);
1269 skb_reserve(skb
, NET_IP_ALIGN
);
1272 /* BUG: Prevent bug on RTL838x SoCs*/
1273 if (priv
->family_id
== RTL8380_FAMILY_ID
) {
1274 sw_w32(0xffffffff, priv
->r
->dma_if_rx_ring_size(0));
1275 for (i
= 0; i
< priv
->rxrings
; i
++) {
1276 /* Update each ring cnt */
1277 val
= sw_r32(priv
->r
->dma_if_rx_ring_cntr(i
));
1278 sw_w32(val
, priv
->r
->dma_if_rx_ring_cntr(i
));
1282 skb_data
= skb_put(skb
, len
);
1283 /* Make sure data is visible */
1285 memcpy(skb
->data
, (u8
*)KSEG1ADDR(data
), len
);
1286 /* Overwrite CRC with cpu_tag */
1288 priv
->r
->decode_tag(h
, &tag
);
1289 skb
->data
[len
-4] = 0x80;
1290 skb
->data
[len
-3] = tag
.port
;
1291 skb
->data
[len
-2] = 0x10;
1292 skb
->data
[len
-1] = 0x00;
1293 if (tag
.l2_offloaded
)
1294 skb
->data
[len
-3] |= 0x40;
1298 pr_debug("Queue: %d, len: %d, reason %d port %d\n",
1299 tag
.queue
, len
, tag
.reason
, tag
.port
);
1301 skb
->protocol
= eth_type_trans(skb
, dev
);
1302 if (dev
->features
& NETIF_F_RXCSUM
) {
1304 skb_checksum_none_assert(skb
);
1306 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1308 dev
->stats
.rx_packets
++;
1309 dev
->stats
.rx_bytes
+= len
;
1311 netif_receive_skb(skb
);
1313 if (net_ratelimit())
1314 dev_warn(&dev
->dev
, "low on memory - packet dropped\n");
1315 dev
->stats
.rx_dropped
++;
1318 /* Reset header structure */
1319 memset(h
, 0, sizeof(struct p_hdr
));
1321 h
->size
= RING_BUFFER
;
1323 ring
->rx_r
[r
][ring
->c_rx
[r
]] = KSEG1ADDR(h
) | 0x1
1324 | (ring
->c_rx
[r
] == (priv
->rxringlen
- 1) ? WRAP
: 0x1);
1325 ring
->c_rx
[r
] = (ring
->c_rx
[r
] + 1) % priv
->rxringlen
;
1326 last
= (u32
*)KSEG1ADDR(sw_r32(priv
->r
->dma_if_rx_cur
+ r
* 4));
1327 } while (&ring
->rx_r
[r
][ring
->c_rx
[r
]] != last
&& work_done
< budget
);
1330 priv
->r
->update_cntr(r
, 0);
1332 spin_unlock_irqrestore(&priv
->lock
, flags
);
1336 static int rtl838x_poll_rx(struct napi_struct
*napi
, int budget
)
1338 struct rtl838x_rx_q
*rx_q
= container_of(napi
, struct rtl838x_rx_q
, napi
);
1339 struct rtl838x_eth_priv
*priv
= rx_q
->priv
;
1344 while (work_done
< budget
) {
1345 work
= rtl838x_hw_receive(priv
->netdev
, r
, budget
- work_done
);
1351 if (work_done
< budget
) {
1352 napi_complete_done(napi
, work_done
);
1354 /* Enable RX interrupt */
1355 if (priv
->family_id
== RTL9300_FAMILY_ID
|| priv
->family_id
== RTL9310_FAMILY_ID
)
1356 sw_w32(0xffffffff, priv
->r
->dma_if_intr_rx_done_msk
);
1358 sw_w32_mask(0, 0xf00ff | BIT(r
+ 8), priv
->r
->dma_if_intr_msk
);
1364 static void rtl838x_validate(struct phylink_config
*config
,
1365 unsigned long *supported
,
1366 struct phylink_link_state
*state
)
1368 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask
) = { 0, };
1370 pr_debug("In %s\n", __func__
);
1372 if (!phy_interface_mode_is_rgmii(state
->interface
) &&
1373 state
->interface
!= PHY_INTERFACE_MODE_1000BASEX
&&
1374 state
->interface
!= PHY_INTERFACE_MODE_MII
&&
1375 state
->interface
!= PHY_INTERFACE_MODE_REVMII
&&
1376 state
->interface
!= PHY_INTERFACE_MODE_GMII
&&
1377 state
->interface
!= PHY_INTERFACE_MODE_QSGMII
&&
1378 state
->interface
!= PHY_INTERFACE_MODE_INTERNAL
&&
1379 state
->interface
!= PHY_INTERFACE_MODE_SGMII
) {
1380 bitmap_zero(supported
, __ETHTOOL_LINK_MODE_MASK_NBITS
);
1381 pr_err("Unsupported interface: %d\n", state
->interface
);
1385 /* Allow all the expected bits */
1386 phylink_set(mask
, Autoneg
);
1387 phylink_set_port_modes(mask
);
1388 phylink_set(mask
, Pause
);
1389 phylink_set(mask
, Asym_Pause
);
1391 /* With the exclusion of MII and Reverse MII, we support Gigabit,
1392 * including Half duplex
1394 if (state
->interface
!= PHY_INTERFACE_MODE_MII
&&
1395 state
->interface
!= PHY_INTERFACE_MODE_REVMII
) {
1396 phylink_set(mask
, 1000baseT_Full
);
1397 phylink_set(mask
, 1000baseT_Half
);
1400 phylink_set(mask
, 10baseT_Half
);
1401 phylink_set(mask
, 10baseT_Full
);
1402 phylink_set(mask
, 100baseT_Half
);
1403 phylink_set(mask
, 100baseT_Full
);
1405 bitmap_and(supported
, supported
, mask
,
1406 __ETHTOOL_LINK_MODE_MASK_NBITS
);
1407 bitmap_and(state
->advertising
, state
->advertising
, mask
,
1408 __ETHTOOL_LINK_MODE_MASK_NBITS
);
1412 static void rtl838x_mac_config(struct phylink_config
*config
,
1414 const struct phylink_link_state
*state
)
1416 /* This is only being called for the master device,
1417 * i.e. the CPU-Port. We don't need to do anything.
1420 pr_info("In %s, mode %x\n", __func__
, mode
);
1423 static void rtl838x_mac_an_restart(struct phylink_config
*config
)
1425 struct net_device
*dev
= container_of(config
->dev
, struct net_device
, dev
);
1426 struct rtl838x_eth_priv
*priv
= netdev_priv(dev
);
1428 /* This works only on RTL838x chips */
1429 if (priv
->family_id
!= RTL8380_FAMILY_ID
)
1432 pr_debug("In %s\n", __func__
);
1433 /* Restart by disabling and re-enabling link */
1434 sw_w32(0x6192D, priv
->r
->mac_force_mode_ctrl
+ priv
->cpu_port
* 4);
1436 sw_w32(0x6192F, priv
->r
->mac_force_mode_ctrl
+ priv
->cpu_port
* 4);
1439 static int rtl838x_mac_pcs_get_state(struct phylink_config
*config
,
1440 struct phylink_link_state
*state
)
1443 struct net_device
*dev
= container_of(config
->dev
, struct net_device
, dev
);
1444 struct rtl838x_eth_priv
*priv
= netdev_priv(dev
);
1445 int port
= priv
->cpu_port
;
1447 pr_debug("In %s\n", __func__
);
1449 state
->link
= priv
->r
->get_mac_link_sts(port
) ? 1 : 0;
1450 state
->duplex
= priv
->r
->get_mac_link_dup_sts(port
) ? 1 : 0;
1452 speed
= priv
->r
->get_mac_link_spd_sts(port
);
1455 state
->speed
= SPEED_10
;
1458 state
->speed
= SPEED_100
;
1461 state
->speed
= SPEED_1000
;
1464 state
->speed
= SPEED_UNKNOWN
;
1468 state
->pause
&= (MLO_PAUSE_RX
| MLO_PAUSE_TX
);
1469 if (priv
->r
->get_mac_rx_pause_sts(port
))
1470 state
->pause
|= MLO_PAUSE_RX
;
1471 if (priv
->r
->get_mac_tx_pause_sts(port
))
1472 state
->pause
|= MLO_PAUSE_TX
;
1477 static void rtl838x_mac_link_down(struct phylink_config
*config
,
1479 phy_interface_t interface
)
1481 struct net_device
*dev
= container_of(config
->dev
, struct net_device
, dev
);
1482 struct rtl838x_eth_priv
*priv
= netdev_priv(dev
);
1484 pr_debug("In %s\n", __func__
);
1485 /* Stop TX/RX to port */
1486 sw_w32_mask(0x03, 0, priv
->r
->mac_port_ctrl(priv
->cpu_port
));
1489 static void rtl838x_mac_link_up(struct phylink_config
*config
, unsigned int mode
,
1490 phy_interface_t interface
,
1491 struct phy_device
*phy
)
1493 struct net_device
*dev
= container_of(config
->dev
, struct net_device
, dev
);
1494 struct rtl838x_eth_priv
*priv
= netdev_priv(dev
);
1496 pr_debug("In %s\n", __func__
);
1497 /* Restart TX/RX to port */
1498 sw_w32_mask(0, 0x03, priv
->r
->mac_port_ctrl(priv
->cpu_port
));
1501 static void rtl838x_set_mac_hw(struct net_device
*dev
, u8
*mac
)
1503 struct rtl838x_eth_priv
*priv
= netdev_priv(dev
);
1504 unsigned long flags
;
1506 spin_lock_irqsave(&priv
->lock
, flags
);
1507 pr_debug("In %s\n", __func__
);
1508 sw_w32((mac
[0] << 8) | mac
[1], priv
->r
->mac
);
1509 sw_w32((mac
[2] << 24) | (mac
[3] << 16) | (mac
[4] << 8) | mac
[5], priv
->r
->mac
+ 4);
1511 if (priv
->family_id
== RTL8380_FAMILY_ID
) {
1512 /* 2 more registers, ALE/MAC block */
1513 sw_w32((mac
[0] << 8) | mac
[1], RTL838X_MAC_ALE
);
1514 sw_w32((mac
[2] << 24) | (mac
[3] << 16) | (mac
[4] << 8) | mac
[5],
1515 (RTL838X_MAC_ALE
+ 4));
1517 sw_w32((mac
[0] << 8) | mac
[1], RTL838X_MAC2
);
1518 sw_w32((mac
[2] << 24) | (mac
[3] << 16) | (mac
[4] << 8) | mac
[5],
1521 spin_unlock_irqrestore(&priv
->lock
, flags
);
1524 static int rtl838x_set_mac_address(struct net_device
*dev
, void *p
)
1526 struct rtl838x_eth_priv
*priv
= netdev_priv(dev
);
1527 const struct sockaddr
*addr
= p
;
1528 u8
*mac
= (u8
*) (addr
->sa_data
);
1530 if (!is_valid_ether_addr(addr
->sa_data
))
1531 return -EADDRNOTAVAIL
;
1533 memcpy(dev
->dev_addr
, addr
->sa_data
, ETH_ALEN
);
1534 rtl838x_set_mac_hw(dev
, mac
);
1536 pr_info("Using MAC %08x%08x\n", sw_r32(priv
->r
->mac
), sw_r32(priv
->r
->mac
+ 4));
1540 static int rtl8390_init_mac(struct rtl838x_eth_priv
*priv
)
1542 // We will need to set-up EEE and the egress-rate limitation
1546 static int rtl8380_init_mac(struct rtl838x_eth_priv
*priv
)
1550 if (priv
->family_id
== 0x8390)
1551 return rtl8390_init_mac(priv
);
1553 pr_info("%s\n", __func__
);
1554 /* fix timer for EEE */
1555 sw_w32(0x5001411, RTL838X_EEE_TX_TIMER_GIGA_CTRL
);
1556 sw_w32(0x5001417, RTL838X_EEE_TX_TIMER_GELITE_CTRL
);
1559 if (priv
->id
== 0x8382) {
1560 for (i
= 0; i
<= 28; i
++)
1561 sw_w32(0, 0xd57c + i
* 0x80);
1563 if (priv
->id
== 0x8380) {
1564 for (i
= 8; i
<= 28; i
++)
1565 sw_w32(0, 0xd57c + i
* 0x80);
1570 static int rtl838x_get_link_ksettings(struct net_device
*ndev
,
1571 struct ethtool_link_ksettings
*cmd
)
1573 struct rtl838x_eth_priv
*priv
= netdev_priv(ndev
);
1575 pr_debug("%s called\n", __func__
);
1576 return phylink_ethtool_ksettings_get(priv
->phylink
, cmd
);
1579 static int rtl838x_set_link_ksettings(struct net_device
*ndev
,
1580 const struct ethtool_link_ksettings
*cmd
)
1582 struct rtl838x_eth_priv
*priv
= netdev_priv(ndev
);
1584 pr_debug("%s called\n", __func__
);
1585 return phylink_ethtool_ksettings_set(priv
->phylink
, cmd
);
1588 static int rtl838x_mdio_read(struct mii_bus
*bus
, int mii_id
, int regnum
)
1592 struct rtl838x_eth_priv
*priv
= bus
->priv
;
1594 if (mii_id
>= 24 && mii_id
<= 27 && priv
->id
== 0x8380)
1595 return rtl838x_read_sds_phy(mii_id
, regnum
);
1596 err
= rtl838x_read_phy(mii_id
, 0, regnum
, &val
);
1602 static int rtl839x_mdio_read(struct mii_bus
*bus
, int mii_id
, int regnum
)
1606 struct rtl838x_eth_priv
*priv
= bus
->priv
;
1608 if (mii_id
>= 48 && mii_id
<= 49 && priv
->id
== 0x8393)
1609 return rtl839x_read_sds_phy(mii_id
, regnum
);
1611 err
= rtl839x_read_phy(mii_id
, 0, regnum
, &val
);
1617 static int rtl930x_mdio_read(struct mii_bus
*bus
, int mii_id
, int regnum
)
1622 // TODO: These are hard-coded for the 2 Fibre Ports of the XGS1210
1623 if (mii_id
>= 26 && mii_id
<= 27)
1624 return rtl930x_read_sds_phy(mii_id
- 18, 0, regnum
);
1626 if (regnum
& MII_ADDR_C45
) {
1627 regnum
&= ~MII_ADDR_C45
;
1628 err
= rtl930x_read_mmd_phy(mii_id
, regnum
>> 16, regnum
& 0xffff, &val
);
1630 err
= rtl930x_read_phy(mii_id
, 0, regnum
, &val
);
1637 static int rtl931x_mdio_read(struct mii_bus
*bus
, int mii_id
, int regnum
)
1641 // struct rtl838x_eth_priv *priv = bus->priv;
1643 // if (mii_id >= 48 && mii_id <= 49 && priv->id == 0x8393)
1644 // return rtl839x_read_sds_phy(mii_id, regnum);
1646 err
= rtl931x_read_phy(mii_id
, 0, regnum
, &val
);
1652 static int rtl838x_mdio_write(struct mii_bus
*bus
, int mii_id
,
1653 int regnum
, u16 value
)
1656 struct rtl838x_eth_priv
*priv
= bus
->priv
;
1658 if (mii_id
>= 24 && mii_id
<= 27 && priv
->id
== 0x8380) {
1661 sw_w32(value
, RTL838X_SDS4_FIB_REG0
+ offset
+ (regnum
<< 2));
1664 return rtl838x_write_phy(mii_id
, 0, regnum
, value
);
1667 static int rtl839x_mdio_write(struct mii_bus
*bus
, int mii_id
,
1668 int regnum
, u16 value
)
1670 struct rtl838x_eth_priv
*priv
= bus
->priv
;
1672 if (mii_id
>= 48 && mii_id
<= 49 && priv
->id
== 0x8393)
1673 return rtl839x_write_sds_phy(mii_id
, regnum
, value
);
1675 return rtl839x_write_phy(mii_id
, 0, regnum
, value
);
1678 static int rtl930x_mdio_write(struct mii_bus
*bus
, int mii_id
,
1679 int regnum
, u16 value
)
1681 // struct rtl838x_eth_priv *priv = bus->priv;
1683 // if (mii_id >= 48 && mii_id <= 49 && priv->id == 0x8393)
1684 // return rtl839x_write_sds_phy(mii_id, regnum, value);
1685 if (regnum
& MII_ADDR_C45
) {
1686 regnum
&= ~MII_ADDR_C45
;
1687 return rtl930x_write_mmd_phy(mii_id
, regnum
>> 16, regnum
& 0xffff, value
);
1690 return rtl930x_write_phy(mii_id
, 0, regnum
, value
);
1693 static int rtl931x_mdio_write(struct mii_bus
*bus
, int mii_id
,
1694 int regnum
, u16 value
)
1696 // struct rtl838x_eth_priv *priv = bus->priv;
1698 // if (mii_id >= 48 && mii_id <= 49 && priv->id == 0x8393)
1699 // return rtl839x_write_sds_phy(mii_id, regnum, value);
1701 return rtl931x_write_phy(mii_id
, 0, regnum
, value
);
1704 static int rtl838x_mdio_reset(struct mii_bus
*bus
)
1706 pr_debug("%s called\n", __func__
);
1707 /* Disable MAC polling the PHY so that we can start configuration */
1708 sw_w32(0x00000000, RTL838X_SMI_POLL_CTRL
);
1710 /* Enable PHY control via SoC */
1711 sw_w32_mask(0, 1 << 15, RTL838X_SMI_GLB_CTRL
);
1713 // Probably should reset all PHYs here...
1717 static int rtl839x_mdio_reset(struct mii_bus
*bus
)
1721 pr_debug("%s called\n", __func__
);
1722 /* BUG: The following does not work, but should! */
1723 /* Disable MAC polling the PHY so that we can start configuration */
1724 sw_w32(0x00000000, RTL839X_SMI_PORT_POLLING_CTRL
);
1725 sw_w32(0x00000000, RTL839X_SMI_PORT_POLLING_CTRL
+ 4);
1726 /* Disable PHY polling via SoC */
1727 sw_w32_mask(1 << 7, 0, RTL839X_SMI_GLB_CTRL
);
1729 // Probably should reset all PHYs here...
1733 static int rtl931x_mdio_reset(struct mii_bus
*bus
)
1735 sw_w32(0x00000000, RTL931X_SMI_PORT_POLLING_CTRL
);
1736 sw_w32(0x00000000, RTL931X_SMI_PORT_POLLING_CTRL
+ 4);
1738 pr_debug("%s called\n", __func__
);
1743 static int rtl930x_mdio_reset(struct mii_bus
*bus
)
1748 pr_info("RTL930X_SMI_PORT0_15_POLLING_SEL %08x 16-27: %08x\n",
1749 sw_r32(RTL930X_SMI_PORT0_15_POLLING_SEL
),
1750 sw_r32(RTL930X_SMI_PORT16_27_POLLING_SEL
));
1752 pr_info("%s: Enable SMI polling on SMI bus 0, SMI1, SMI2, disable on SMI3\n", __func__
);
1753 sw_w32_mask(BIT(20) | BIT(21) | BIT(22), BIT(23), RTL930X_SMI_GLB_CTRL
);
1755 pr_info("RTL9300 Powering on SerDes ports\n");
1756 rtl9300_sds_power(24, 1);
1757 rtl9300_sds_power(25, 1);
1758 rtl9300_sds_power(26, 1);
1759 rtl9300_sds_power(27, 1);
1762 // RTL930X_SMI_PORT0_15_POLLING_SEL 55550000 16-27: 00f9aaaa
1763 // i.e SMI=0 for all ports
1764 for (i
= 0; i
< 5; i
++)
1765 pr_info("port phy: %08x\n", sw_r32(RTL930X_SMI_PORT0_5_ADDR
+ i
*4));
1767 // 1-to-1 mapping of port to phy-address
1768 for (i
= 0; i
< 24; i
++) {
1770 sw_w32_mask(0x1f << pos
, i
<< pos
, RTL930X_SMI_PORT0_5_ADDR
+ (i
/ 6) * 4);
1773 // ports 24 and 25 have PHY addresses 8 and 9, ports 26/27 PHY 26/27
1774 sw_w32(8 | 9 << 5 | 26 << 10 | 27 << 15, RTL930X_SMI_PORT0_5_ADDR
+ 4 * 4);
1776 // Ports 24 and 25 live on SMI bus 1 and 2
1777 sw_w32_mask(0x3 << 16, 0x1 << 16, RTL930X_SMI_PORT16_27_POLLING_SEL
);
1778 sw_w32_mask(0x3 << 18, 0x2 << 18, RTL930X_SMI_PORT16_27_POLLING_SEL
);
1780 // SMI bus 1 and 2 speak Clause 45 TODO: Configure from .dts
1781 sw_w32_mask(0, BIT(17) | BIT(18), RTL930X_SMI_GLB_CTRL
);
1783 // Ports 24 and 25 are 2.5 Gig, set this type (1)
1784 sw_w32_mask(0x7 << 12, 1 << 12, RTL930X_SMI_MAC_TYPE_CTRL
);
1785 sw_w32_mask(0x7 << 15, 1 << 15, RTL930X_SMI_MAC_TYPE_CTRL
);
1790 static int rtl838x_mdio_init(struct rtl838x_eth_priv
*priv
)
1792 struct device_node
*mii_np
;
1795 pr_debug("%s called\n", __func__
);
1796 mii_np
= of_get_child_by_name(priv
->pdev
->dev
.of_node
, "mdio-bus");
1799 dev_err(&priv
->pdev
->dev
, "no %s child node found", "mdio-bus");
1803 if (!of_device_is_available(mii_np
)) {
1808 priv
->mii_bus
= devm_mdiobus_alloc(&priv
->pdev
->dev
);
1809 if (!priv
->mii_bus
) {
1814 switch(priv
->family_id
) {
1815 case RTL8380_FAMILY_ID
:
1816 priv
->mii_bus
->name
= "rtl838x-eth-mdio";
1817 priv
->mii_bus
->read
= rtl838x_mdio_read
;
1818 priv
->mii_bus
->write
= rtl838x_mdio_write
;
1819 priv
->mii_bus
->reset
= rtl838x_mdio_reset
;
1821 case RTL8390_FAMILY_ID
:
1822 priv
->mii_bus
->name
= "rtl839x-eth-mdio";
1823 priv
->mii_bus
->read
= rtl839x_mdio_read
;
1824 priv
->mii_bus
->write
= rtl839x_mdio_write
;
1825 priv
->mii_bus
->reset
= rtl839x_mdio_reset
;
1827 case RTL9300_FAMILY_ID
:
1828 priv
->mii_bus
->name
= "rtl930x-eth-mdio";
1829 priv
->mii_bus
->read
= rtl930x_mdio_read
;
1830 priv
->mii_bus
->write
= rtl930x_mdio_write
;
1831 priv
->mii_bus
->reset
= rtl930x_mdio_reset
;
1832 // priv->mii_bus->probe_capabilities = MDIOBUS_C22_C45; TODO for linux 5.9
1834 case RTL9310_FAMILY_ID
:
1835 priv
->mii_bus
->name
= "rtl931x-eth-mdio";
1836 priv
->mii_bus
->read
= rtl931x_mdio_read
;
1837 priv
->mii_bus
->write
= rtl931x_mdio_write
;
1838 priv
->mii_bus
->reset
= rtl931x_mdio_reset
;
1839 // priv->mii_bus->probe_capabilities = MDIOBUS_C22_C45; TODO for linux 5.9
1842 priv
->mii_bus
->priv
= priv
;
1843 priv
->mii_bus
->parent
= &priv
->pdev
->dev
;
1845 snprintf(priv
->mii_bus
->id
, MII_BUS_ID_SIZE
, "%pOFn", mii_np
);
1846 ret
= of_mdiobus_register(priv
->mii_bus
, mii_np
);
1849 of_node_put(mii_np
);
1853 static int rtl838x_mdio_remove(struct rtl838x_eth_priv
*priv
)
1855 pr_debug("%s called\n", __func__
);
1859 mdiobus_unregister(priv
->mii_bus
);
1860 mdiobus_free(priv
->mii_bus
);
1865 static netdev_features_t
rtl838x_fix_features(struct net_device
*dev
,
1866 netdev_features_t features
)
1871 static int rtl83xx_set_features(struct net_device
*dev
, netdev_features_t features
)
1873 struct rtl838x_eth_priv
*priv
= netdev_priv(dev
);
1875 if ((features
^ dev
->features
) & NETIF_F_RXCSUM
) {
1876 if (!(features
& NETIF_F_RXCSUM
))
1877 sw_w32_mask(BIT(3), 0, priv
->r
->mac_port_ctrl(priv
->cpu_port
));
1879 sw_w32_mask(0, BIT(4), priv
->r
->mac_port_ctrl(priv
->cpu_port
));
1885 static int rtl93xx_set_features(struct net_device
*dev
, netdev_features_t features
)
1887 struct rtl838x_eth_priv
*priv
= netdev_priv(dev
);
1889 if ((features
^ dev
->features
) & NETIF_F_RXCSUM
) {
1890 if (!(features
& NETIF_F_RXCSUM
))
1891 sw_w32_mask(BIT(4), 0, priv
->r
->mac_port_ctrl(priv
->cpu_port
));
1893 sw_w32_mask(0, BIT(4), priv
->r
->mac_port_ctrl(priv
->cpu_port
));
1899 static const struct net_device_ops rtl838x_eth_netdev_ops
= {
1900 .ndo_open
= rtl838x_eth_open
,
1901 .ndo_stop
= rtl838x_eth_stop
,
1902 .ndo_start_xmit
= rtl838x_eth_tx
,
1903 .ndo_select_queue
= rtl83xx_pick_tx_queue
,
1904 .ndo_set_mac_address
= rtl838x_set_mac_address
,
1905 .ndo_validate_addr
= eth_validate_addr
,
1906 .ndo_set_rx_mode
= rtl838x_eth_set_multicast_list
,
1907 .ndo_tx_timeout
= rtl838x_eth_tx_timeout
,
1908 .ndo_set_features
= rtl83xx_set_features
,
1909 .ndo_fix_features
= rtl838x_fix_features
,
1912 static const struct net_device_ops rtl839x_eth_netdev_ops
= {
1913 .ndo_open
= rtl838x_eth_open
,
1914 .ndo_stop
= rtl838x_eth_stop
,
1915 .ndo_start_xmit
= rtl838x_eth_tx
,
1916 .ndo_select_queue
= rtl83xx_pick_tx_queue
,
1917 .ndo_set_mac_address
= rtl838x_set_mac_address
,
1918 .ndo_validate_addr
= eth_validate_addr
,
1919 .ndo_set_rx_mode
= rtl839x_eth_set_multicast_list
,
1920 .ndo_tx_timeout
= rtl838x_eth_tx_timeout
,
1921 .ndo_set_features
= rtl83xx_set_features
,
1922 .ndo_fix_features
= rtl838x_fix_features
,
1925 static const struct net_device_ops rtl930x_eth_netdev_ops
= {
1926 .ndo_open
= rtl838x_eth_open
,
1927 .ndo_stop
= rtl838x_eth_stop
,
1928 .ndo_start_xmit
= rtl838x_eth_tx
,
1929 .ndo_select_queue
= rtl93xx_pick_tx_queue
,
1930 .ndo_set_mac_address
= rtl838x_set_mac_address
,
1931 .ndo_validate_addr
= eth_validate_addr
,
1932 .ndo_set_rx_mode
= rtl930x_eth_set_multicast_list
,
1933 .ndo_tx_timeout
= rtl838x_eth_tx_timeout
,
1934 .ndo_set_features
= rtl93xx_set_features
,
1935 .ndo_fix_features
= rtl838x_fix_features
,
1938 static const struct net_device_ops rtl931x_eth_netdev_ops
= {
1939 .ndo_open
= rtl838x_eth_open
,
1940 .ndo_stop
= rtl838x_eth_stop
,
1941 .ndo_start_xmit
= rtl838x_eth_tx
,
1942 .ndo_select_queue
= rtl93xx_pick_tx_queue
,
1943 .ndo_set_mac_address
= rtl838x_set_mac_address
,
1944 .ndo_validate_addr
= eth_validate_addr
,
1945 .ndo_set_rx_mode
= rtl931x_eth_set_multicast_list
,
1946 .ndo_tx_timeout
= rtl838x_eth_tx_timeout
,
1947 .ndo_set_features
= rtl93xx_set_features
,
1948 .ndo_fix_features
= rtl838x_fix_features
,
1951 static const struct phylink_mac_ops rtl838x_phylink_ops
= {
1952 .validate
= rtl838x_validate
,
1953 .mac_link_state
= rtl838x_mac_pcs_get_state
,
1954 .mac_an_restart
= rtl838x_mac_an_restart
,
1955 .mac_config
= rtl838x_mac_config
,
1956 .mac_link_down
= rtl838x_mac_link_down
,
1957 .mac_link_up
= rtl838x_mac_link_up
,
1960 static const struct ethtool_ops rtl838x_ethtool_ops
= {
1961 .get_link_ksettings
= rtl838x_get_link_ksettings
,
1962 .set_link_ksettings
= rtl838x_set_link_ksettings
,
1965 static int __init
rtl838x_eth_probe(struct platform_device
*pdev
)
1967 struct net_device
*dev
;
1968 struct device_node
*dn
= pdev
->dev
.of_node
;
1969 struct rtl838x_eth_priv
*priv
;
1970 struct resource
*res
, *mem
;
1971 phy_interface_t phy_mode
;
1972 struct phylink
*phylink
;
1973 int err
= 0, i
, rxrings
, rxringlen
;
1974 struct ring_b
*ring
;
1976 pr_info("Probing RTL838X eth device pdev: %x, dev: %x\n",
1977 (u32
)pdev
, (u32
)(&(pdev
->dev
)));
1980 dev_err(&pdev
->dev
, "No DT found\n");
1984 rxrings
= (soc_info
.family
== RTL8380_FAMILY_ID
1985 || soc_info
.family
== RTL8390_FAMILY_ID
) ? 8 : 32;
1986 rxrings
= rxrings
> MAX_RXRINGS
? MAX_RXRINGS
: rxrings
;
1987 rxringlen
= MAX_ENTRIES
/ rxrings
;
1988 rxringlen
= rxringlen
> MAX_RXLEN
? MAX_RXLEN
: rxringlen
;
1990 dev
= alloc_etherdev_mqs(sizeof(struct rtl838x_eth_priv
), TXRINGS
, rxrings
);
1995 SET_NETDEV_DEV(dev
, &pdev
->dev
);
1996 priv
= netdev_priv(dev
);
1998 /* obtain buffer memory space */
1999 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
2001 mem
= devm_request_mem_region(&pdev
->dev
, res
->start
,
2002 resource_size(res
), res
->name
);
2004 dev_err(&pdev
->dev
, "cannot request memory space\n");
2009 dev
->mem_start
= mem
->start
;
2010 dev
->mem_end
= mem
->end
;
2012 dev_err(&pdev
->dev
, "cannot request IO resource\n");
2017 /* Allocate buffer memory */
2018 priv
->membase
= dmam_alloc_coherent(&pdev
->dev
, rxrings
* rxringlen
* RING_BUFFER
2019 + sizeof(struct ring_b
) + sizeof(struct notify_b
),
2020 (void *)&dev
->mem_start
, GFP_KERNEL
);
2021 if (!priv
->membase
) {
2022 dev_err(&pdev
->dev
, "cannot allocate DMA buffer\n");
2027 // Allocate ring-buffer space at the end of the allocated memory
2028 ring
= priv
->membase
;
2029 ring
->rx_space
= priv
->membase
+ sizeof(struct ring_b
) + sizeof(struct notify_b
);
2031 spin_lock_init(&priv
->lock
);
2033 /* obtain device IRQ number */
2034 res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, 0);
2036 dev_err(&pdev
->dev
, "cannot obtain IRQ, using default 24\n");
2039 dev
->irq
= res
->start
;
2041 dev
->ethtool_ops
= &rtl838x_ethtool_ops
;
2042 dev
->min_mtu
= ETH_ZLEN
;
2043 dev
->max_mtu
= 1536;
2044 dev
->features
= NETIF_F_RXCSUM
| NETIF_F_HW_CSUM
;
2045 dev
->hw_features
= NETIF_F_RXCSUM
;
2047 priv
->id
= soc_info
.id
;
2048 priv
->family_id
= soc_info
.family
;
2050 pr_info("Found SoC ID: %4x: %s, family %x\n",
2051 priv
->id
, soc_info
.name
, priv
->family_id
);
2053 pr_err("Unknown chip id (%04x)\n", priv
->id
);
2057 switch (priv
->family_id
) {
2058 case RTL8380_FAMILY_ID
:
2059 priv
->cpu_port
= RTL838X_CPU_PORT
;
2060 priv
->r
= &rtl838x_reg
;
2061 dev
->netdev_ops
= &rtl838x_eth_netdev_ops
;
2063 case RTL8390_FAMILY_ID
:
2064 priv
->cpu_port
= RTL839X_CPU_PORT
;
2065 priv
->r
= &rtl839x_reg
;
2066 dev
->netdev_ops
= &rtl839x_eth_netdev_ops
;
2068 case RTL9300_FAMILY_ID
:
2069 priv
->cpu_port
= RTL930X_CPU_PORT
;
2070 priv
->r
= &rtl930x_reg
;
2071 dev
->netdev_ops
= &rtl930x_eth_netdev_ops
;
2073 case RTL9310_FAMILY_ID
:
2074 priv
->cpu_port
= RTL931X_CPU_PORT
;
2075 priv
->r
= &rtl931x_reg
;
2076 dev
->netdev_ops
= &rtl931x_eth_netdev_ops
;
2079 pr_err("Unknown SoC family\n");
2082 priv
->rxringlen
= rxringlen
;
2083 priv
->rxrings
= rxrings
;
2085 rtl8380_init_mac(priv
);
2087 /* try to get mac address in the following order:
2088 * 1) from device tree data
2089 * 2) from internal registers set by bootloader
2091 of_get_mac_address(pdev
->dev
.of_node
, dev
->dev_addr
);
2092 if (is_valid_ether_addr(dev
->dev_addr
))) {
2093 rtl838x_set_mac_hw(dev
, (u8
*)dev
->dev_addr
);
2095 dev
->dev_addr
[0] = (sw_r32(priv
->r
->mac
) >> 8) & 0xff;
2096 dev
->dev_addr
[1] = sw_r32(priv
->r
->mac
) & 0xff;
2097 dev
->dev_addr
[2] = (sw_r32(priv
->r
->mac
+ 4) >> 24) & 0xff;
2098 dev
->dev_addr
[3] = (sw_r32(priv
->r
->mac
+ 4) >> 16) & 0xff;
2099 dev
->dev_addr
[4] = (sw_r32(priv
->r
->mac
+ 4) >> 8) & 0xff;
2100 dev
->dev_addr
[5] = sw_r32(priv
->r
->mac
+ 4) & 0xff;
2102 /* if the address is invalid, use a random value */
2103 if (!is_valid_ether_addr(dev
->dev_addr
)) {
2104 struct sockaddr sa
= { AF_UNSPEC
};
2106 netdev_warn(dev
, "Invalid MAC address, using random\n");
2107 eth_hw_addr_random(dev
);
2108 memcpy(sa
.sa_data
, dev
->dev_addr
, ETH_ALEN
);
2109 if (rtl838x_set_mac_address(dev
, &sa
))
2110 netdev_warn(dev
, "Failed to set MAC address.\n");
2112 pr_info("Using MAC %08x%08x\n", sw_r32(priv
->r
->mac
),
2113 sw_r32(priv
->r
->mac
+ 4));
2114 strcpy(dev
->name
, "eth%d");
2118 err
= rtl838x_mdio_init(priv
);
2122 err
= register_netdev(dev
);
2126 for (i
= 0; i
< priv
->rxrings
; i
++) {
2127 priv
->rx_qs
[i
].id
= i
;
2128 priv
->rx_qs
[i
].priv
= priv
;
2129 netif_napi_add(dev
, &priv
->rx_qs
[i
].napi
, rtl838x_poll_rx
, 64);
2132 platform_set_drvdata(pdev
, dev
);
2134 phy_mode
= of_get_phy_mode(dn
);
2136 dev_err(&pdev
->dev
, "incorrect phy-mode\n");
2140 priv
->phylink_config
.dev
= &dev
->dev
;
2141 priv
->phylink_config
.type
= PHYLINK_NETDEV
;
2143 phylink
= phylink_create(&priv
->phylink_config
, pdev
->dev
.fwnode
,
2144 phy_mode
, &rtl838x_phylink_ops
);
2145 if (IS_ERR(phylink
)) {
2146 err
= PTR_ERR(phylink
);
2149 priv
->phylink
= phylink
;
2154 pr_err("Error setting up netdev, freeing it again.\n");
2159 static int rtl838x_eth_remove(struct platform_device
*pdev
)
2161 struct net_device
*dev
= platform_get_drvdata(pdev
);
2162 struct rtl838x_eth_priv
*priv
= netdev_priv(dev
);
2166 pr_info("Removing platform driver for rtl838x-eth\n");
2167 rtl838x_mdio_remove(priv
);
2168 rtl838x_hw_stop(priv
);
2170 netif_tx_stop_all_queues(dev
);
2172 for (i
= 0; i
< priv
->rxrings
; i
++)
2173 netif_napi_del(&priv
->rx_qs
[i
].napi
);
2175 unregister_netdev(dev
);
2181 static const struct of_device_id rtl838x_eth_of_ids
[] = {
2182 { .compatible
= "realtek,rtl838x-eth"},
2185 MODULE_DEVICE_TABLE(of
, rtl838x_eth_of_ids
);
2187 static struct platform_driver rtl838x_eth_driver
= {
2188 .probe
= rtl838x_eth_probe
,
2189 .remove
= rtl838x_eth_remove
,
2191 .name
= "rtl838x-eth",
2193 .of_match_table
= rtl838x_eth_of_ids
,
2197 module_platform_driver(rtl838x_eth_driver
);
2199 MODULE_AUTHOR("B. Koblitz");
2200 MODULE_DESCRIPTION("RTL838X SoC Ethernet Driver");
2201 MODULE_LICENSE("GPL");