1 // SPDX-License-Identifier: GPL-2.0-only
3 * Realtek RTL838X architecture specific IRQ handling
5 * Copyright (C) 2020 B. Koblitz
6 * based on the original BSP
7 * Copyright (C) 2006-2012 Tony Wu (tonywu@realtek.com)
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/interrupt.h>
14 #include <linux/irqchip.h>
15 #include <linux/of_irq.h>
16 #include <linux/of_address.h>
17 #include <linux/spinlock.h>
19 #include <asm/irq_cpu.h>
20 #include <asm/mipsregs.h>
21 #include <mach-rtl838x.h>
23 extern struct rtl838x_soc_info soc_info
;
25 #define icu_r32(reg) rtl838x_r32(soc_info.icu_base + reg)
26 #define icu_w32(val, reg) rtl838x_w32(val, soc_info.icu_base + reg)
27 #define icu_w32_mask(clear, set, reg) rtl838x_w32_mask(clear, set, soc_info.icu_base + reg)
29 static DEFINE_RAW_SPINLOCK(irq_lock
);
31 extern irqreturn_t
c0_compare_interrupt(int irq
, void *dev_id
);
32 unsigned int rtl838x_ictl_irq_dispatch1(void);
33 unsigned int rtl838x_ictl_irq_dispatch2(void);
34 unsigned int rtl838x_ictl_irq_dispatch3(void);
35 unsigned int rtl838x_ictl_irq_dispatch4(void);
36 unsigned int rtl838x_ictl_irq_dispatch5(void);
38 static struct irqaction irq_cascade1
= {
40 .name
= "RTL838X IRQ cascade1",
43 static struct irqaction irq_cascade2
= {
45 .name
= "RTL838X IRQ cascade2",
48 static struct irqaction irq_cascade3
= {
50 .name
= "RTL838X IRQ cascade3",
53 static struct irqaction irq_cascade4
= {
55 .name
= "RTL838X IRQ cascade4",
58 static struct irqaction irq_cascade5
= {
60 .name
= "RTL838X IRQ cascade5",
63 static void rtl838x_ictl_enable_irq(struct irq_data
*i
)
67 raw_spin_lock_irqsave(&irq_lock
, flags
);
68 icu_w32_mask(0, 1 << i
->irq
, GIMR
);
69 raw_spin_unlock_irqrestore(&irq_lock
, flags
);
72 static unsigned int rtl838x_ictl_startup_irq(struct irq_data
*i
)
74 rtl838x_ictl_enable_irq(i
);
78 static void rtl838x_ictl_disable_irq(struct irq_data
*i
)
82 raw_spin_lock_irqsave(&irq_lock
, flags
);
83 icu_w32_mask(1 << i
->irq
, 0, GIMR
);
84 raw_spin_unlock_irqrestore(&irq_lock
, flags
);
87 static void rtl838x_ictl_eoi_irq(struct irq_data
*i
)
91 raw_spin_lock_irqsave(&irq_lock
, flags
);
92 icu_w32_mask(0, 1 << i
->irq
, GIMR
);
93 raw_spin_unlock_irqrestore(&irq_lock
, flags
);
96 static struct irq_chip rtl838x_ictl_irq
= {
98 .irq_startup
= rtl838x_ictl_startup_irq
,
99 .irq_shutdown
= rtl838x_ictl_disable_irq
,
100 .irq_enable
= rtl838x_ictl_enable_irq
,
101 .irq_disable
= rtl838x_ictl_disable_irq
,
102 .irq_ack
= rtl838x_ictl_disable_irq
,
103 .irq_mask
= rtl838x_ictl_disable_irq
,
104 .irq_unmask
= rtl838x_ictl_enable_irq
,
105 .irq_eoi
= rtl838x_ictl_eoi_irq
,
109 * RTL8390/80/28 Interrupt Scheme
112 * -------- ------- -------
125 unsigned int rtl838x_ictl_irq_dispatch1(void)
127 /* Identify shared IRQ */
128 unsigned int extint_ip
= icu_r32(GIMR
) & icu_r32(GISR
);
130 if (extint_ip
& TC1_IP
)
132 else if (extint_ip
& UART1_IP
)
135 spurious_interrupt();
140 unsigned int rtl838x_ictl_irq_dispatch2(void)
146 unsigned int rtl838x_ictl_irq_dispatch3(void)
152 unsigned int rtl838x_ictl_irq_dispatch4(void)
154 /* Identify shared IRQ */
155 unsigned int extint_ip
= icu_r32(GIMR
) & icu_r32(GISR
);
157 if (extint_ip
& NIC_IP
)
159 else if (extint_ip
& GPIO_ABCD_IP
)
160 do_IRQ(GPIO_ABCD_IRQ
);
161 else if ((extint_ip
& GPIO_EFGH_IP
) && (soc_info
.family
== RTL8328_FAMILY_ID
))
162 do_IRQ(GPIO_EFGH_IRQ
);
164 spurious_interrupt();
169 unsigned int rtl838x_ictl_irq_dispatch5(void)
175 asmlinkage
void plat_irq_dispatch(void)
177 unsigned int pending
;
179 pending
= read_c0_cause() & read_c0_status() & ST0_IM
;
181 if (pending
& CAUSEF_IP7
)
182 c0_compare_interrupt(7, NULL
);
183 else if (pending
& CAUSEF_IP6
)
184 rtl838x_ictl_irq_dispatch5();
185 else if (pending
& CAUSEF_IP5
)
186 rtl838x_ictl_irq_dispatch4();
187 else if (pending
& CAUSEF_IP4
)
188 rtl838x_ictl_irq_dispatch3();
189 else if (pending
& CAUSEF_IP3
)
190 rtl838x_ictl_irq_dispatch2();
191 else if (pending
& CAUSEF_IP2
)
192 rtl838x_ictl_irq_dispatch1();
194 spurious_interrupt();
197 static void __init
rtl838x_ictl_irq_init(unsigned int irq_base
)
201 for (i
= 0; i
< RTL838X_IRQ_ICTL_NUM
; i
++)
202 irq_set_chip_and_handler(irq_base
+ i
, &rtl838x_ictl_irq
, handle_level_irq
);
204 setup_irq(RTL838X_ICTL1_IRQ
, &irq_cascade1
);
205 setup_irq(RTL838X_ICTL2_IRQ
, &irq_cascade2
);
206 setup_irq(RTL838X_ICTL3_IRQ
, &irq_cascade3
);
207 setup_irq(RTL838X_ICTL4_IRQ
, &irq_cascade4
);
208 setup_irq(RTL838X_ICTL5_IRQ
, &irq_cascade5
);
211 icu_w32(TC0_IE
| UART0_IE
, GIMR
);
212 icu_w32(IRR0_SETTING
, IRR0
);
213 icu_w32(IRR1_SETTING
, IRR1
);
214 icu_w32(IRR2_SETTING
, IRR2
);
215 icu_w32(IRR3_SETTING
, IRR3
);
218 static int intc_map(struct irq_domain
*d
, unsigned int irq
, irq_hw_number_t hw
)
220 irq_set_chip_and_handler(hw
, &rtl838x_ictl_irq
, handle_level_irq
);
225 static const struct irq_domain_ops irq_domain_ops
= {
226 .xlate
= irq_domain_xlate_onecell
,
230 int __init
icu_of_init(struct device_node
*node
, struct device_node
*parent
)
233 struct irq_domain
*domain
;
236 pr_info("Found Interrupt controller: %s (%s)\n", node
->name
, node
->full_name
);
237 if (of_address_to_resource(node
, 0, &res
)) {
238 panic("Failed to get icu memory range");
240 if (!request_mem_region(res
.start
, resource_size(&res
), res
.name
))
241 pr_err("Failed to request icu memory\n");
242 soc_info
.icu_base
= ioremap(res
.start
, resource_size(&res
));
243 pr_info("ICU Memory: %08x\n", (u32
)soc_info
.icu_base
);
247 domain
= irq_domain_add_simple(node
, 32, 0, &irq_domain_ops
, NULL
);
249 /* Setup all external HW irqs */
250 for (i
= 8; i
< 32; i
++)
251 irq_domain_associate(domain
, i
, i
);
253 rtl838x_ictl_irq_init(RTL838X_IRQ_ICTL_BASE
);
257 void __init
arch_init_irq(void)
259 /* do board-specific irq initialization */
263 IRQCHIP_DECLARE(mips_cpu_intc
, "rtl838x,icu", icu_of_init
);