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rtl838x: add new architecture
[openwrt/staging/ynezz.git] / target / linux / rtl838x / files-5.4 / drivers / mtd / spi-nor / rtl838x-nor.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <linux/device.h>
4 #include <linux/init.h>
5 #include <linux/module.h>
6 #include <linux/mutex.h>
7 #include <linux/of.h>
8 #include <linux/of_device.h>
9 #include <linux/platform_device.h>
10 #include <linux/slab.h>
11 #include <linux/mtd/mtd.h>
12 #include <linux/mtd/partitions.h>
13 #include <linux/mtd/spi-nor.h>
14
15 #include "rtl838x-spi.h"
16 #include <asm/mach-rtl838x/mach-rtl838x.h>
17
18 extern struct rtl838x_soc_info soc_info;
19
20 struct rtl838x_nor {
21 struct spi_nor nor;
22 struct device *dev;
23 volatile void __iomem *base;
24 bool fourByteMode;
25 u32 chipSize;
26 uint32_t flags;
27 uint32_t io_status;
28 };
29
30 static uint32_t spi_prep(struct rtl838x_nor *rtl838x_nor)
31 {
32 /* Needed because of MMU constraints */
33 SPI_WAIT_READY;
34 spi_w32w(SPI_CS_INIT, SFCSR); //deactivate CS0, CS1
35 spi_w32w(0, SFCSR); //activate CS0,CS1
36 spi_w32w(SPI_CS_INIT, SFCSR); //deactivate CS0, CS1
37
38 return (CS0 & rtl838x_nor->flags) ? (SPI_eCS0 & SPI_LEN_INIT)
39 : ((SPI_eCS1 & SPI_LEN_INIT) | SFCSR_CHIP_SEL);
40 }
41
42 static uint32_t rtl838x_nor_get_SR(struct rtl838x_nor *rtl838x_nor)
43 {
44 uint32_t sfcsr, sfdr;
45
46 sfcsr = spi_prep(rtl838x_nor);
47 sfdr = (SPINOR_OP_RDSR)<<24;
48
49 pr_debug("%s: rdid,sfcsr_val = %.8x,SFDR = %.8x\n", __func__, sfcsr, sfdr);
50 pr_debug("rdid,sfcsr = %.8x\n", sfcsr | SPI_LEN4);
51 spi_w32w(sfcsr, SFCSR);
52 spi_w32w(sfdr, SFDR);
53 spi_w32_mask(0, SPI_LEN4, SFCSR);
54 SPI_WAIT_READY;
55
56 return spi_r32(SFDR);
57 }
58
59 static void spi_write_disable(struct rtl838x_nor *rtl838x_nor)
60 {
61 uint32_t sfcsr, sfdr;
62
63 sfcsr = spi_prep(rtl838x_nor);
64 sfdr = (SPINOR_OP_WRDI) << 24;
65 spi_w32w(sfcsr, SFCSR);
66 spi_w32w(sfdr, SFDR);
67 pr_debug("%s: sfcsr_val = %.8x,SFDR = %.8x", __func__, sfcsr, sfdr);
68
69 spi_prep(rtl838x_nor);
70 }
71
72 static void spi_write_enable(struct rtl838x_nor *rtl838x_nor)
73 {
74 uint32_t sfcsr, sfdr;
75
76 sfcsr = spi_prep(rtl838x_nor);
77 sfdr = (SPINOR_OP_WREN) << 24;
78 spi_w32w(sfcsr, SFCSR);
79 spi_w32w(sfdr, SFDR);
80 pr_debug("%s: sfcsr_val = %.8x,SFDR = %.8x", __func__, sfcsr, sfdr);
81
82 spi_prep(rtl838x_nor);
83 }
84
85 static void spi_4b_set(struct rtl838x_nor *rtl838x_nor, bool enable)
86 {
87 uint32_t sfcsr, sfdr;
88
89 sfcsr = spi_prep(rtl838x_nor);
90 if (enable)
91 sfdr = (SPINOR_OP_EN4B) << 24;
92 else
93 sfdr = (SPINOR_OP_EX4B) << 24;
94
95 spi_w32w(sfcsr, SFCSR);
96 spi_w32w(sfdr, SFDR);
97 pr_debug("%s: sfcsr_val = %.8x,SFDR = %.8x", __func__, sfcsr, sfdr);
98
99 spi_prep(rtl838x_nor);
100 }
101
102 static int rtl838x_get_addr_mode(struct rtl838x_nor *rtl838x_nor)
103 {
104 int res = 3;
105 u32 reg;
106
107 sw_w32(0x3, RTL838X_INT_RW_CTRL);
108 if (!sw_r32(RTL838X_EXT_VERSION)) {
109 if (sw_r32(RTL838X_STRAP_DBG) & (1 << 29))
110 res = 4;
111 } else {
112 reg = sw_r32(RTL838X_PLL_CML_CTRL);
113 if ((reg & (1 << 30)) && (reg & (1 << 31)))
114 res = 4;
115 if ((!(reg & (1 << 30)))
116 && sw_r32(RTL838X_STRAP_DBG) & (1 << 29))
117 res = 4;
118 }
119 sw_w32(0x0, RTL838X_INT_RW_CTRL);
120 return res;
121 }
122
123 static int rtl8390_get_addr_mode(struct rtl838x_nor *rtl838x_nor)
124 {
125 if (spi_r32(RTL8390_SOC_SPI_MMIO_CONF) & (1 << 9))
126 return 4;
127 return 3;
128 }
129
130 ssize_t rtl838x_do_read(struct rtl838x_nor *rtl838x_nor, loff_t from,
131 size_t length, u_char *buffer, uint8_t command)
132 {
133 uint32_t sfcsr, sfdr;
134 uint32_t len = length;
135
136 sfcsr = spi_prep(rtl838x_nor);
137 sfdr = command << 24;
138
139 /* Perform SPINOR_OP_READ: 1 byte command & 3 byte addr*/
140 sfcsr |= SPI_LEN4;
141 sfdr |= from;
142
143 spi_w32w(sfcsr, SFCSR);
144 spi_w32w(sfdr, SFDR);
145
146 /* Read Data, 4 bytes at a time */
147 while (length >= 4) {
148 SPI_WAIT_READY;
149 *((uint32_t *) buffer) = spi_r32(SFDR);
150 /* printk("%.8x ", *((uint32_t*) buffer)); */
151 buffer += 4;
152 length -= 4;
153 }
154
155 /* The rest needs to be read 1 byte a time */
156 sfcsr &= SPI_LEN_INIT|SPI_LEN1;
157 SPI_WAIT_READY;
158 spi_w32w(sfcsr, SFCSR);
159 while (length > 0) {
160 SPI_WAIT_READY;
161 *(buffer) = spi_r32(SFDR) >> 24;
162 /* printk("%.2x ", *(buffer)); */
163 buffer++;
164 length--;
165 }
166 return len;
167 }
168
169 /*
170 * Do fast read in 3 or 4 Byte addressing mode
171 */
172 static ssize_t rtl838x_do_4bf_read(struct rtl838x_nor *rtl838x_nor, loff_t from,
173 size_t length, u_char *buffer, uint8_t command)
174 {
175 int sfcsr_addr_len = rtl838x_nor->fourByteMode ? 0x3 : 0x2;
176 int sfdr_addr_shift = rtl838x_nor->fourByteMode ? 0 : 8;
177 uint32_t sfcsr;
178 uint32_t len = length;
179
180 pr_debug("Fast read from %llx, len %x, shift %d\n",
181 from, sfcsr_addr_len, sfdr_addr_shift);
182 sfcsr = spi_prep(rtl838x_nor);
183
184 /* Send read command */
185 spi_w32w(sfcsr | SPI_LEN1, SFCSR);
186 spi_w32w(command << 24, SFDR);
187
188 /* Send address */
189 spi_w32w(sfcsr | (sfcsr_addr_len << 28), SFCSR);
190 spi_w32w(from << sfdr_addr_shift, SFDR);
191
192 /* Dummy cycles */
193 spi_w32w(sfcsr | SPI_LEN1, SFCSR);
194 spi_w32w(0, SFDR);
195
196 /* Start reading */
197 spi_w32w(sfcsr | SPI_LEN4, SFCSR);
198
199 /* Read Data, 4 bytes at a time */
200 while (length >= 4) {
201 SPI_WAIT_READY;
202 *((uint32_t *) buffer) = spi_r32(SFDR);
203 /* printk("%.8x ", *((uint32_t*) buffer)); */
204 buffer += 4;
205 length -= 4;
206 }
207
208 /* The rest needs to be read 1 byte a time */
209 sfcsr &= SPI_LEN_INIT|SPI_LEN1;
210 SPI_WAIT_READY;
211 spi_w32w(sfcsr, SFCSR);
212 while (length > 0) {
213 SPI_WAIT_READY;
214 *(buffer) = spi_r32(SFDR) >> 24;
215 /* printk("%.2x ", *(buffer)); */
216 buffer++;
217 length--;
218 }
219 return len;
220
221 }
222
223 /*
224 * Do write (Page Programming) in 3 or 4 Byte addressing mode
225 */
226 static ssize_t rtl838x_do_4b_write(struct rtl838x_nor *rtl838x_nor, loff_t to,
227 size_t length, const u_char *buffer,
228 uint8_t command)
229 {
230 int sfcsr_addr_len = rtl838x_nor->fourByteMode ? 0x3 : 0x2;
231 int sfdr_addr_shift = rtl838x_nor->fourByteMode ? 0 : 8;
232 uint32_t sfcsr;
233 uint32_t len = length;
234
235 pr_debug("Write to %llx, len %x, shift %d\n",
236 to, sfcsr_addr_len, sfdr_addr_shift);
237 sfcsr = spi_prep(rtl838x_nor);
238
239 /* Send write command, command IO-width is 1 (bit 25/26) */
240 spi_w32w(sfcsr | SPI_LEN1 | (0 << 25), SFCSR);
241 spi_w32w(command << 24, SFDR);
242
243 /* Send address */
244 spi_w32w(sfcsr | (sfcsr_addr_len << 28) | (0 << 25), SFCSR);
245 spi_w32w(to << sfdr_addr_shift, SFDR);
246
247 /* Write Data, 1 byte at a time, if we are not 4-byte aligned */
248 if (((long)buffer) % 4) {
249 spi_w32w(sfcsr | SPI_LEN1, SFCSR);
250 while (length > 0 && (((long)buffer) % 4)) {
251 SPI_WAIT_READY;
252 spi_w32(*(buffer) << 24, SFDR);
253 buffer += 1;
254 length -= 1;
255 }
256 }
257
258 /* Now we can write 4 bytes at a time */
259 SPI_WAIT_READY;
260 spi_w32w(sfcsr | SPI_LEN4, SFCSR);
261 while (length >= 4) {
262 SPI_WAIT_READY;
263 spi_w32(*((uint32_t *)buffer), SFDR);
264 buffer += 4;
265 length -= 4;
266 }
267
268 /* Final bytes might need to be written 1 byte at a time, again */
269 SPI_WAIT_READY;
270 spi_w32w(sfcsr | SPI_LEN1, SFCSR);
271 while (length > 0) {
272 SPI_WAIT_READY;
273 spi_w32(*(buffer) << 24, SFDR);
274 buffer++;
275 length--;
276 }
277 return len;
278 }
279
280 static ssize_t rtl838x_nor_write(struct spi_nor *nor, loff_t to, size_t len,
281 const u_char *buffer)
282 {
283 int ret = 0;
284 uint32_t offset = 0;
285 struct rtl838x_nor *rtl838x_nor = nor->priv;
286 size_t l = len;
287 uint8_t cmd = SPINOR_OP_PP;
288
289 /* Do write in 4-byte mode on large Macronix chips */
290 if (rtl838x_nor->fourByteMode) {
291 cmd = SPINOR_OP_PP_4B;
292 spi_4b_set(rtl838x_nor, true);
293 }
294
295 pr_debug("In %s %8x to: %llx\n", __func__,
296 (unsigned int) rtl838x_nor, to);
297
298 while (l >= SPI_MAX_TRANSFER_SIZE) {
299 while
300 (rtl838x_nor_get_SR(rtl838x_nor) & SPI_WIP);
301 do {
302 spi_write_enable(rtl838x_nor);
303 } while (!(rtl838x_nor_get_SR(rtl838x_nor) & SPI_WEL));
304 ret = rtl838x_do_4b_write(rtl838x_nor, to + offset,
305 SPI_MAX_TRANSFER_SIZE, buffer+offset, cmd);
306 l -= SPI_MAX_TRANSFER_SIZE;
307 offset += SPI_MAX_TRANSFER_SIZE;
308 }
309
310 if (l > 0) {
311 while
312 (rtl838x_nor_get_SR(rtl838x_nor) & SPI_WIP);
313 do {
314 spi_write_enable(rtl838x_nor);
315 } while (!(rtl838x_nor_get_SR(rtl838x_nor) & SPI_WEL));
316 ret = rtl838x_do_4b_write(rtl838x_nor, to+offset,
317 len, buffer+offset, cmd);
318 }
319
320 return len;
321 }
322
323 static ssize_t rtl838x_nor_read(struct spi_nor *nor, loff_t from,
324 size_t length, u_char *buffer)
325 {
326 uint32_t offset = 0;
327 uint8_t cmd = SPINOR_OP_READ_FAST;
328 size_t l = length;
329 struct rtl838x_nor *rtl838x_nor = nor->priv;
330
331 /* Do fast read in 3, or 4-byte mode on large Macronix chips */
332 if (rtl838x_nor->fourByteMode) {
333 cmd = SPINOR_OP_READ_FAST_4B;
334 spi_4b_set(rtl838x_nor, true);
335 }
336
337 /* TODO: do timeout and return error */
338 pr_debug("Waiting for pending writes\n");
339 while
340 (rtl838x_nor_get_SR(rtl838x_nor) & SPI_WIP);
341 do {
342 spi_write_enable(rtl838x_nor);
343 } while (!(rtl838x_nor_get_SR(rtl838x_nor) & SPI_WEL));
344
345 pr_debug("cmd is %d\n", cmd);
346 pr_debug("%s: addr %.8llx to addr %.8x, cmd %.8x, size %d\n", __func__,
347 from, (u32)buffer, (u32)cmd, length);
348
349 while (l >= SPI_MAX_TRANSFER_SIZE) {
350 rtl838x_do_4bf_read(rtl838x_nor, from + offset,
351 SPI_MAX_TRANSFER_SIZE, buffer+offset, cmd);
352 l -= SPI_MAX_TRANSFER_SIZE;
353 offset += SPI_MAX_TRANSFER_SIZE;
354 }
355
356 if (l > 0)
357 rtl838x_do_4bf_read(rtl838x_nor, from + offset, l, buffer+offset, cmd);
358
359 return length;
360 }
361
362 static int rtl838x_erase(struct spi_nor *nor, loff_t offs)
363 {
364 struct rtl838x_nor *rtl838x_nor = nor->priv;
365 int sfcsr_addr_len = rtl838x_nor->fourByteMode ? 0x3 : 0x2;
366 int sfdr_addr_shift = rtl838x_nor->fourByteMode ? 0 : 8;
367 uint32_t sfcsr;
368 uint8_t cmd = SPINOR_OP_SE;
369
370 pr_debug("Erasing sector at %llx\n", offs);
371
372 /* Do erase in 4-byte mode on large Macronix chips */
373 if (rtl838x_nor->fourByteMode) {
374 cmd = SPINOR_OP_SE_4B;
375 spi_4b_set(rtl838x_nor, true);
376 }
377 /* TODO: do timeout and return error */
378 while
379 (rtl838x_nor_get_SR(rtl838x_nor) & SPI_WIP);
380 do {
381 spi_write_enable(rtl838x_nor);
382 } while (!(rtl838x_nor_get_SR(rtl838x_nor) & SPI_WEL));
383
384 sfcsr = spi_prep(rtl838x_nor);
385
386 /* Send erase command, command IO-width is 1 (bit 25/26) */
387 spi_w32w(sfcsr | SPI_LEN1 | (0 << 25), SFCSR);
388 spi_w32w(cmd << 24, SFDR);
389
390 /* Send address */
391 spi_w32w(sfcsr | (sfcsr_addr_len << 28) | (0 << 25), SFCSR);
392 spi_w32w(offs << sfdr_addr_shift, SFDR);
393
394 return 0;
395 }
396
397 static int rtl838x_nor_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
398 {
399 int length = len;
400 u8 *buffer = buf;
401 uint32_t sfcsr, sfdr;
402 struct rtl838x_nor *rtl838x_nor = nor->priv;
403
404 pr_debug("In %s: opcode %x, len %x\n", __func__, opcode, len);
405
406 sfcsr = spi_prep(rtl838x_nor);
407 sfdr = opcode << 24;
408
409 sfcsr |= SPI_LEN1;
410
411 spi_w32w(sfcsr, SFCSR);
412 spi_w32w(sfdr, SFDR);
413
414 while (length > 0) {
415 SPI_WAIT_READY;
416 *(buffer) = spi_r32(SFDR) >> 24;
417 buffer++;
418 length--;
419 }
420
421 return len;
422 }
423
424 static int rtl838x_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
425 {
426 uint32_t sfcsr, sfdr;
427 struct rtl838x_nor *rtl838x_nor = nor->priv;
428
429 pr_debug("In %s, opcode %x, len %x\n", __func__, opcode, len);
430 sfcsr = spi_prep(rtl838x_nor);
431 sfdr = opcode << 24;
432
433 if (len == 1) { /* SPINOR_OP_WRSR */
434 sfdr |= buf[0];
435 sfcsr |= SPI_LEN2;
436 }
437 spi_w32w(sfcsr, SFCSR);
438 spi_w32w(sfdr, SFDR);
439 return 0;
440 }
441
442 static int spi_enter_sio(struct spi_nor *nor)
443 {
444 uint32_t sfcsr, sfcr2, sfdr;
445 uint32_t ret = 0, reg = 0, size_bits;
446 struct rtl838x_nor *rtl838x_nor = nor->priv;
447
448 pr_debug("In %s\n", __func__);
449 rtl838x_nor->io_status = 0;
450 sfdr = SPI_C_RSTQIO << 24;
451 sfcsr = spi_prep(rtl838x_nor);
452
453 reg = spi_r32(SFCR2);
454 pr_debug("SFCR2: %x, size %x, rdopt: %x\n", reg, SFCR2_GETSIZE(reg),
455 (reg & SFCR2_RDOPT));
456 size_bits = rtl838x_nor->fourByteMode ? SFCR2_SIZE(0x6) : SFCR2_SIZE(0x7);
457
458 sfcr2 = SFCR2_HOLD_TILL_SFDR2 | size_bits
459 | (reg & SFCR2_RDOPT) | SFCR2_CMDIO(0)
460 | SFCR2_ADDRIO(0) | SFCR2_DUMMYCYCLE(4)
461 | SFCR2_DATAIO(0) | SFCR2_SFCMD(SPINOR_OP_READ_FAST);
462 pr_debug("SFCR2: %x, size %x\n", reg, SFCR2_GETSIZE(reg));
463
464 SPI_WAIT_READY;
465 spi_w32w(sfcr2, SFCR2);
466 spi_w32w(sfcsr, SFCSR);
467 spi_w32w(sfdr, SFDR);
468
469 spi_w32_mask(SFCR2_HOLD_TILL_SFDR2, 0, SFCR2);
470 rtl838x_nor->io_status &= ~IOSTATUS_CIO_MASK;
471 rtl838x_nor->io_status |= CIO1;
472
473 spi_prep(rtl838x_nor);
474
475 return ret;
476 }
477
478 int rtl838x_spi_nor_scan(struct spi_nor *nor, const char *name)
479 {
480 static const struct spi_nor_hwcaps hwcaps = {
481 .mask = SNOR_HWCAPS_READ | SNOR_HWCAPS_PP
482 | SNOR_HWCAPS_READ_FAST
483 };
484
485 struct rtl838x_nor *rtl838x_nor = nor->priv;
486
487 pr_debug("In %s\n", __func__);
488
489 spi_w32_mask(0, SFCR_EnableWBO, SFCR);
490 spi_w32_mask(0, SFCR_EnableRBO, SFCR);
491
492 rtl838x_nor->flags = CS0 | R_MODE;
493
494 spi_nor_scan(nor, NULL, &hwcaps);
495 pr_debug("------------- Got size: %llx\n", nor->mtd.size);
496
497 return 0;
498 }
499
500 int rtl838x_nor_init(struct rtl838x_nor *rtl838x_nor,
501 struct device_node *flash_node)
502 {
503 int ret;
504 struct spi_nor *nor;
505
506 pr_info("%s called\n", __func__);
507 nor = &rtl838x_nor->nor;
508 nor->dev = rtl838x_nor->dev;
509 nor->priv = rtl838x_nor;
510 spi_nor_set_flash_node(nor, flash_node);
511
512 nor->read_reg = rtl838x_nor_read_reg;
513 nor->write_reg = rtl838x_nor_write_reg;
514 nor->read = rtl838x_nor_read;
515 nor->write = rtl838x_nor_write;
516 nor->erase = rtl838x_erase;
517 nor->mtd.name = "rtl838x_nor";
518 nor->erase_opcode = rtl838x_nor->fourByteMode ? SPINOR_OP_SE_4B
519 : SPINOR_OP_SE;
520 /* initialized with NULL */
521 ret = rtl838x_spi_nor_scan(nor, NULL);
522 if (ret)
523 return ret;
524
525 spi_enter_sio(nor);
526 spi_write_disable(rtl838x_nor);
527
528 ret = mtd_device_parse_register(&nor->mtd, NULL, NULL, NULL, 0);
529 return ret;
530 }
531
532 static int rtl838x_nor_drv_probe(struct platform_device *pdev)
533 {
534 struct device_node *flash_np;
535 struct resource *res;
536 int ret;
537 struct rtl838x_nor *rtl838x_nor;
538 int addrMode;
539
540 pr_info("Initializing rtl838x_nor_driver\n");
541 if (!pdev->dev.of_node) {
542 dev_err(&pdev->dev, "No DT found\n");
543 return -EINVAL;
544 }
545
546 rtl838x_nor = devm_kzalloc(&pdev->dev, sizeof(*rtl838x_nor), GFP_KERNEL);
547 if (!rtl838x_nor)
548 return -ENOMEM;
549 platform_set_drvdata(pdev, rtl838x_nor);
550
551 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
552 rtl838x_nor->base = devm_ioremap_resource(&pdev->dev, res);
553 if (IS_ERR((void *)rtl838x_nor->base))
554 return PTR_ERR((void *)rtl838x_nor->base);
555
556 pr_info("SPI resource base is %08x\n", (u32)rtl838x_nor->base);
557 rtl838x_nor->dev = &pdev->dev;
558
559 /* only support one attached flash */
560 flash_np = of_get_next_available_child(pdev->dev.of_node, NULL);
561 if (!flash_np) {
562 dev_err(&pdev->dev, "no SPI flash device to configure\n");
563 ret = -ENODEV;
564 goto nor_free;
565 }
566
567 /* Get the 3/4 byte address mode as configure by bootloader */
568 if (soc_info.family == RTL8390_FAMILY_ID)
569 addrMode = rtl8390_get_addr_mode(rtl838x_nor);
570 else
571 addrMode = rtl838x_get_addr_mode(rtl838x_nor);
572 pr_info("Address mode is %d bytes\n", addrMode);
573 if (addrMode == 4)
574 rtl838x_nor->fourByteMode = true;
575
576 ret = rtl838x_nor_init(rtl838x_nor, flash_np);
577
578 nor_free:
579 return ret;
580 }
581
582 static int rtl838x_nor_drv_remove(struct platform_device *pdev)
583 {
584 /* struct rtl8xx_nor *rtl838x_nor = platform_get_drvdata(pdev); */
585 return 0;
586 }
587
588 static const struct of_device_id rtl838x_nor_of_ids[] = {
589 { .compatible = "realtek,rtl838x-nor"},
590 { /* sentinel */ }
591 };
592 MODULE_DEVICE_TABLE(of, rtl838x_nor_of_ids);
593
594 static struct platform_driver rtl838x_nor_driver = {
595 .probe = rtl838x_nor_drv_probe,
596 .remove = rtl838x_nor_drv_remove,
597 .driver = {
598 .name = "rtl838x-nor",
599 .pm = NULL,
600 .of_match_table = rtl838x_nor_of_ids,
601 },
602 };
603
604 module_platform_driver(rtl838x_nor_driver);
605
606 MODULE_LICENSE("GPL v2");
607 MODULE_DESCRIPTION("RTL838x SPI NOR Flash Driver");
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