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kernel: bump 5.4 to 5.4.80
[openwrt/staging/chunkeey.git] / target / linux / rtl838x / files-5.4 / drivers / mtd / spi-nor / rtl838x-nor.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <linux/device.h>
4 #include <linux/init.h>
5 #include <linux/module.h>
6 #include <linux/mutex.h>
7 #include <linux/of.h>
8 #include <linux/of_device.h>
9 #include <linux/platform_device.h>
10 #include <linux/slab.h>
11 #include <linux/mtd/mtd.h>
12 #include <linux/mtd/partitions.h>
13 #include <linux/mtd/spi-nor.h>
14
15 #include "rtl838x-spi.h"
16 #include <asm/mach-rtl838x/mach-rtl838x.h>
17
18 struct rtl838x_nor {
19 struct spi_nor nor;
20 struct device *dev;
21 volatile void __iomem *base;
22 bool fourByteMode;
23 u32 chipSize;
24 uint32_t flags;
25 uint32_t io_status;
26 };
27
28 static uint32_t spi_prep(struct rtl838x_nor *rtl838x_nor)
29 {
30 /* Needed because of MMU constraints */
31 SPI_WAIT_READY;
32 spi_w32w(SPI_CS_INIT, SFCSR); //deactivate CS0, CS1
33 spi_w32w(0, SFCSR); //activate CS0,CS1
34 spi_w32w(SPI_CS_INIT, SFCSR); //deactivate CS0, CS1
35
36 return (CS0 & rtl838x_nor->flags) ? (SPI_eCS0 & SPI_LEN_INIT)
37 : ((SPI_eCS1 & SPI_LEN_INIT) | SFCSR_CHIP_SEL);
38 }
39
40 static uint32_t rtl838x_nor_get_SR(struct rtl838x_nor *rtl838x_nor)
41 {
42 uint32_t sfcsr, sfdr;
43
44 sfcsr = spi_prep(rtl838x_nor);
45 sfdr = (SPINOR_OP_RDSR)<<24;
46
47 pr_debug("%s: rdid,sfcsr_val = %.8x,SFDR = %.8x\n", __func__, sfcsr, sfdr);
48 pr_debug("rdid,sfcsr = %.8x\n", sfcsr | SPI_LEN4);
49 spi_w32w(sfcsr, SFCSR);
50 spi_w32w(sfdr, SFDR);
51 spi_w32_mask(0, SPI_LEN4, SFCSR);
52 SPI_WAIT_READY;
53
54 return spi_r32(SFDR);
55 }
56
57 static void spi_write_disable(struct rtl838x_nor *rtl838x_nor)
58 {
59 uint32_t sfcsr, sfdr;
60
61 sfcsr = spi_prep(rtl838x_nor);
62 sfdr = (SPINOR_OP_WRDI) << 24;
63 spi_w32w(sfcsr, SFCSR);
64 spi_w32w(sfdr, SFDR);
65 pr_debug("%s: sfcsr_val = %.8x,SFDR = %.8x", __func__, sfcsr, sfdr);
66
67 spi_prep(rtl838x_nor);
68 }
69
70 static void spi_write_enable(struct rtl838x_nor *rtl838x_nor)
71 {
72 uint32_t sfcsr, sfdr;
73
74 sfcsr = spi_prep(rtl838x_nor);
75 sfdr = (SPINOR_OP_WREN) << 24;
76 spi_w32w(sfcsr, SFCSR);
77 spi_w32w(sfdr, SFDR);
78 pr_debug("%s: sfcsr_val = %.8x,SFDR = %.8x", __func__, sfcsr, sfdr);
79
80 spi_prep(rtl838x_nor);
81 }
82
83 static void spi_4b_set(struct rtl838x_nor *rtl838x_nor, bool enable)
84 {
85 uint32_t sfcsr, sfdr;
86
87 sfcsr = spi_prep(rtl838x_nor);
88 if (enable)
89 sfdr = (SPINOR_OP_EN4B) << 24;
90 else
91 sfdr = (SPINOR_OP_EX4B) << 24;
92
93 spi_w32w(sfcsr, SFCSR);
94 spi_w32w(sfdr, SFDR);
95 pr_debug("%s: sfcsr_val = %.8x,SFDR = %.8x", __func__, sfcsr, sfdr);
96
97 spi_prep(rtl838x_nor);
98 }
99
100 static int rtl838x_get_addr_mode(struct rtl838x_nor *rtl838x_nor)
101 {
102 int res = 3;
103 u32 reg;
104
105 sw_w32(0x3, RTL838X_INT_RW_CTRL);
106 if (!sw_r32(RTL838X_EXT_VERSION)) {
107 if (sw_r32(RTL838X_STRAP_DBG) & (1 << 29))
108 res = 4;
109 } else {
110 reg = sw_r32(RTL838X_PLL_CML_CTRL);
111 if ((reg & (1 << 30)) && (reg & (1 << 31)))
112 res = 4;
113 if ((!(reg & (1 << 30)))
114 && sw_r32(RTL838X_STRAP_DBG) & (1 << 29))
115 res = 4;
116 }
117 sw_w32(0x0, RTL838X_INT_RW_CTRL);
118 return res;
119 }
120
121 static int rtl8390_get_addr_mode(struct rtl838x_nor *rtl838x_nor)
122 {
123 if (spi_r32(RTL8390_SOC_SPI_MMIO_CONF) & (1 << 9))
124 return 4;
125 return 3;
126 }
127
128 ssize_t rtl838x_do_read(struct rtl838x_nor *rtl838x_nor, loff_t from,
129 size_t length, u_char *buffer, uint8_t command)
130 {
131 uint32_t sfcsr, sfdr;
132 uint32_t len = length;
133
134 sfcsr = spi_prep(rtl838x_nor);
135 sfdr = command << 24;
136
137 /* Perform SPINOR_OP_READ: 1 byte command & 3 byte addr*/
138 sfcsr |= SPI_LEN4;
139 sfdr |= from;
140
141 spi_w32w(sfcsr, SFCSR);
142 spi_w32w(sfdr, SFDR);
143
144 /* Read Data, 4 bytes at a time */
145 while (length >= 4) {
146 SPI_WAIT_READY;
147 *((uint32_t *) buffer) = spi_r32(SFDR);
148 buffer += 4;
149 length -= 4;
150 }
151
152 /* The rest needs to be read 1 byte a time */
153 sfcsr &= SPI_LEN_INIT|SPI_LEN1;
154 SPI_WAIT_READY;
155 spi_w32w(sfcsr, SFCSR);
156 while (length > 0) {
157 SPI_WAIT_READY;
158 *(buffer) = spi_r32(SFDR) >> 24;
159 buffer++;
160 length--;
161 }
162 return len;
163 }
164
165 /*
166 * Do fast read in 3 or 4 Byte addressing mode
167 */
168 static ssize_t rtl838x_do_4bf_read(struct rtl838x_nor *rtl838x_nor, loff_t from,
169 size_t length, u_char *buffer, uint8_t command)
170 {
171 int sfcsr_addr_len = rtl838x_nor->fourByteMode ? 0x3 : 0x2;
172 int sfdr_addr_shift = rtl838x_nor->fourByteMode ? 0 : 8;
173 uint32_t sfcsr;
174 uint32_t len = length;
175
176 pr_debug("Fast read from %llx, len %x, shift %d\n",
177 from, sfcsr_addr_len, sfdr_addr_shift);
178 sfcsr = spi_prep(rtl838x_nor);
179
180 /* Send read command */
181 spi_w32w(sfcsr | SPI_LEN1, SFCSR);
182 spi_w32w(command << 24, SFDR);
183
184 /* Send address */
185 spi_w32w(sfcsr | (sfcsr_addr_len << 28), SFCSR);
186 spi_w32w(from << sfdr_addr_shift, SFDR);
187
188 /* Dummy cycles */
189 spi_w32w(sfcsr | SPI_LEN1, SFCSR);
190 spi_w32w(0, SFDR);
191
192 /* Start reading */
193 spi_w32w(sfcsr | SPI_LEN4, SFCSR);
194
195 /* Read Data, 4 bytes at a time */
196 while (length >= 4) {
197 SPI_WAIT_READY;
198 *((uint32_t *) buffer) = spi_r32(SFDR);
199 buffer += 4;
200 length -= 4;
201 }
202
203 /* The rest needs to be read 1 byte a time */
204 sfcsr &= SPI_LEN_INIT|SPI_LEN1;
205 SPI_WAIT_READY;
206 spi_w32w(sfcsr, SFCSR);
207 while (length > 0) {
208 SPI_WAIT_READY;
209 *(buffer) = spi_r32(SFDR) >> 24;
210 buffer++;
211 length--;
212 }
213 return len;
214
215 }
216
217 /*
218 * Do write (Page Programming) in 3 or 4 Byte addressing mode
219 */
220 static ssize_t rtl838x_do_4b_write(struct rtl838x_nor *rtl838x_nor, loff_t to,
221 size_t length, const u_char *buffer,
222 uint8_t command)
223 {
224 int sfcsr_addr_len = rtl838x_nor->fourByteMode ? 0x3 : 0x2;
225 int sfdr_addr_shift = rtl838x_nor->fourByteMode ? 0 : 8;
226 uint32_t sfcsr;
227 uint32_t len = length;
228
229 pr_debug("Write to %llx, len %x, shift %d\n",
230 to, sfcsr_addr_len, sfdr_addr_shift);
231 sfcsr = spi_prep(rtl838x_nor);
232
233 /* Send write command, command IO-width is 1 (bit 25/26) */
234 spi_w32w(sfcsr | SPI_LEN1 | (0 << 25), SFCSR);
235 spi_w32w(command << 24, SFDR);
236
237 /* Send address */
238 spi_w32w(sfcsr | (sfcsr_addr_len << 28) | (0 << 25), SFCSR);
239 spi_w32w(to << sfdr_addr_shift, SFDR);
240
241 /* Write Data, 1 byte at a time, if we are not 4-byte aligned */
242 if (((long)buffer) % 4) {
243 spi_w32w(sfcsr | SPI_LEN1, SFCSR);
244 while (length > 0 && (((long)buffer) % 4)) {
245 SPI_WAIT_READY;
246 spi_w32(*(buffer) << 24, SFDR);
247 buffer += 1;
248 length -= 1;
249 }
250 }
251
252 /* Now we can write 4 bytes at a time */
253 SPI_WAIT_READY;
254 spi_w32w(sfcsr | SPI_LEN4, SFCSR);
255 while (length >= 4) {
256 SPI_WAIT_READY;
257 spi_w32(*((uint32_t *)buffer), SFDR);
258 buffer += 4;
259 length -= 4;
260 }
261
262 /* Final bytes might need to be written 1 byte at a time, again */
263 SPI_WAIT_READY;
264 spi_w32w(sfcsr | SPI_LEN1, SFCSR);
265 while (length > 0) {
266 SPI_WAIT_READY;
267 spi_w32(*(buffer) << 24, SFDR);
268 buffer++;
269 length--;
270 }
271 return len;
272 }
273
274 static ssize_t rtl838x_nor_write(struct spi_nor *nor, loff_t to, size_t len,
275 const u_char *buffer)
276 {
277 int ret = 0;
278 uint32_t offset = 0;
279 struct rtl838x_nor *rtl838x_nor = nor->priv;
280 size_t l = len;
281 uint8_t cmd = SPINOR_OP_PP;
282
283 /* Do write in 4-byte mode on large Macronix chips */
284 if (rtl838x_nor->fourByteMode) {
285 cmd = SPINOR_OP_PP_4B;
286 spi_4b_set(rtl838x_nor, true);
287 }
288
289 pr_debug("In %s %8x to: %llx\n", __func__,
290 (unsigned int) rtl838x_nor, to);
291
292 while (l >= SPI_MAX_TRANSFER_SIZE) {
293 while
294 (rtl838x_nor_get_SR(rtl838x_nor) & SPI_WIP);
295 do {
296 spi_write_enable(rtl838x_nor);
297 } while (!(rtl838x_nor_get_SR(rtl838x_nor) & SPI_WEL));
298 ret = rtl838x_do_4b_write(rtl838x_nor, to + offset,
299 SPI_MAX_TRANSFER_SIZE, buffer+offset, cmd);
300 l -= SPI_MAX_TRANSFER_SIZE;
301 offset += SPI_MAX_TRANSFER_SIZE;
302 }
303
304 if (l > 0) {
305 while
306 (rtl838x_nor_get_SR(rtl838x_nor) & SPI_WIP);
307 do {
308 spi_write_enable(rtl838x_nor);
309 } while (!(rtl838x_nor_get_SR(rtl838x_nor) & SPI_WEL));
310 ret = rtl838x_do_4b_write(rtl838x_nor, to+offset,
311 len, buffer+offset, cmd);
312 }
313
314 return len;
315 }
316
317 static ssize_t rtl838x_nor_read(struct spi_nor *nor, loff_t from,
318 size_t length, u_char *buffer)
319 {
320 uint32_t offset = 0;
321 uint8_t cmd = SPINOR_OP_READ_FAST;
322 size_t l = length;
323 struct rtl838x_nor *rtl838x_nor = nor->priv;
324
325 /* Do fast read in 3, or 4-byte mode on large Macronix chips */
326 if (rtl838x_nor->fourByteMode) {
327 cmd = SPINOR_OP_READ_FAST_4B;
328 spi_4b_set(rtl838x_nor, true);
329 }
330
331 /* TODO: do timeout and return error */
332 pr_debug("Waiting for pending writes\n");
333 while
334 (rtl838x_nor_get_SR(rtl838x_nor) & SPI_WIP);
335 do {
336 spi_write_enable(rtl838x_nor);
337 } while (!(rtl838x_nor_get_SR(rtl838x_nor) & SPI_WEL));
338
339 pr_debug("cmd is %d\n", cmd);
340 pr_debug("%s: addr %.8llx to addr %.8x, cmd %.8x, size %d\n", __func__,
341 from, (u32)buffer, (u32)cmd, length);
342
343 while (l >= SPI_MAX_TRANSFER_SIZE) {
344 rtl838x_do_4bf_read(rtl838x_nor, from + offset,
345 SPI_MAX_TRANSFER_SIZE, buffer+offset, cmd);
346 l -= SPI_MAX_TRANSFER_SIZE;
347 offset += SPI_MAX_TRANSFER_SIZE;
348 }
349
350 if (l > 0)
351 rtl838x_do_4bf_read(rtl838x_nor, from + offset, l, buffer+offset, cmd);
352
353 return length;
354 }
355
356 static int rtl838x_erase(struct spi_nor *nor, loff_t offs)
357 {
358 struct rtl838x_nor *rtl838x_nor = nor->priv;
359 int sfcsr_addr_len = rtl838x_nor->fourByteMode ? 0x3 : 0x2;
360 int sfdr_addr_shift = rtl838x_nor->fourByteMode ? 0 : 8;
361 uint32_t sfcsr;
362 uint8_t cmd = SPINOR_OP_SE;
363
364 pr_debug("Erasing sector at %llx\n", offs);
365
366 /* Do erase in 4-byte mode on large Macronix chips */
367 if (rtl838x_nor->fourByteMode) {
368 cmd = SPINOR_OP_SE_4B;
369 spi_4b_set(rtl838x_nor, true);
370 }
371 /* TODO: do timeout and return error */
372 while
373 (rtl838x_nor_get_SR(rtl838x_nor) & SPI_WIP);
374 do {
375 spi_write_enable(rtl838x_nor);
376 } while (!(rtl838x_nor_get_SR(rtl838x_nor) & SPI_WEL));
377
378 sfcsr = spi_prep(rtl838x_nor);
379
380 /* Send erase command, command IO-width is 1 (bit 25/26) */
381 spi_w32w(sfcsr | SPI_LEN1 | (0 << 25), SFCSR);
382 spi_w32w(cmd << 24, SFDR);
383
384 /* Send address */
385 spi_w32w(sfcsr | (sfcsr_addr_len << 28) | (0 << 25), SFCSR);
386 spi_w32w(offs << sfdr_addr_shift, SFDR);
387
388 return 0;
389 }
390
391 static int rtl838x_nor_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
392 {
393 int length = len;
394 u8 *buffer = buf;
395 uint32_t sfcsr, sfdr;
396 struct rtl838x_nor *rtl838x_nor = nor->priv;
397
398 pr_debug("In %s: opcode %x, len %x\n", __func__, opcode, len);
399
400 sfcsr = spi_prep(rtl838x_nor);
401 sfdr = opcode << 24;
402
403 sfcsr |= SPI_LEN1;
404
405 spi_w32w(sfcsr, SFCSR);
406 spi_w32w(sfdr, SFDR);
407
408 while (length > 0) {
409 SPI_WAIT_READY;
410 *(buffer) = spi_r32(SFDR) >> 24;
411 buffer++;
412 length--;
413 }
414
415 return len;
416 }
417
418 static int rtl838x_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
419 {
420 uint32_t sfcsr, sfdr;
421 struct rtl838x_nor *rtl838x_nor = nor->priv;
422
423 pr_debug("In %s, opcode %x, len %x\n", __func__, opcode, len);
424 sfcsr = spi_prep(rtl838x_nor);
425 sfdr = opcode << 24;
426
427 if (len == 1) { /* SPINOR_OP_WRSR */
428 sfdr |= buf[0];
429 sfcsr |= SPI_LEN2;
430 }
431 spi_w32w(sfcsr, SFCSR);
432 spi_w32w(sfdr, SFDR);
433 return 0;
434 }
435
436 static int spi_enter_sio(struct spi_nor *nor)
437 {
438 uint32_t sfcsr, sfcr2, sfdr;
439 uint32_t ret = 0, reg = 0, size_bits;
440 struct rtl838x_nor *rtl838x_nor = nor->priv;
441
442 pr_debug("In %s\n", __func__);
443 rtl838x_nor->io_status = 0;
444 sfdr = SPI_C_RSTQIO << 24;
445 sfcsr = spi_prep(rtl838x_nor);
446
447 reg = spi_r32(SFCR2);
448 pr_debug("SFCR2: %x, size %x, rdopt: %x\n", reg, SFCR2_GETSIZE(reg),
449 (reg & SFCR2_RDOPT));
450 size_bits = rtl838x_nor->fourByteMode ? SFCR2_SIZE(0x6) : SFCR2_SIZE(0x7);
451
452 sfcr2 = SFCR2_HOLD_TILL_SFDR2 | size_bits
453 | (reg & SFCR2_RDOPT) | SFCR2_CMDIO(0)
454 | SFCR2_ADDRIO(0) | SFCR2_DUMMYCYCLE(4)
455 | SFCR2_DATAIO(0) | SFCR2_SFCMD(SPINOR_OP_READ_FAST);
456 pr_debug("SFCR2: %x, size %x\n", reg, SFCR2_GETSIZE(reg));
457
458 SPI_WAIT_READY;
459 spi_w32w(sfcr2, SFCR2);
460 spi_w32w(sfcsr, SFCSR);
461 spi_w32w(sfdr, SFDR);
462
463 spi_w32_mask(SFCR2_HOLD_TILL_SFDR2, 0, SFCR2);
464 rtl838x_nor->io_status &= ~IOSTATUS_CIO_MASK;
465 rtl838x_nor->io_status |= CIO1;
466
467 spi_prep(rtl838x_nor);
468
469 return ret;
470 }
471
472 int rtl838x_spi_nor_scan(struct spi_nor *nor, const char *name)
473 {
474 static const struct spi_nor_hwcaps hwcaps = {
475 .mask = SNOR_HWCAPS_READ | SNOR_HWCAPS_PP
476 | SNOR_HWCAPS_READ_FAST
477 };
478
479 struct rtl838x_nor *rtl838x_nor = nor->priv;
480
481 pr_debug("In %s\n", __func__);
482
483 spi_w32_mask(0, SFCR_EnableWBO, SFCR);
484 spi_w32_mask(0, SFCR_EnableRBO, SFCR);
485
486 rtl838x_nor->flags = CS0 | R_MODE;
487
488 spi_nor_scan(nor, NULL, &hwcaps);
489 pr_debug("------------- Got size: %llx\n", nor->mtd.size);
490
491 return 0;
492 }
493
494 int rtl838x_nor_init(struct rtl838x_nor *rtl838x_nor,
495 struct device_node *flash_node)
496 {
497 int ret;
498 struct spi_nor *nor;
499
500 pr_info("%s called\n", __func__);
501 nor = &rtl838x_nor->nor;
502 nor->dev = rtl838x_nor->dev;
503 nor->priv = rtl838x_nor;
504 spi_nor_set_flash_node(nor, flash_node);
505
506 nor->read_reg = rtl838x_nor_read_reg;
507 nor->write_reg = rtl838x_nor_write_reg;
508 nor->read = rtl838x_nor_read;
509 nor->write = rtl838x_nor_write;
510 nor->erase = rtl838x_erase;
511 nor->mtd.name = "rtl838x_nor";
512 nor->erase_opcode = rtl838x_nor->fourByteMode ? SPINOR_OP_SE_4B
513 : SPINOR_OP_SE;
514 /* initialized with NULL */
515 ret = rtl838x_spi_nor_scan(nor, NULL);
516 if (ret)
517 return ret;
518
519 spi_enter_sio(nor);
520 spi_write_disable(rtl838x_nor);
521
522 ret = mtd_device_parse_register(&nor->mtd, NULL, NULL, NULL, 0);
523 return ret;
524 }
525
526 static int rtl838x_nor_drv_probe(struct platform_device *pdev)
527 {
528 struct device_node *flash_np;
529 struct resource *res;
530 int ret;
531 struct rtl838x_nor *rtl838x_nor;
532 int addrMode;
533
534 pr_info("Initializing rtl838x_nor_driver\n");
535 if (!pdev->dev.of_node) {
536 dev_err(&pdev->dev, "No DT found\n");
537 return -EINVAL;
538 }
539
540 rtl838x_nor = devm_kzalloc(&pdev->dev, sizeof(*rtl838x_nor), GFP_KERNEL);
541 if (!rtl838x_nor)
542 return -ENOMEM;
543 platform_set_drvdata(pdev, rtl838x_nor);
544
545 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
546 rtl838x_nor->base = devm_ioremap_resource(&pdev->dev, res);
547 if (IS_ERR((void *)rtl838x_nor->base))
548 return PTR_ERR((void *)rtl838x_nor->base);
549
550 pr_info("SPI resource base is %08x\n", (u32)rtl838x_nor->base);
551 rtl838x_nor->dev = &pdev->dev;
552
553 /* only support one attached flash */
554 flash_np = of_get_next_available_child(pdev->dev.of_node, NULL);
555 if (!flash_np) {
556 dev_err(&pdev->dev, "no SPI flash device to configure\n");
557 ret = -ENODEV;
558 goto nor_free;
559 }
560
561 /* Get the 3/4 byte address mode as configure by bootloader */
562 if (soc_info.family == RTL8390_FAMILY_ID)
563 addrMode = rtl8390_get_addr_mode(rtl838x_nor);
564 else
565 addrMode = rtl838x_get_addr_mode(rtl838x_nor);
566 pr_info("Address mode is %d bytes\n", addrMode);
567 if (addrMode == 4)
568 rtl838x_nor->fourByteMode = true;
569
570 ret = rtl838x_nor_init(rtl838x_nor, flash_np);
571
572 nor_free:
573 return ret;
574 }
575
576 static int rtl838x_nor_drv_remove(struct platform_device *pdev)
577 {
578 /* struct rtl8xx_nor *rtl838x_nor = platform_get_drvdata(pdev); */
579 return 0;
580 }
581
582 static const struct of_device_id rtl838x_nor_of_ids[] = {
583 { .compatible = "realtek,rtl838x-nor"},
584 { /* sentinel */ }
585 };
586 MODULE_DEVICE_TABLE(of, rtl838x_nor_of_ids);
587
588 static struct platform_driver rtl838x_nor_driver = {
589 .probe = rtl838x_nor_drv_probe,
590 .remove = rtl838x_nor_drv_remove,
591 .driver = {
592 .name = "rtl838x-nor",
593 .pm = NULL,
594 .of_match_table = rtl838x_nor_of_ids,
595 },
596 };
597
598 module_platform_driver(rtl838x_nor_driver);
599
600 MODULE_LICENSE("GPL v2");
601 MODULE_DESCRIPTION("RTL838x SPI NOR Flash Driver");
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