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rtl838x: add new architecture
[openwrt/staging/ynezz.git] / target / linux / rtl838x / files-5.4 / drivers / net / dsa / rtl838x_sw.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <linux/etherdevice.h>
4 #include <linux/if_bridge.h>
5 #include <linux/iopoll.h>
6 #include <linux/mdio.h>
7 #include <linux/mfd/syscon.h>
8 #include <linux/module.h>
9 #include <linux/netdevice.h>
10 #include <linux/of_mdio.h>
11 #include <linux/of_net.h>
12 #include <linux/of_platform.h>
13 #include <linux/phylink.h>
14 #include <linux/phy_fixed.h>
15 #include <net/dsa.h>
16
17 #include <asm/mach-rtl838x/mach-rtl838x.h>
18 #include "rtl838x.h"
19
20 #define RTL8380_VERSION_A 'A'
21 #define RTL8390_VERSION_A 'A'
22 #define RTL8380_VERSION_B 'B'
23
24 DEFINE_MUTEX(smi_lock);
25
26 #define MIB_DESC(_size, _offset, _name) {.size = _size, .offset = _offset, .name = _name}
27 struct rtl838x_mib_desc {
28 unsigned int size;
29 unsigned int offset;
30 const char *name;
31 };
32
33 inline void rtl838x_mask_port_reg(u64 clear, u64 set, int reg)
34 {
35 sw_w32_mask((u32)clear, (u32)set, reg);
36 }
37
38 inline void rtl839x_mask_port_reg(u64 clear, u64 set, int reg)
39 {
40 sw_w32_mask((u32) (clear >> 32), (u32) (set >> 32), reg);
41 sw_w32_mask((u32) (clear & 0xffffffff), (u32) (set & 0xffffffff), reg + 4);
42 }
43
44 inline void rtl838x_set_port_reg(u64 set, int reg)
45 {
46 sw_w32(set, reg);
47 }
48
49 inline void rtl839x_set_port_reg(u64 set, int reg)
50 {
51 sw_w32(set >> 32, reg);
52 sw_w32(set & 0xffffffff, reg + 4);
53 }
54
55 inline u64 rtl838x_get_port_reg(int reg)
56 {
57 return ((u64) sw_r32(reg));
58 }
59
60 inline u64 rtl839x_get_port_reg(int reg)
61 {
62 u64 v = sw_r32(reg);
63
64 v <<= 32;
65 v |= sw_r32(reg + 4);
66 return v;
67 }
68
69 inline int rtl838x_stat_port_std_mib(int p)
70 {
71 return RTL838X_STAT_PORT_STD_MIB + (p << 8);
72 }
73
74 inline int rtl839x_stat_port_std_mib(int p)
75 {
76 return RTL839X_STAT_PORT_STD_MIB + (p << 8);
77 }
78
79 inline void rtl838x_mask_port_iso_ctrl(u64 clear, u64 set, int port)
80 {
81 sw_w32_mask(clear, set, RTL838X_PORT_ISO_CTRL(port));
82 }
83
84 inline void rtl839x_mask_port_iso_ctrl(u64 clear, u64 set, int port)
85 {
86 sw_w32_mask(clear >> 32, set >> 32, RTL839X_PORT_ISO_CTRL(port));
87 sw_w32_mask(clear & 0xffffffff, set & 0xffffffff,
88 RTL839X_PORT_ISO_CTRL(port) + 4);
89 }
90
91 inline void rtl838x_set_port_iso_ctrl(u64 set, int port)
92 {
93 sw_w32(set, RTL838X_PORT_ISO_CTRL(port));
94 }
95
96 inline void rtl839x_set_port_iso_ctrl(u64 set, int port)
97 {
98 sw_w32(set >> 32, RTL839X_PORT_ISO_CTRL(port));
99 sw_w32(set & 0xffffffff, RTL839X_PORT_ISO_CTRL(port) + 4);
100 }
101
102 inline void rtl838x_exec_tbl0_cmd(u32 cmd)
103 {
104 sw_w32(cmd, RTL838X_TBL_ACCESS_CTRL_0);
105 do { } while (sw_r32(RTL838X_TBL_ACCESS_CTRL_0) & (1 << 15));
106 }
107
108 inline void rtl839x_exec_tbl0_cmd(u32 cmd)
109 {
110 sw_w32(cmd, RTL839X_TBL_ACCESS_CTRL_0);
111 do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_0) & (1 << 16));
112 }
113
114 inline void rtl838x_exec_tbl1_cmd(u32 cmd)
115 {
116 sw_w32(cmd, RTL838X_TBL_ACCESS_CTRL_1);
117 do { } while (sw_r32(RTL838X_TBL_ACCESS_CTRL_1) & (1 << 15));
118 }
119
120 inline void rtl839x_exec_tbl1_cmd(u32 cmd)
121 {
122 sw_w32(cmd, RTL839X_TBL_ACCESS_CTRL_1);
123 do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_1) & (1 << 16));
124 }
125
126 inline int rtl838x_tbl_access_data_0(int i)
127 {
128 return RTL838X_TBL_ACCESS_DATA_0(i);
129 }
130
131 inline int rtl839x_tbl_access_data_0(int i)
132 {
133 return RTL839X_TBL_ACCESS_DATA_0(i);
134 }
135
136 static void rtl839x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info)
137 {
138 u32 cmd;
139 u64 v;
140
141 cmd = 1 << 16 /* Execute cmd */
142 | 0 << 15 /* Read */
143 | 0 << 12 /* Table type 0b000 */
144 | (vlan & 0xfff);
145 rtl839x_exec_tbl0_cmd(cmd);
146
147 v = sw_r32(RTL838X_TBL_ACCESS_DATA_0(0));
148 v <<= 32;
149 v |= sw_r32(RTL838X_TBL_ACCESS_DATA_0(1));
150 info->tagged_ports = v >> 11;
151 info->vlan_conf = (v & 0x7ff) << 2;
152 info->vlan_conf |= sw_r32(RTL838X_TBL_ACCESS_DATA_0(1)) >> 30;
153
154 cmd = 1 << 16 /* Execute cmd */
155 | 0 << 15 /* Read */
156 | 0 << 12 /* Table type 0b000 */
157 | (vlan & 0xfff);
158 rtl839x_exec_tbl1_cmd(cmd);
159 v = sw_r32(RTL838X_TBL_ACCESS_DATA_1(0));
160 v <<= 32;
161 v |= sw_r32(RTL838X_TBL_ACCESS_DATA_1(1));
162 info->untagged_ports = v >> 11;
163 }
164
165 static void rtl838x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info)
166 {
167 u32 cmd;
168
169 cmd = 1 << 15 /* Execute cmd */
170 | 1 << 14 /* Read */
171 | 0 << 12 /* Table type 0b00 */
172 | (vlan & 0xfff);
173 rtl838x_exec_tbl0_cmd(cmd);
174 info->tagged_ports = sw_r32(RTL838X_TBL_ACCESS_DATA_0(0));
175 info->vlan_conf = sw_r32(RTL838X_TBL_ACCESS_DATA_0(1));
176
177 cmd = 1 << 15 /* Execute cmd */
178 | 1 << 14 /* Read */
179 | 0 << 12 /* Table type 0b00 */
180 | (vlan & 0xfff);
181 rtl838x_exec_tbl1_cmd(cmd);
182 info->untagged_ports = sw_r32(RTL838X_TBL_ACCESS_DATA_1(0));
183 }
184
185 static void rtl839x_vlan_set_tagged(u32 vlan, u64 portmask, u32 conf)
186 {
187 u32 cmd = 1 << 16 /* Execute cmd */
188 | 1 << 15 /* Write */
189 | 0 << 12 /* Table type 0b00 */
190 | (vlan & 0xfff);
191 u64 v = portmask << 11;
192
193 v |= (conf >> 2) & 0x7ff;
194 sw_w64(v, RTL838X_TBL_ACCESS_DATA_0(0));
195 sw_w32(conf << 30, RTL838X_TBL_ACCESS_DATA_0(2));
196 rtl839x_exec_tbl0_cmd(cmd);
197 }
198
199 static void rtl838x_vlan_set_tagged(u32 vlan, u64 portmask, u32 conf)
200 {
201 u32 cmd = 1 << 15 /* Execute cmd */
202 | 0 << 14 /* Write */
203 | 0 << 12 /* Table type 0b00 */
204 | (vlan & 0xfff);
205
206 sw_w32(portmask, RTL838X_TBL_ACCESS_DATA_0(0));
207 sw_w32(conf, RTL838X_TBL_ACCESS_DATA_0(1));
208 rtl838x_exec_tbl0_cmd(cmd);
209 }
210
211 static void rtl839x_vlan_set_untagged(u32 vlan, u64 portmask)
212 {
213 u32 cmd = 1 << 16 /* Execute cmd */
214 | 1 << 15 /* Write */
215 | 0 << 12 /* Table type 0b00 */
216 | (vlan & 0xfff);
217 sw_w64(portmask << 11, RTL838X_TBL_ACCESS_DATA_1(0));
218 rtl839x_exec_tbl1_cmd(cmd);
219 }
220
221 static void rtl838x_vlan_set_untagged(u32 vlan, u64 portmask)
222 {
223 u32 cmd = 1 << 15 /* Execute cmd */
224 | 0 << 14 /* Write */
225 | 0 << 12 /* Table type 0b00 */
226 | (vlan & 0xfff);
227 sw_w32(portmask & 0x1fffffff, RTL838X_TBL_ACCESS_DATA_1(0));
228 rtl838x_exec_tbl1_cmd(cmd);
229 }
230
231 static inline int rtl838x_mac_force_mode_ctrl(int p)
232 {
233 return RTL838X_MAC_FORCE_MODE_CTRL + (p << 2);
234 }
235
236 static inline int rtl839x_mac_force_mode_ctrl(int p)
237 {
238 return RTL839X_MAC_FORCE_MODE_CTRL + (p << 2);
239 }
240
241 static const struct rtl838x_reg rtl838x_reg = {
242 .mask_port_reg = rtl838x_mask_port_reg,
243 .set_port_reg = rtl838x_set_port_reg,
244 .get_port_reg = rtl838x_get_port_reg,
245 .stat_port_rst = RTL838X_STAT_PORT_RST,
246 .stat_rst = RTL838X_STAT_RST,
247 .stat_port_std_mib = rtl838x_stat_port_std_mib,
248 .mask_port_iso_ctrl = rtl838x_mask_port_iso_ctrl,
249 .set_port_iso_ctrl = rtl838x_set_port_iso_ctrl,
250 .l2_ctrl_0 = RTL838X_L2_CTRL_0,
251 .l2_ctrl_1 = RTL838X_L2_CTRL_1,
252 .l2_port_aging_out = RTL838X_L2_PORT_AGING_OUT,
253 .smi_poll_ctrl = RTL838X_SMI_POLL_CTRL,
254 .l2_tbl_flush_ctrl = RTL838X_L2_TBL_FLUSH_CTRL,
255 .exec_tbl0_cmd = rtl838x_exec_tbl0_cmd,
256 .exec_tbl1_cmd = rtl838x_exec_tbl1_cmd,
257 .tbl_access_data_0 = rtl838x_tbl_access_data_0,
258 .isr_glb_src = RTL838X_ISR_GLB_SRC,
259 .isr_port_link_sts_chg = RTL838X_ISR_PORT_LINK_STS_CHG,
260 .imr_port_link_sts_chg = RTL838X_IMR_PORT_LINK_STS_CHG,
261 .imr_glb = RTL838X_IMR_GLB,
262 .vlan_tables_read = rtl838x_vlan_tables_read,
263 .vlan_set_tagged = rtl838x_vlan_set_tagged,
264 .vlan_set_untagged = rtl838x_vlan_set_untagged,
265 .mac_force_mode_ctrl = rtl838x_mac_force_mode_ctrl,
266 .rst_glb_ctrl = RTL838X_RST_GLB_CTRL_0,
267 };
268
269 static const struct rtl838x_reg rtl839x_reg = {
270 .mask_port_reg = rtl839x_mask_port_reg,
271 .set_port_reg = rtl839x_set_port_reg,
272 .get_port_reg = rtl839x_get_port_reg,
273 .stat_port_rst = RTL839X_STAT_PORT_RST,
274 .stat_rst = RTL839X_STAT_RST,
275 .stat_port_std_mib = rtl839x_stat_port_std_mib,
276 .mask_port_iso_ctrl = rtl839x_mask_port_iso_ctrl,
277 .set_port_iso_ctrl = rtl839x_set_port_iso_ctrl,
278 .l2_ctrl_0 = RTL839X_L2_CTRL_0,
279 .l2_ctrl_1 = RTL839X_L2_CTRL_1,
280 .l2_port_aging_out = RTL839X_L2_PORT_AGING_OUT,
281 .smi_poll_ctrl = RTL839X_SMI_PORT_POLLING_CTRL,
282 .l2_tbl_flush_ctrl = RTL839X_L2_TBL_FLUSH_CTRL,
283 .exec_tbl0_cmd = rtl839x_exec_tbl0_cmd,
284 .exec_tbl1_cmd = rtl839x_exec_tbl1_cmd,
285 .tbl_access_data_0 = rtl839x_tbl_access_data_0,
286 .isr_glb_src = RTL839X_ISR_GLB_SRC,
287 .isr_port_link_sts_chg = RTL839X_ISR_PORT_LINK_STS_CHG,
288 .imr_port_link_sts_chg = RTL839X_IMR_PORT_LINK_STS_CHG,
289 .imr_glb = RTL839X_IMR_GLB,
290 .vlan_tables_read = rtl839x_vlan_tables_read,
291 .vlan_set_tagged = rtl839x_vlan_set_tagged,
292 .vlan_set_untagged = rtl839x_vlan_set_untagged,
293 .mac_force_mode_ctrl = rtl839x_mac_force_mode_ctrl,
294 .rst_glb_ctrl = RTL839X_RST_GLB_CTRL,
295 };
296
297 static const struct rtl838x_mib_desc rtl838x_mib[] = {
298 MIB_DESC(2, 0xf8, "ifInOctets"),
299 MIB_DESC(2, 0xf0, "ifOutOctets"),
300 MIB_DESC(1, 0xec, "dot1dTpPortInDiscards"),
301 MIB_DESC(1, 0xe8, "ifInUcastPkts"),
302 MIB_DESC(1, 0xe4, "ifInMulticastPkts"),
303 MIB_DESC(1, 0xe0, "ifInBroadcastPkts"),
304 MIB_DESC(1, 0xdc, "ifOutUcastPkts"),
305 MIB_DESC(1, 0xd8, "ifOutMulticastPkts"),
306 MIB_DESC(1, 0xd4, "ifOutBroadcastPkts"),
307 MIB_DESC(1, 0xd0, "ifOutDiscards"),
308 MIB_DESC(1, 0xcc, ".3SingleCollisionFrames"),
309 MIB_DESC(1, 0xc8, ".3MultipleCollisionFrames"),
310 MIB_DESC(1, 0xc4, ".3DeferredTransmissions"),
311 MIB_DESC(1, 0xc0, ".3LateCollisions"),
312 MIB_DESC(1, 0xbc, ".3ExcessiveCollisions"),
313 MIB_DESC(1, 0xb8, ".3SymbolErrors"),
314 MIB_DESC(1, 0xb4, ".3ControlInUnknownOpcodes"),
315 MIB_DESC(1, 0xb0, ".3InPauseFrames"),
316 MIB_DESC(1, 0xac, ".3OutPauseFrames"),
317 MIB_DESC(1, 0xa8, "DropEvents"),
318 MIB_DESC(1, 0xa4, "tx_BroadcastPkts"),
319 MIB_DESC(1, 0xa0, "tx_MulticastPkts"),
320 MIB_DESC(1, 0x9c, "CRCAlignErrors"),
321 MIB_DESC(1, 0x98, "tx_UndersizePkts"),
322 MIB_DESC(1, 0x94, "rx_UndersizePkts"),
323 MIB_DESC(1, 0x90, "rx_UndersizedropPkts"),
324 MIB_DESC(1, 0x8c, "tx_OversizePkts"),
325 MIB_DESC(1, 0x88, "rx_OversizePkts"),
326 MIB_DESC(1, 0x84, "Fragments"),
327 MIB_DESC(1, 0x80, "Jabbers"),
328 MIB_DESC(1, 0x7c, "Collisions"),
329 MIB_DESC(1, 0x78, "tx_Pkts64Octets"),
330 MIB_DESC(1, 0x74, "rx_Pkts64Octets"),
331 MIB_DESC(1, 0x70, "tx_Pkts65to127Octets"),
332 MIB_DESC(1, 0x6c, "rx_Pkts65to127Octets"),
333 MIB_DESC(1, 0x68, "tx_Pkts128to255Octets"),
334 MIB_DESC(1, 0x64, "rx_Pkts128to255Octets"),
335 MIB_DESC(1, 0x60, "tx_Pkts256to511Octets"),
336 MIB_DESC(1, 0x5c, "rx_Pkts256to511Octets"),
337 MIB_DESC(1, 0x58, "tx_Pkts512to1023Octets"),
338 MIB_DESC(1, 0x54, "rx_Pkts512to1023Octets"),
339 MIB_DESC(1, 0x50, "tx_Pkts1024to1518Octets"),
340 MIB_DESC(1, 0x4c, "rx_StatsPkts1024to1518Octets"),
341 MIB_DESC(1, 0x48, "tx_Pkts1519toMaxOctets"),
342 MIB_DESC(1, 0x44, "rx_Pkts1519toMaxOctets"),
343 MIB_DESC(1, 0x40, "rxMacDiscards")
344 };
345
346 static irqreturn_t rtl838x_switch_irq(int irq, void *dev_id)
347 {
348 struct dsa_switch *ds = dev_id;
349 u32 status = sw_r32(RTL838X_ISR_GLB_SRC);
350 u32 ports = sw_r32(RTL838X_ISR_PORT_LINK_STS_CHG);
351 u32 link;
352 int i;
353
354 /* Clear status */
355 sw_w32(ports, RTL838X_ISR_PORT_LINK_STS_CHG);
356 pr_info("Link change: status: %x, ports %x\n", status, ports);
357
358 for (i = 0; i < 28; i++) {
359 if (ports & (1 << i)) {
360 link = sw_r32(RTL838X_MAC_LINK_STS);
361 if (link & (1 << i))
362 dsa_port_phylink_mac_change(ds, i, true);
363 else
364 dsa_port_phylink_mac_change(ds, i, false);
365 }
366 }
367 return IRQ_HANDLED;
368 }
369
370 static irqreturn_t rtl839x_switch_irq(int irq, void *dev_id)
371 {
372 struct dsa_switch *ds = dev_id;
373 u32 status = sw_r32(RTL839X_ISR_GLB_SRC);
374 u64 ports = sw_r64(RTL839X_ISR_PORT_LINK_STS_CHG);
375 u64 link;
376 int i;
377
378 /* Clear status */
379 sw_w64(ports, RTL839X_ISR_PORT_LINK_STS_CHG);
380 pr_info("Link change: status: %x, ports %llx\n", status, ports);
381
382 for (i = 0; i < 52; i++) {
383 if (ports & (1 << i)) {
384 link = sw_r64(RTL839X_MAC_LINK_STS);
385 if (link & (1 << i))
386 dsa_port_phylink_mac_change(ds, i, true);
387 else
388 dsa_port_phylink_mac_change(ds, i, false);
389 }
390 }
391 return IRQ_HANDLED;
392 }
393
394 int rtl8380_sds_power(int mac, int val)
395 {
396 u32 mode = (val == 1) ? 0x4 : 0x9;
397 u32 offset = (mac == 24) ? 5 : 0;
398
399 if ((mac != 24) && (mac != 26)) {
400 pr_err("%s: not a fibre port: %d\n", __func__, mac);
401 return -1;
402 }
403
404 sw_w32_mask(0x1f << offset, mode << offset, RTL838X_SDS_MODE_SEL);
405
406 rtl8380_sds_rst(mac);
407
408 return 0;
409 }
410
411 static int rtl838x_smi_wait_op(int timeout)
412 {
413 do {
414 timeout--;
415 udelay(10);
416 } while ((sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_1) & 0x1) && (timeout >= 0));
417 if (timeout <= 0)
418 return -1;
419 return 0;
420 }
421
422 /*
423 * Write to a register in a page of the PHY
424 */
425 int rtl838x_write_phy(u32 port, u32 page, u32 reg, u32 val)
426 {
427 u32 v;
428 u32 park_page;
429
430 val &= 0xffff;
431 if (port > 31 || page > 4095 || reg > 31)
432 return -ENOTSUPP;
433
434 mutex_lock(&smi_lock);
435 if (rtl838x_smi_wait_op(10000))
436 goto timeout;
437
438 sw_w32(1 << port, RTL838X_SMI_ACCESS_PHY_CTRL_0);
439 mdelay(10);
440
441 sw_w32_mask(0xffff0000, val << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2);
442
443 park_page = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_1) & ((0x1f << 15) | 0x2);
444 v = reg << 20 | page << 3 | 0x4;
445 sw_w32(v | park_page, RTL838X_SMI_ACCESS_PHY_CTRL_1);
446 sw_w32_mask(0, 1, RTL838X_SMI_ACCESS_PHY_CTRL_1);
447
448 if (rtl838x_smi_wait_op(10000))
449 goto timeout;
450
451 mutex_unlock(&smi_lock);
452 return 0;
453
454 timeout:
455 mutex_unlock(&smi_lock);
456 return -ETIMEDOUT;
457 }
458
459 int rtl839x_write_phy(u32 port, u32 page, u32 reg, u32 val)
460 {
461 u32 v;
462 int err = 0;
463
464 val &= 0xffff;
465 if (port > 63 || page > 4095 || reg > 31)
466 return -ENOTSUPP;
467
468 mutex_lock(&smi_lock);
469 /* Clear both port registers */
470 sw_w32(0, RTL839X_PHYREG_PORT_CTRL(0));
471 sw_w32(0, RTL839X_PHYREG_PORT_CTRL(0) + 4);
472 sw_w32_mask(0, 1 << port, RTL839X_PHYREG_PORT_CTRL(port));
473
474 sw_w32_mask(0xffff0000, val << 16, RTL839X_PHYREG_DATA_CTRL);
475
476 v = reg << 5 | page << 10 | ((page == 0x1fff) ? 0x1f : 0) << 23;
477 sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
478
479 sw_w32(0x1ff, RTL839X_PHYREG_CTRL);
480
481 v |= 1 << 3 | 1; /* Write operation and execute */
482 sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
483
484 do {
485 } while (sw_r32(RTL839X_PHYREG_ACCESS_CTRL) & 0x1);
486
487 if (sw_r32(RTL839X_PHYREG_ACCESS_CTRL) & 0x2)
488 err = -EIO;
489
490 mutex_unlock(&smi_lock);
491 return err;
492 }
493
494 /*
495 * Reads a register in a page from the PHY
496 */
497 int rtl838x_read_phy(u32 port, u32 page, u32 reg, u32 *val)
498 {
499 u32 v;
500 u32 park_page;
501
502 if (port > 31 || page > 4095 || reg > 31)
503 return -ENOTSUPP;
504
505 mutex_lock(&smi_lock);
506
507 if (rtl838x_smi_wait_op(10000))
508 goto timeout;
509
510 sw_w32_mask(0xffff0000, port << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2);
511
512 park_page = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_1) & ((0x1f << 15) | 0x2);
513 v = reg << 20 | page << 3;
514 sw_w32(v | park_page, RTL838X_SMI_ACCESS_PHY_CTRL_1);
515 sw_w32_mask(0, 1, RTL838X_SMI_ACCESS_PHY_CTRL_1);
516
517 if (rtl838x_smi_wait_op(10000))
518 goto timeout;
519
520 *val = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_2) & 0xffff;
521
522 mutex_unlock(&smi_lock);
523 return 0;
524
525 timeout:
526 mutex_unlock(&smi_lock);
527 return -ETIMEDOUT;
528 }
529
530 int rtl839x_read_phy(u32 port, u32 page, u32 reg, u32 *val)
531 {
532 u32 v;
533
534 if (port > 63 || page > 4095 || reg > 31)
535 return -ENOTSUPP;
536
537 mutex_lock(&smi_lock);
538
539 sw_w32_mask(0xffff0000, port << 16, RTL839X_PHYREG_DATA_CTRL);
540 v = reg << 5 | page << 10 | ((page == 0x1fff) ? 0x1f : 0) << 23;
541 sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
542
543 sw_w32(0x1ff, RTL839X_PHYREG_CTRL);
544
545 v |= 1;
546 sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
547
548 do {
549 } while (sw_r32(RTL839X_PHYREG_ACCESS_CTRL) & 0x1);
550
551 *val = sw_r32(RTL839X_PHYREG_DATA_CTRL) & 0xffff;
552
553 mutex_unlock(&smi_lock);
554 return 0;
555 }
556
557 static int read_phy(u32 port, u32 page, u32 reg, u32 *val)
558 {
559 if (soc_info.family == RTL8390_FAMILY_ID)
560 return rtl839x_read_phy(port, page, reg, val);
561 else
562 return rtl838x_read_phy(port, page, reg, val);
563 }
564
565 static int write_phy(u32 port, u32 page, u32 reg, u32 val)
566 {
567 if (soc_info.family == RTL8390_FAMILY_ID)
568 return rtl839x_write_phy(port, page, reg, val);
569 else
570 return rtl838x_write_phy(port, page, reg, val);
571 }
572
573 /*
574 * Write to an mmd register of the PHY
575 */
576 int rtl838x_write_mmd_phy(u32 port, u32 addr, u32 reg, u32 val)
577 {
578 u32 v;
579
580 pr_debug("MMD write: port %d, dev %d, reg %d, val %x\n", port, addr, reg, val);
581 val &= 0xffff;
582 mutex_lock(&smi_lock);
583
584 if (rtl838x_smi_wait_op(10000))
585 goto timeout;
586
587 sw_w32(1 << port, RTL838X_SMI_ACCESS_PHY_CTRL_0);
588 mdelay(10);
589
590 sw_w32_mask(0xffff0000, val << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2);
591
592 sw_w32_mask(0x1f << 16, addr << 16, RTL838X_SMI_ACCESS_PHY_CTRL_3);
593 sw_w32_mask(0xffff, reg, RTL838X_SMI_ACCESS_PHY_CTRL_3);
594 /* mmd-access | write | cmd-start */
595 v = 1 << 1 | 1 << 2 | 1;
596 sw_w32(v, RTL838X_SMI_ACCESS_PHY_CTRL_1);
597
598 if (rtl838x_smi_wait_op(10000))
599 goto timeout;
600
601 mutex_unlock(&smi_lock);
602 return 0;
603
604 timeout:
605 mutex_unlock(&smi_lock);
606 return -ETIMEDOUT;
607 }
608
609 /*
610 * Read to an mmd register of the PHY
611 */
612 int rtl838x_read_mmd_phy(u32 port, u32 addr, u32 reg, u32 *val)
613 {
614 u32 v;
615
616 mutex_lock(&smi_lock);
617
618 if (rtl838x_smi_wait_op(10000))
619 goto timeout;
620
621 sw_w32(1 << port, RTL838X_SMI_ACCESS_PHY_CTRL_0);
622 mdelay(10);
623
624 sw_w32_mask(0xffff0000, port << 16, RTL838X_SMI_ACCESS_PHY_CTRL_2);
625
626 v = addr << 16 | reg;
627 sw_w32(v, RTL838X_SMI_ACCESS_PHY_CTRL_3);
628
629 /* mmd-access | read | cmd-start */
630 v = 1 << 1 | 0 << 2 | 1;
631 sw_w32(v, RTL838X_SMI_ACCESS_PHY_CTRL_1);
632
633 if (rtl838x_smi_wait_op(10000))
634 goto timeout;
635
636 *val = sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_2) & 0xffff;
637
638 mutex_unlock(&smi_lock);
639 return 0;
640
641 timeout:
642 mutex_unlock(&smi_lock);
643 return -ETIMEDOUT;
644 }
645
646 static void rtl8380_get_version(struct rtl838x_switch_priv *priv)
647 {
648 u32 rw_save, info_save;
649 u32 info;
650
651 if (priv->id)
652 pr_debug("SoC ID: %4x: %s\n", priv->id, soc_info.name);
653 else
654 pr_err("Unknown chip id (%04x)\n", priv->id);
655
656 rw_save = sw_r32(RTL838X_INT_RW_CTRL);
657 sw_w32(rw_save | 0x3, RTL838X_INT_RW_CTRL);
658
659 info_save = sw_r32(RTL838X_CHIP_INFO);
660 sw_w32(info_save | 0xA0000000, RTL838X_CHIP_INFO);
661
662 info = sw_r32(RTL838X_CHIP_INFO);
663 sw_w32(info_save, RTL838X_CHIP_INFO);
664 sw_w32(rw_save, RTL838X_INT_RW_CTRL);
665
666 if ((info & 0xFFFF) == 0x6275) {
667 if (((info >> 16) & 0x1F) == 0x1)
668 priv->version = RTL8380_VERSION_A;
669 else if (((info >> 16) & 0x1F) == 0x2)
670 priv->version = RTL8380_VERSION_B;
671 else
672 priv->version = RTL8380_VERSION_B;
673 } else {
674 priv->version = '-';
675 }
676 }
677
678 static void rtl8390_get_version(struct rtl838x_switch_priv *priv)
679 {
680 u32 info;
681
682 sw_w32_mask(0xf << 28, 0xa << 28, RTL839X_CHIP_INFO);
683 info = sw_r32(RTL839X_CHIP_INFO);
684 pr_info("Chip-Info: %x\n", info);
685 priv->version = RTL8390_VERSION_A;
686 }
687
688 int dsa_phy_read(struct dsa_switch *ds, int phy_addr, int phy_reg)
689 {
690 u32 val;
691 u32 offset = 0;
692 struct rtl838x_switch_priv *priv = ds->priv;
693
694 if (phy_addr >= 24 && phy_addr <= 27
695 && priv->ports[24].phy == PHY_RTL838X_SDS) {
696 if (phy_addr == 26)
697 offset = 0x100;
698 val = sw_r32(MAPLE_SDS4_FIB_REG0r + offset + (phy_reg << 2)) & 0xffff;
699 return val;
700 }
701
702 read_phy(phy_addr, 0, phy_reg, &val);
703 return val;
704 }
705
706 int dsa_phy_write(struct dsa_switch *ds, int phy_addr, int phy_reg, u16 val)
707 {
708 u32 offset = 0;
709 struct rtl838x_switch_priv *priv = ds->priv;
710
711 if (phy_addr >= 24 && phy_addr <= 27
712 && priv->ports[24].phy == PHY_RTL838X_SDS) {
713 if (phy_addr == 26)
714 offset = 0x100;
715 sw_w32(val, MAPLE_SDS4_FIB_REG0r + offset + (phy_reg << 2));
716 return 0;
717 }
718 return write_phy(phy_addr, 0, phy_reg, val);
719 }
720
721 static int rtl838x_mdio_read(struct mii_bus *bus, int addr, int regnum)
722 {
723 int ret;
724 struct rtl838x_switch_priv *priv = bus->priv;
725
726 ret = dsa_phy_read(priv->ds, addr, regnum);
727 return ret;
728 }
729
730 static int rtl838x_mdio_write(struct mii_bus *bus, int addr, int regnum,
731 u16 val)
732 {
733 struct rtl838x_switch_priv *priv = bus->priv;
734
735 return dsa_phy_write(priv->ds, addr, regnum, val);
736 }
737
738 static void rtl838x_enable_phy_polling(struct rtl838x_switch_priv *priv)
739 {
740 int i;
741 u64 v = 0;
742
743 msleep(1000);
744 /* Enable all ports with a PHY, including the SFP-ports */
745 for (i = 0; i < priv->cpu_port; i++) {
746 if (priv->ports[i].phy)
747 v |= 1 << i;
748 }
749
750 pr_info("%s: %16llx\n", __func__, v);
751 priv->r->set_port_reg(v, priv->r->smi_poll_ctrl);
752
753 /* PHY update complete */
754 if (priv->family_id == RTL8390_FAMILY_ID)
755 sw_w32_mask(1 << 7, 0, RTL839X_SMI_GLB_CTRL);
756 else
757 sw_w32_mask(0, 0x8000, RTL838X_SMI_GLB_CTRL);
758 }
759
760 void rtl839x_print_matrix(void)
761 {
762 volatile u64 *ptr = RTL838X_SW_BASE + RTL839X_PORT_ISO_CTRL(0);
763 int i;
764
765 for (i = 0; i < 52; i += 4)
766 pr_info("> %16llx %16llx %16llx %16llx\n",
767 ptr[i + 0], ptr[i + 1], ptr[i + 2], ptr[i + 3]);
768 pr_info("CPU_PORT> %16llx\n", ptr[52]);
769 }
770
771 void rtl838x_print_matrix(void)
772 {
773 unsigned volatile int *ptr = RTL838X_SW_BASE + RTL838X_PORT_ISO_CTRL(0);
774 int i;
775
776 if (soc_info.family == RTL8390_FAMILY_ID)
777 return rtl839x_print_matrix();
778
779 for (i = 0; i < 28; i += 8)
780 pr_info("> %8x %8x %8x %8x %8x %8x %8x %8x\n",
781 ptr[i + 0], ptr[i + 1], ptr[i + 2], ptr[i + 3], ptr[i + 4], ptr[i + 5],
782 ptr[i + 6], ptr[i + 7]);
783 pr_info("CPU_PORT> %8x\n", ptr[28]);
784 }
785
786 static void rtl838x_init_stats(struct rtl838x_switch_priv *priv)
787 {
788 mutex_lock(&priv->reg_mutex);
789
790 /* Enable statistics module: all counters plus debug.
791 * On RTL839x all counters are enabled by default
792 */
793 if (priv->family_id == RTL8380_FAMILY_ID)
794 sw_w32_mask(0, 3, RTL838X_STAT_CTRL);
795
796 /* Reset statistics counters */
797 sw_w32_mask(0, 1, priv->r->stat_rst);
798
799 mutex_unlock(&priv->reg_mutex);
800 }
801
802 static int rtl838x_setup(struct dsa_switch *ds)
803 {
804 int i;
805 u64 port_bitmap = 0;
806 struct rtl838x_switch_priv *priv = ds->priv;
807
808 pr_info("%s called\n", __func__);
809
810 /* Disable MAC polling the PHY so that we can start configuration */
811 priv->r->set_port_reg(0, priv->r->smi_poll_ctrl);
812
813 for (i = 0; i < ds->num_ports; i++)
814 priv->ports[i].enable = false;
815 priv->ports[priv->cpu_port].enable = true;
816
817 /* Isolate ports from each other: traffic only CPU <-> port */
818 for (i = 0; i < priv->cpu_port; i++) {
819 if (priv->ports[i].phy) {
820 priv->r->set_port_iso_ctrl(1 << priv->cpu_port, i);
821 priv->r->mask_port_iso_ctrl(0, 1 << i, i);
822 port_bitmap |= 1 << i;
823 }
824 }
825 priv->r->set_port_iso_ctrl(port_bitmap, priv->cpu_port);
826
827 rtl838x_print_matrix();
828
829 rtl838x_init_stats(priv);
830
831 /* Enable MAC Polling PHY again */
832 rtl838x_enable_phy_polling(priv);
833 pr_info("Please wait until PHY is settled\n");
834 msleep(1000);
835 return 0;
836 }
837
838 static void rtl838x_get_strings(struct dsa_switch *ds,
839 int port, u32 stringset, u8 *data)
840 {
841 int i;
842
843 if (stringset != ETH_SS_STATS)
844 return;
845
846 for (i = 0; i < ARRAY_SIZE(rtl838x_mib); i++)
847 strncpy(data + i * ETH_GSTRING_LEN, rtl838x_mib[i].name,
848 ETH_GSTRING_LEN);
849 }
850
851 static void rtl838x_get_ethtool_stats(struct dsa_switch *ds, int port,
852 uint64_t *data)
853 {
854 struct rtl838x_switch_priv *priv = ds->priv;
855 const struct rtl838x_mib_desc *mib;
856 int i;
857 u64 high;
858
859 for (i = 0; i < ARRAY_SIZE(rtl838x_mib); i++) {
860 mib = &rtl838x_mib[i];
861
862 data[i] = sw_r32(priv->r->stat_port_std_mib(port) + 252 - mib->offset);
863 if (mib->size == 2) {
864 high = sw_r32(priv->r->stat_port_std_mib(port) + 252 - mib->offset - 4);
865 data[i] |= high << 32;
866 }
867 }
868 }
869
870 static int rtl838x_get_sset_count(struct dsa_switch *ds, int port, int sset)
871 {
872 if (sset != ETH_SS_STATS)
873 return 0;
874
875 return ARRAY_SIZE(rtl838x_mib);
876 }
877
878 static enum dsa_tag_protocol
879 rtl838x_get_tag_protocol(struct dsa_switch *ds, int port)
880 {
881 /* The switch does not tag the frames, instead internally the header
882 * structure for each packet is tagged accordingly.
883 */
884 return DSA_TAG_PROTO_TRAILER;
885 }
886
887 static int rtl838x_get_l2aging(struct rtl838x_switch_priv *priv)
888 {
889 int t = sw_r32(priv->r->l2_ctrl_1) & 0x7fffff;
890
891 pr_debug("RTL838X_L2_CTRL_1 %x\n", sw_r32(priv->r->l2_ctrl_1));
892
893 t = t * 128 / 625; /* Aging time in seconds. 0: L2 aging disabled */
894 pr_info("L2 AGING time: %d sec\n", t);
895 pr_info("Dynamic aging for ports: %x\n",
896 sw_r32(priv->r->l2_port_aging_out));
897 return t;
898 }
899
900 /*
901 * Set Switch L2 Aging time, t is time in milliseconds
902 * t = 0: aging is disabled
903 */
904 static int rtl838x_set_l2aging(struct dsa_switch *ds, u32 t)
905 {
906 struct rtl838x_switch_priv *priv = ds->priv;
907 /* Convert time in mseconds to internal value */
908 if (t > 0x10000000) /* Set to maximum */
909 t = 0x7fffff;
910 else
911 t = ((t * 625) / 1000 + 127) / 128;
912
913 sw_w32(t, priv->r->l2_ctrl_1);
914
915 return 0;
916 }
917
918 static void rtl838x_fast_age(struct dsa_switch *ds, int port)
919 {
920 struct rtl838x_switch_priv *priv = ds->priv;
921 int s = priv->family_id == RTL8390_FAMILY_ID ? 2 : 0;
922
923 pr_info("FAST AGE port %d\n", port);
924 mutex_lock(&priv->reg_mutex);
925 /* RTL838X_L2_TBL_FLUSH_CTRL register bits, 839x has 1 bit larger
926 * port fields:
927 * 0-4: Replacing port
928 * 5-9: Flushed/replaced port
929 * 10-21: FVID
930 * 22: Entry types: 1: dynamic, 0: also static
931 * 23: Match flush port
932 * 24: Match FVID
933 * 25: Flush (0) or replace (1) L2 entries
934 * 26: Status of action (1: Start, 0: Done)
935 */
936 sw_w32(1 << (26 + s) | 1 << (23 + s) | port << 5, priv->r->l2_tbl_flush_ctrl);
937
938 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & (1 << (26 + s)));
939
940 mutex_unlock(&priv->reg_mutex);
941 }
942
943 /*
944 * Applies the same hash algorithm as the one used currently by the ASIC
945 */
946 static u32 rtl838x_hash(struct rtl838x_switch_priv *priv, u64 seed)
947 {
948 u32 h1, h2, h3, h;
949
950 if (sw_r32(priv->r->l2_ctrl_0) & 1) {
951 h1 = (seed >> 11) & 0x7ff;
952 h1 = ((h1 & 0x1f) << 6) | ((h1 >> 5) & 0x3f);
953
954 h2 = (seed >> 33) & 0x7ff;
955 h2 = ((h2 & 0x3f) << 5) | ((h2 >> 6) & 0x1f);
956
957 h3 = (seed >> 44) & 0x7ff;
958 h3 = ((h3 & 0x7f) << 4) | ((h3 >> 7) & 0xf);
959
960 h = h1 ^ h2 ^ h3 ^ ((seed >> 55) & 0x1ff);
961 h ^= ((seed >> 22) & 0x7ff) ^ (seed & 0x7ff);
962 } else {
963 h = ((seed >> 55) & 0x1ff) ^ ((seed >> 44) & 0x7ff)
964 ^ ((seed >> 33) & 0x7ff) ^ ((seed >> 22) & 0x7ff)
965 ^ ((seed >> 11) & 0x7ff) ^ (seed & 0x7ff);
966 }
967
968 return h;
969 }
970
971 static u64 rtl838x_hash_key(struct rtl838x_switch_priv *priv, u64 mac, u32 vid)
972 {
973 return rtl838x_hash(priv, mac << 12 | vid);
974 }
975
976 static u64 read_l2_entry_using_hash(u32 hash, u32 position, u32 *r)
977 {
978 u64 entry;
979 /* Search in SRAM, with hash and at position in hash bucket (0-3) */
980 u32 idx = (0 << 14) | (hash << 2) | position;
981
982 u32 cmd = 1 << 16 /* Execute cmd */
983 | 1 << 15 /* Read */
984 | 0 << 13 /* Table type 0b00 */
985 | (idx & 0x1fff);
986
987 sw_w32(cmd, RTL838X_TBL_ACCESS_L2_CTRL);
988 do { } while (sw_r32(RTL838X_TBL_ACCESS_L2_CTRL) & (1 << 16));
989 r[0] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(0));
990 r[1] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(1));
991 r[2] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(2));
992
993 entry = (((u64) r[1]) << 32) | (r[2] & 0xfffff000) | (r[0] & 0xfff);
994 return entry;
995 }
996
997 static u64 rtl838x_read_cam(int idx, u32 *r)
998 {
999 u64 entry;
1000 u32 cmd = 1 << 16 /* Execute cmd */
1001 | 1 << 15 /* Read */
1002 | 1 << 13 /* Table type 0b01 */
1003 | (idx & 0x3f);
1004 sw_w32(cmd, RTL838X_TBL_ACCESS_L2_CTRL);
1005 do { } while (sw_r32(RTL838X_TBL_ACCESS_L2_CTRL) & (1 << 16));
1006 r[0] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(0));
1007 r[1] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(1));
1008 r[2] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(2));
1009
1010 entry = (((u64) r[1]) << 32) | (r[2] & 0xfffff000) | (r[0] & 0xfff);
1011 return entry;
1012 }
1013
1014 static void rtl838x_write_cam(int idx, u32 *r)
1015 {
1016 u32 cmd = 1 << 16 /* Execute cmd */
1017 | 1 << 15 /* Read */
1018 | 1 << 13 /* Table type 0b01 */
1019 | (idx & 0x3f);
1020
1021 sw_w32(r[0], RTL838X_TBL_ACCESS_L2_DATA(0));
1022 sw_w32(r[1], RTL838X_TBL_ACCESS_L2_DATA(1));
1023 sw_w32(r[2], RTL838X_TBL_ACCESS_L2_DATA(2));
1024
1025 sw_w32(cmd, RTL838X_TBL_ACCESS_L2_CTRL);
1026 do { } while (sw_r32(RTL838X_TBL_ACCESS_L2_CTRL) & (1 << 16));
1027 }
1028
1029 static void rtl838x_write_hash(int idx, u32 *r)
1030 {
1031 u32 cmd = 1 << 16 /* Execute cmd */
1032 | 0 << 15 /* Write */
1033 | 0 << 13 /* Table type 0b00 */
1034 | (idx & 0x1fff);
1035
1036 sw_w32(0, RTL838X_TBL_ACCESS_L2_DATA(0));
1037 sw_w32(0, RTL838X_TBL_ACCESS_L2_DATA(1));
1038 sw_w32(0, RTL838X_TBL_ACCESS_L2_DATA(2));
1039 sw_w32(cmd, RTL838X_TBL_ACCESS_L2_CTRL);
1040 do { } while (sw_r32(RTL838X_TBL_ACCESS_L2_CTRL) & (1 << 16));
1041 }
1042
1043 static void dump_fdb(struct rtl838x_switch_priv *priv)
1044 {
1045 u32 r[3];
1046 int i;
1047 u8 mac[6];
1048 u16 vid, rvid;
1049
1050 mutex_lock(&priv->reg_mutex);
1051
1052 for (i = 0; i < 8192; i++) {
1053 read_l2_entry_using_hash(i >> 2, i & 0x3, r);
1054 mac[0] = (r[1] >> 20);
1055 mac[1] = (r[1] >> 12);
1056 mac[2] = (r[1] >> 4);
1057 mac[3] = (r[1] & 0xf) << 4 | (r[2] >> 28);
1058 mac[4] = (r[2] >> 20);
1059 mac[5] = (r[2] >> 12);
1060 vid = r[0] & 0xfff;
1061 rvid = r[2] & 0xfff;
1062
1063 if (!(r[0] >> 17)) /* Check for invalid entry */
1064 continue;
1065
1066 pr_info("-> port %02d: %pM, vid: %d, rvid: %d\n",
1067 (r[0] >> 12) & priv->port_mask, &mac[0], vid, rvid);
1068 }
1069
1070 mutex_unlock(&priv->reg_mutex);
1071 }
1072
1073 static int rtl838x_port_fdb_dump(struct dsa_switch *ds, int port,
1074 dsa_fdb_dump_cb_t *cb, void *data)
1075 {
1076 u32 r[3];
1077 u8 mac[6];
1078 u16 vid, rvid;
1079 struct rtl838x_switch_priv *priv = ds->priv;
1080 int i;
1081
1082 mutex_lock(&priv->reg_mutex);
1083
1084 for (i = 0; i < 8192; i++) {
1085 read_l2_entry_using_hash(i >> 2, i & 0x3, r);
1086 mac[0] = (r[1] >> 20);
1087 mac[1] = (r[1] >> 12);
1088 mac[2] = (r[1] >> 4);
1089 mac[3] = (r[1] & 0xf) << 4 | (r[2] >> 28);
1090 mac[4] = (r[2] >> 20);
1091 mac[5] = (r[2] >> 12);
1092 vid = r[0] & 0xfff;
1093 rvid = r[2] & 0xfff;
1094
1095 if (!(r[0] >> 17)) /* Check for invalid entry */
1096 continue;
1097
1098 if (port == ((r[0] >> 12) & 0x1f)) {
1099 pr_info("-> mac %pM, vid: %d, rvid: %d\n", &mac[0], vid, rvid);
1100 cb(mac, vid, (r[0] >> 19) & 1, data);
1101 }
1102 }
1103
1104 for (i = 0; i < 64; i++) {
1105 rtl838x_read_cam(i, r);
1106 mac[0] = (r[1] >> 20);
1107 mac[1] = (r[1] >> 12);
1108 mac[2] = (r[1] >> 4);
1109 mac[3] = (r[1] & 0xf) << 4 | (r[2] >> 28);
1110 mac[4] = (r[2] >> 20);
1111 mac[5] = (r[2] >> 12);
1112 vid = r[0] & 0xfff;
1113
1114 if (!(r[0] >> 17))
1115 continue;
1116
1117 pr_info("Found in CAM: R1 %x R2 %x R3 %x\n", r[0], r[1], r[2]);
1118 if (port == ((r[0] >> 12) & priv->port_mask))
1119 cb(mac, vid, (r[0] >> 19) & 1, data);
1120 }
1121
1122 mutex_unlock(&priv->reg_mutex);
1123 return 0;
1124 }
1125
1126 static int rtl838x_port_fdb_del(struct dsa_switch *ds, int port,
1127 const unsigned char *addr, u16 vid)
1128 {
1129 struct rtl838x_switch_priv *priv = ds->priv;
1130 u64 mac = ether_addr_to_u64(addr);
1131 u32 key = rtl838x_hash_key(priv, mac, vid);
1132 int i;
1133 u32 r[3];
1134 u64 entry;
1135 int idx = -1;
1136 int err = 0;
1137
1138 pr_info("In %s, mac %llx, vid: %d, key: %x\n", __func__, mac, vid, key);
1139 mutex_lock(&priv->reg_mutex);
1140 for (i = 0; i < 4; i++) {
1141 entry = read_l2_entry_using_hash(key, i, r);
1142 if (!(r[0] >> 17)) /* Check for invalid entry */
1143 continue;
1144 if ((entry & 0x0fffffffffffffff) == ((mac << 12) | vid)) {
1145 idx = (key << 2) | i;
1146 break;
1147 }
1148 }
1149
1150 if (idx >= 0) {
1151 r[0] = r[1] = r[2] = 0;
1152 rtl838x_write_hash(idx, r);
1153 goto out;
1154 }
1155
1156 /* Check CAM for spillover from hash buckets */
1157 for (i = 0; i < 64; i++) {
1158 entry = rtl838x_read_cam(i, r);
1159 if ((entry & 0x0fffffffffffffff) == ((mac << 12) | vid)) {
1160 idx = i;
1161 break;
1162 }
1163 }
1164 if (idx >= 0) {
1165 r[0] = r[1] = r[2] = 0;
1166 rtl838x_write_cam(idx, r);
1167 goto out;
1168 }
1169 err = -ENOENT;
1170 out:
1171 mutex_unlock(&priv->reg_mutex);
1172 return err;
1173 }
1174
1175 static int rtl838x_port_fdb_add(struct dsa_switch *ds, int port,
1176 const unsigned char *addr, u16 vid)
1177 {
1178 struct rtl838x_switch_priv *priv = ds->priv;
1179 u64 mac = ether_addr_to_u64(addr);
1180 u32 key = rtl838x_hash_key(priv, mac, vid);
1181 int i;
1182 u32 r[3];
1183 int idx = -1;
1184 u64 entry;
1185 int err = 0;
1186
1187 mutex_lock(&priv->reg_mutex);
1188 for (i = 0; i < 4; i++) {
1189 entry = read_l2_entry_using_hash(key, i, r);
1190 if (!(r[0] >> 17)) { /* Check for invalid entry */
1191 idx = (key << 2) | i;
1192 break;
1193 }
1194 if ((entry & 0x0fffffffffffffff) == ((mac << 12) | vid)) {
1195 idx = (key << 2) | i;
1196 break;
1197 }
1198 }
1199 if (idx >= 0) {
1200 // Found for del: R1 60000 R2 901b0e9 R3 12b0e000, 901b0e912b0e000
1201 r[0] = 3 << 17 | port << 12; // Aging and port
1202 r[0] |= vid;
1203 r[1] = mac >> 16;
1204 r[2] = (mac & 0xffff) << 12; /* rvid = 0 */
1205 rtl838x_write_hash(idx, r);
1206 goto out;
1207 }
1208
1209 /* Hash bucket full, try CAM */
1210 for (i = 0; i < 64; i++) {
1211 entry = rtl838x_read_cam(i, r);
1212 if (!(r[0] >> 17)) { /* Check for invalid entry */
1213 if (idx < 0) /* First empty entry? */
1214 idx = i;
1215 break;
1216 } else if ((entry & 0x0fffffffffffffff) == ((mac << 12) | vid)) {
1217 pr_debug("Found entry in CAM\n");
1218 idx = i;
1219 break;
1220 }
1221 }
1222 if (idx >= 0) {
1223 r[0] = 3 << 17 | port << 12; // Aging
1224 r[0] |= vid;
1225 r[1] = mac >> 16;
1226 r[2] = (mac & 0xffff) << 12; /* rvid = 0 */
1227 rtl838x_write_cam(idx, r);
1228 goto out;
1229 }
1230 err = -ENOTSUPP;
1231 out:
1232 mutex_unlock(&priv->reg_mutex);
1233 return err;
1234 }
1235
1236 static void rtl838x_port_stp_state_set(struct dsa_switch *ds, int port,
1237 u8 state)
1238 {
1239 u32 cmd, msti = 0;
1240 u32 port_state[4];
1241 int index, bit, i;
1242
1243 struct rtl838x_switch_priv *priv = ds->priv;
1244 int n = priv->family_id == RTL8380_FAMILY_ID ? 2 : 4;
1245
1246 pr_info("%s: port %d state %2x\n", __func__, port, state);
1247 if (port >= priv->cpu_port)
1248 return;
1249
1250 mutex_lock(&priv->reg_mutex);
1251
1252 index = n - (port >> 4) - 1;
1253 bit = (port << 1) % 32;
1254
1255 if (priv->family_id == RTL8380_FAMILY_ID) {
1256 cmd = 1 << 15 /* Execute cmd */
1257 | 1 << 14 /* Read */
1258 | 2 << 12 /* Table type 0b10 */
1259 | (msti & 0xfff);
1260 } else {
1261 cmd = 1 << 16 /* Execute cmd */
1262 | 0 << 15 /* Read */
1263 | 5 << 12 /* Table type 0b101 */
1264 | (msti & 0xfff);
1265 }
1266 priv->r->exec_tbl0_cmd(cmd);
1267
1268 for (i = 0; i < n; i++)
1269 port_state[i] = sw_r32(priv->r->tbl_access_data_0(i));
1270
1271 pr_debug("Current state, port %d: %d\n", port, (port_state[index] >> bit) & 3);
1272 port_state[index] &= ~(3 << bit);
1273
1274 switch (state) {
1275 case BR_STATE_DISABLED: /* 0 */
1276 port_state[index] |= (0 << bit);
1277 break;
1278 case BR_STATE_BLOCKING: /* 4 */
1279 case BR_STATE_LISTENING: /* 1 */
1280 port_state[index] |= (1 << bit);
1281 break;
1282 case BR_STATE_LEARNING: /* 2 */
1283 port_state[index] |= (2 << bit);
1284 break;
1285 case BR_STATE_FORWARDING: /* 3*/
1286 port_state[index] |= (3 << bit);
1287 default:
1288 break;
1289 }
1290
1291 if (priv->family_id == RTL8380_FAMILY_ID) {
1292 cmd = 1 << 15 /* Execute cmd */
1293 | 0 << 14 /* Write */
1294 | 2 << 12 /* Table type 0b10 */
1295 | (msti & 0xfff);
1296 } else {
1297 cmd = 1 << 16 /* Execute cmd */
1298 | 1 << 15 /* Write */
1299 | 5 << 12 /* Table type 0b101 */
1300 | (msti & 0xfff);
1301 }
1302 for (i = 0; i < n; i++)
1303 sw_w32(port_state[i], priv->r->tbl_access_data_0(i));
1304 priv->r->exec_tbl0_cmd(cmd);
1305
1306 mutex_unlock(&priv->reg_mutex);
1307 }
1308
1309 static int rtl838x_port_mirror_add(struct dsa_switch *ds, int port,
1310 struct dsa_mall_mirror_tc_entry *mirror,
1311 bool ingress)
1312 {
1313 /* We support 4 mirror groups, one destination port per group */
1314 int group;
1315 struct rtl838x_switch_priv *priv = ds->priv;
1316
1317 pr_info("In %s\n", __func__);
1318
1319 for (group = 0; group < 4; group++) {
1320 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1321 break;
1322 }
1323 if (group >= 4) {
1324 for (group = 0; group < 4; group++) {
1325 if (priv->mirror_group_ports[group] < 0)
1326 break;
1327 }
1328 }
1329
1330 if (group >= 4)
1331 return -ENOSPC;
1332
1333 pr_debug("Using group %d\n", group);
1334 mutex_lock(&priv->reg_mutex);
1335 /* Enable mirroring to port across VLANs (bit 11) */
1336 sw_w32(1 << 11 | (mirror->to_local_port << 4) | 1, RTL838X_MIR_CTRL(group));
1337
1338 if (ingress && (sw_r32(RTL838X_MIR_SPM_CTRL(group)) & (1 << port))) {
1339 mutex_unlock(&priv->reg_mutex);
1340 return -EEXIST;
1341 }
1342 if ((!ingress) && (sw_r32(RTL838X_MIR_DPM_CTRL(group)) & (1 << port))) {
1343 mutex_unlock(&priv->reg_mutex);
1344 return -EEXIST;
1345 }
1346 if (ingress)
1347 sw_w32_mask(0, 1 << port, RTL838X_MIR_SPM_CTRL(group));
1348 else
1349 sw_w32_mask(0, 1 << port, RTL838X_MIR_DPM_CTRL(group));
1350
1351 priv->mirror_group_ports[group] = mirror->to_local_port;
1352 mutex_unlock(&priv->reg_mutex);
1353 return 0;
1354 }
1355
1356 static void rtl838x_port_mirror_del(struct dsa_switch *ds, int port,
1357 struct dsa_mall_mirror_tc_entry *mirror)
1358 {
1359 int group = 0;
1360 struct rtl838x_switch_priv *priv = ds->priv;
1361
1362 pr_info("In %s\n", __func__);
1363 for (group = 0; group < 4; group++) {
1364 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1365 break;
1366 }
1367 if (group >= 4)
1368 return;
1369
1370 mutex_lock(&priv->reg_mutex);
1371 if (mirror->ingress) {
1372 /* Ingress, clear source port matrix */
1373 sw_w32_mask(1 << port, 0, RTL838X_MIR_SPM_CTRL(group));
1374 } else {
1375 /* Egress, clear destination port matrix */
1376 sw_w32_mask(1 << port, 0, RTL838X_MIR_DPM_CTRL(group));
1377 }
1378
1379 if (!(sw_r32(RTL838X_MIR_DPM_CTRL(group)) || sw_r32(RTL838X_MIR_DPM_CTRL(group)))) {
1380 priv->mirror_group_ports[group] = -1;
1381 sw_w32(0, RTL838X_MIR_CTRL(group));
1382 }
1383
1384 mutex_unlock(&priv->reg_mutex);
1385 }
1386
1387
1388 void rtl838x_vlan_profile_dump(int index)
1389 {
1390 u32 profile;
1391
1392 if (index < 0 || index > 7)
1393 return;
1394
1395 profile = sw_r32(RTL838X_VLAN_PROFILE(index));
1396
1397 pr_info("VLAN %d: L2 learning: %d, L2 Unknown MultiCast Field %x",
1398 index, profile & 1, (profile >> 1) & 0x1ff);
1399 pr_info(" IPv4 Unkn MultiCast Field %x, IPv6 Unkn MultiCast Field: %x",
1400 (profile >> 10) & 0x1ff, (profile >> 19) & 0x1ff);
1401 }
1402
1403 static int rtl838x_vlan_filtering(struct dsa_switch *ds, int port,
1404 bool vlan_filtering)
1405 {
1406 struct rtl838x_switch_priv *priv = ds->priv;
1407
1408 pr_info("%s: port %d\n", __func__, port);
1409 mutex_lock(&priv->reg_mutex);
1410
1411 if (vlan_filtering) {
1412 /* Enable ingress and egress filtering */
1413 if (port != priv->cpu_port) {
1414 if (port < 16) {
1415 sw_w32_mask(0b10 << (port << 1),
1416 0b01 << (port << 1),
1417 RTL838X_VLAN_PORT_IGR_FLTR_0);
1418 } else {
1419 sw_w32_mask(0b10 << ((port - 16) << 1),
1420 0b01 << ((port - 16) << 1),
1421 RTL838X_VLAN_PORT_IGR_FLTR_1);
1422 }
1423 }
1424 sw_w32_mask(0, 1 << port, RTL838X_VLAN_PORT_EGR_FLTR);
1425 } else {
1426 /* Disable ingress and egress filtering */
1427 if (port != priv->cpu_port) {
1428 if (port < 16) {
1429 sw_w32_mask(0b11 << (port << 1),
1430 0,
1431 RTL838X_VLAN_PORT_IGR_FLTR_0);
1432 } else {
1433 sw_w32_mask(0b11 << ((port - 16) << 1),
1434 0,
1435 RTL838X_VLAN_PORT_IGR_FLTR_1);
1436 }
1437 }
1438 sw_w32_mask(1 << port, 0, RTL838X_VLAN_PORT_EGR_FLTR);
1439 }
1440
1441 /* We need to do something to the CPU-Port, too */
1442 mutex_unlock(&priv->reg_mutex);
1443
1444 return 0;
1445 }
1446
1447 static int rtl838x_vlan_prepare(struct dsa_switch *ds, int port,
1448 const struct switchdev_obj_port_vlan *vlan)
1449 {
1450 struct rtl838x_vlan_info info;
1451 struct rtl838x_switch_priv *priv = ds->priv;
1452
1453 pr_info("%s: port %d\n", __func__, port);
1454
1455 mutex_lock(&priv->reg_mutex);
1456
1457 priv->r->vlan_tables_read(1, &info);
1458
1459 pr_info("Tagged ports %llx, untag %llx, prof %x, MC# %d, UC# %d, MSTI %x\n",
1460 info.tagged_ports, info.untagged_ports, info.vlan_conf & 7,
1461 (info.vlan_conf & 8) >> 3, (info.vlan_conf & 16) >> 4,
1462 (info.vlan_conf & 0x3e0) >> 5);
1463
1464 mutex_unlock(&priv->reg_mutex);
1465 return 0;
1466 }
1467
1468 static void rtl838x_vlan_add(struct dsa_switch *ds, int port,
1469 const struct switchdev_obj_port_vlan *vlan)
1470 {
1471 struct rtl838x_vlan_info info;
1472 struct rtl838x_switch_priv *priv = ds->priv;
1473 int v;
1474 u64 portmask;
1475
1476 pr_info("%s port %d, vid_end %d, vid_end %d, flags %x\n", __func__,
1477 port, vlan->vid_begin, vlan->vid_end, vlan->flags);
1478
1479 if (vlan->vid_begin > 4095 || vlan->vid_end > 4095) {
1480 dev_err(priv->dev, "VLAN out of range: %d - %d",
1481 vlan->vid_begin, vlan->vid_end);
1482 return;
1483 }
1484
1485 mutex_lock(&priv->reg_mutex);
1486
1487 if (vlan->flags & BRIDGE_VLAN_INFO_PVID) {
1488 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
1489 /* Set both inner and outer PVID of the port */
1490 sw_w32((v << 16) | v, RTL838X_VLAN_PORT_PB_VLAN(port));
1491 }
1492 }
1493
1494 if (vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED) {
1495 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
1496 /* Get untagged port memberships of this vlan */
1497 priv->r->vlan_tables_read(v, &info);
1498 portmask = info.untagged_ports | (1 << port);
1499 pr_debug("Untagged ports, VLAN %d: %llx\n", v, portmask);
1500 priv->r->vlan_set_untagged(v, portmask);
1501 }
1502 } else {
1503 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
1504 /* Get tagged port memberships of this vlan */
1505 priv->r->vlan_tables_read(v, &info);
1506 portmask = info.tagged_ports | (1 << port);
1507 pr_debug("Tagged ports, VLAN %d: %llx\n", v, portmask);
1508 priv->r->vlan_set_tagged(v, portmask, info.vlan_conf);
1509 }
1510 }
1511 mutex_unlock(&priv->reg_mutex);
1512 }
1513
1514 static int rtl838x_vlan_del(struct dsa_switch *ds, int port,
1515 const struct switchdev_obj_port_vlan *vlan)
1516 {
1517 struct rtl838x_vlan_info info;
1518 struct rtl838x_switch_priv *priv = ds->priv;
1519 int v;
1520 u64 portmask;
1521
1522 pr_info("%s: port %d, vid_end %d, vid_end %d, flags %x\n", __func__,
1523 port, vlan->vid_begin, vlan->vid_end, vlan->flags);
1524
1525 if (vlan->vid_begin > 4095 || vlan->vid_end > 4095) {
1526 dev_err(priv->dev, "VLAN out of range: %d - %d",
1527 vlan->vid_begin, vlan->vid_end);
1528 return -ENOTSUPP;
1529 }
1530
1531 mutex_lock(&priv->reg_mutex);
1532
1533 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
1534 /* Reset both inner and out PVID of the port */
1535 sw_w32(0, RTL838X_VLAN_PORT_PB_VLAN(port));
1536
1537 if (vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED) {
1538 /* Get untagged port memberships of this vlan */
1539 priv->r->vlan_tables_read(v, &info);
1540 portmask = info.untagged_ports & (~(1 << port));
1541 pr_info("Untagged ports, VLAN %d: %llx\n", v, portmask);
1542 priv->r->vlan_set_untagged(v, portmask);
1543 }
1544
1545 /* Get tagged port memberships of this vlan */
1546 priv->r->vlan_tables_read(v, &info);
1547 portmask = info.tagged_ports & (~(1 << port));
1548 pr_info("Tagged ports, VLAN %d: %llx\n", v, portmask);
1549 priv->r->vlan_set_tagged(v, portmask, info.vlan_conf);
1550 }
1551 mutex_unlock(&priv->reg_mutex);
1552
1553 return 0;
1554 }
1555
1556 static void rtl838x_port_bridge_leave(struct dsa_switch *ds, int port,
1557 struct net_device *bridge)
1558 {
1559 struct rtl838x_switch_priv *priv = ds->priv;
1560 u64 port_bitmap = 1 << priv->cpu_port;
1561 int i;
1562
1563 pr_info("%s %x: %d", __func__, (u32)priv, port);
1564 mutex_lock(&priv->reg_mutex);
1565 for (i = 0; i < ds->num_ports; i++) {
1566 /* Remove this port from the port matrix of the other ports
1567 * in the same bridge. If the port is disabled, port matrix
1568 * is kept and not being setup until the port becomes enabled.
1569 * And the other port's port matrix cannot be broken when the
1570 * other port is still a VLAN-aware port.
1571 */
1572 if (dsa_is_user_port(ds, i) && i != port) {
1573 if (dsa_to_port(ds, i)->bridge_dev != bridge)
1574 continue;
1575 if (priv->ports[i].enable)
1576 priv->r->mask_port_iso_ctrl(1 << port, 0, i);
1577 priv->ports[i].pm |= 1 << port;
1578
1579 port_bitmap &= ~(1 << i);
1580 }
1581 }
1582
1583 /* Add all other ports to this port matrix. */
1584 if (priv->ports[port].enable)
1585 priv->r->mask_port_iso_ctrl(0, port_bitmap, port);
1586 priv->ports[port].pm &= ~port_bitmap;
1587 mutex_unlock(&priv->reg_mutex);
1588
1589 rtl838x_print_matrix();
1590 }
1591
1592 static int rtl838x_port_bridge_join(struct dsa_switch *ds, int port,
1593 struct net_device *bridge)
1594 {
1595 struct rtl838x_switch_priv *priv = ds->priv;
1596 u64 port_bitmap = 1 << priv->cpu_port;
1597 int i;
1598
1599 pr_info("%s %x: %d %llx", __func__, (u32)priv, port, port_bitmap);
1600 mutex_lock(&priv->reg_mutex);
1601 for (i = 0; i < ds->num_ports; i++) {
1602 /* Add this port to the port matrix of the other ports in the
1603 * same bridge. If the port is disabled, port matrix is kept
1604 * and not being setup until the port becomes enabled.
1605 */
1606 if (dsa_is_user_port(ds, i) && i != port) {
1607 if (dsa_to_port(ds, i)->bridge_dev != bridge)
1608 continue;
1609 if (priv->ports[i].enable)
1610 priv->r->mask_port_iso_ctrl(0, 1 << port, i);
1611 priv->ports[i].pm |= 1 << port;
1612
1613 port_bitmap |= 1 << i;
1614 }
1615 }
1616
1617 /* Add all other ports to this port matrix. */
1618 if (priv->ports[port].enable) {
1619 priv->r->mask_port_iso_ctrl(0, 1 << port, priv->cpu_port);
1620 priv->r->mask_port_iso_ctrl(0, port_bitmap, port);
1621 }
1622 priv->ports[port].pm |= port_bitmap;
1623 mutex_unlock(&priv->reg_mutex);
1624
1625 return 0;
1626 }
1627
1628 static int rtl838x_port_enable(struct dsa_switch *ds, int port,
1629 struct phy_device *phydev)
1630 {
1631 struct rtl838x_switch_priv *priv = ds->priv;
1632
1633 pr_info("%s: %x %d", __func__, (u32) priv, port);
1634 priv->ports[port].enable = true;
1635
1636 if (dsa_is_cpu_port(ds, port))
1637 return 0;
1638
1639 /* add port to switch mask of CPU_PORT */
1640 priv->r->mask_port_iso_ctrl(0, 1 << port, priv->cpu_port);
1641
1642 /* add all other ports in the same bridge to switch mask of port */
1643 priv->r->mask_port_iso_ctrl(0, priv->ports[port].pm, port);
1644
1645 /* enable PHY polling */
1646 sw_w32_mask(0, 1 << port, RTL838X_SMI_POLL_CTRL);
1647
1648 return 0;
1649 }
1650
1651 static void rtl838x_port_disable(struct dsa_switch *ds, int port)
1652 {
1653 struct rtl838x_switch_priv *priv = ds->priv;
1654
1655 pr_info("%s %x: %d", __func__, (u32)priv, port);
1656
1657 /* you can only disable user ports */
1658 if (!dsa_is_user_port(ds, port))
1659 return;
1660
1661 /* remove port from switch mask of CPU_PORT */
1662 priv->r->mask_port_iso_ctrl(1 << port, 0, priv->cpu_port);
1663
1664 /* remove all other ports in the same bridge from switch mask of port */
1665 priv->r->mask_port_iso_ctrl(priv->ports[port].pm, 0, port);
1666
1667 priv->ports[port].enable = false;
1668
1669 /* disable PHY polling */
1670 sw_w32_mask(1 << port, 0, RTL838X_SMI_POLL_CTRL);
1671 }
1672
1673 static int rtl838x_get_mac_eee(struct dsa_switch *ds, int port,
1674 struct ethtool_eee *e)
1675 {
1676 struct rtl838x_switch_priv *priv = ds->priv;
1677
1678 pr_info("%s: port %d", __func__, port);
1679 e->supported = SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full;
1680 if (sw_r32(priv->r->mac_force_mode_ctrl(port)) & (1 << 9))
1681 e->advertised |= ADVERTISED_100baseT_Full;
1682
1683 if (sw_r32(priv->r->mac_force_mode_ctrl(port)) & (1 << 10))
1684 e->advertised |= ADVERTISED_1000baseT_Full;
1685
1686 e->eee_enabled = priv->ports[port].eee_enabled;
1687 pr_info("enabled: %d, active %x\n", e->eee_enabled, e->advertised);
1688
1689 if (sw_r32(RTL838X_MAC_EEE_ABLTY) & (1 << port)) {
1690 e->lp_advertised = ADVERTISED_100baseT_Full;
1691 e->lp_advertised |= ADVERTISED_1000baseT_Full;
1692 }
1693
1694 e->eee_active = !!(e->advertised & e->lp_advertised);
1695 pr_info("active: %d, lp %x\n", e->eee_active, e->lp_advertised);
1696
1697 return 0;
1698 }
1699
1700 static int rtl838x_set_mac_eee(struct dsa_switch *ds, int port,
1701 struct ethtool_eee *e)
1702 {
1703 struct rtl838x_switch_priv *priv = ds->priv;
1704
1705 pr_info("%s: port %d", __func__, port);
1706 if (e->eee_enabled) {
1707 pr_info("Globally enabling EEE\n");
1708 sw_w32_mask(0x4, 0, RTL838X_SMI_GLB_CTRL);
1709 }
1710 if (e->eee_enabled) {
1711 pr_info("Enabling EEE for MAC %d\n", port);
1712 sw_w32_mask(0, 3 << 9, priv->r->mac_force_mode_ctrl(port));
1713 sw_w32_mask(0, 1 << port, RTL838X_EEE_PORT_TX_EN);
1714 sw_w32_mask(0, 1 << port, RTL838X_EEE_PORT_RX_EN);
1715 priv->ports[port].eee_enabled = true;
1716 e->eee_enabled = true;
1717 } else {
1718 pr_info("Disabling EEE for MAC %d\n", port);
1719 sw_w32_mask(3 << 9, 0, priv->r->mac_force_mode_ctrl(port));
1720 sw_w32_mask(1 << port, 0, RTL838X_EEE_PORT_TX_EN);
1721 sw_w32_mask(1 << port, 0, RTL838X_EEE_PORT_RX_EN);
1722 priv->ports[port].eee_enabled = false;
1723 e->eee_enabled = false;
1724 }
1725 return 0;
1726 }
1727
1728 static void rtl838x_phylink_mac_config(struct dsa_switch *ds, int port,
1729 unsigned int mode,
1730 const struct phylink_link_state *state)
1731 {
1732 struct rtl838x_switch_priv *priv = ds->priv;
1733 u32 reg;
1734
1735 pr_info("%s port %d, mode %x\n", __func__, port, mode);
1736
1737 if (port == priv->cpu_port) {
1738 /* Set Speed, duplex, flow control
1739 * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL
1740 * | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN
1741 * | MEDIA_SEL
1742 */
1743 if (priv->family_id == RTL8380_FAMILY_ID) {
1744 sw_w32(0x6192F, priv->r->mac_force_mode_ctrl(priv->cpu_port));
1745 /* allow CRC errors on CPU-port */
1746 sw_w32_mask(0, 0x8, RTL838X_MAC_PORT_CTRL(priv->cpu_port));
1747 } else {
1748 sw_w32_mask(0, 3, priv->r->mac_force_mode_ctrl(priv->cpu_port));
1749 }
1750 return;
1751 }
1752
1753 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
1754 if (mode == MLO_AN_PHY) {
1755 pr_info("PHY autonegotiates\n");
1756 reg |= 1 << 2;
1757 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
1758 return;
1759 }
1760
1761 if (mode != MLO_AN_FIXED)
1762 pr_info("Not fixed\n");
1763
1764 /* Clear id_mode_dis bit, and the existing port mode, let
1765 * RGMII_MODE_EN bet set by mac_link_{up,down}
1766 */
1767 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
1768
1769 if (state->pause & MLO_PAUSE_TXRX_MASK) {
1770 if (state->pause & MLO_PAUSE_TX)
1771 reg |= TX_PAUSE_EN;
1772 reg |= RX_PAUSE_EN;
1773 }
1774
1775 reg &= ~(3 << 4);
1776 switch (state->speed) {
1777 case SPEED_1000:
1778 reg |= 2 << 4;
1779 break;
1780 case SPEED_100:
1781 reg |= 1 << 4;
1782 break;
1783 }
1784
1785 reg &= ~(DUPLEX_FULL | FORCE_LINK_EN);
1786 if (state->link)
1787 reg |= FORCE_LINK_EN;
1788 if (state->duplex == DUPLEX_FULL)
1789 reg |= DUPLX_MODE;
1790
1791 // Disable AN
1792 reg &= ~(1 << 2);
1793 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
1794 }
1795
1796 static void rtl838x_phylink_mac_link_down(struct dsa_switch *ds, int port,
1797 unsigned int mode,
1798 phy_interface_t interface)
1799 {
1800 /* Stop TX/RX to port */
1801 sw_w32_mask(0x03, 0, RTL838X_MAC_PORT_CTRL(port));
1802 }
1803
1804 static void rtl838x_phylink_mac_link_up(struct dsa_switch *ds, int port,
1805 unsigned int mode,
1806 phy_interface_t interface,
1807 struct phy_device *phydev)
1808 {
1809 /* Restart TX/RX to port */
1810 sw_w32_mask(0, 0x03, RTL838X_MAC_PORT_CTRL(port));
1811 }
1812
1813 static void rtl838x_phylink_validate(struct dsa_switch *ds, int port,
1814 unsigned long *supported,
1815 struct phylink_link_state *state)
1816 {
1817 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
1818
1819 pr_info("In %s port %d", __func__, port);
1820
1821 if (!phy_interface_mode_is_rgmii(state->interface) &&
1822 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
1823 state->interface != PHY_INTERFACE_MODE_MII &&
1824 state->interface != PHY_INTERFACE_MODE_REVMII &&
1825 state->interface != PHY_INTERFACE_MODE_GMII &&
1826 state->interface != PHY_INTERFACE_MODE_QSGMII &&
1827 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
1828 state->interface != PHY_INTERFACE_MODE_SGMII) {
1829 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
1830 dev_err(ds->dev,
1831 "Unsupported interface: %d for port %d\n",
1832 state->interface, port);
1833 return;
1834 }
1835
1836 /* switch chip-id? if (priv->id == 0x8382) */
1837
1838 /* Allow all the expected bits */
1839 phylink_set(mask, Autoneg);
1840 phylink_set_port_modes(mask);
1841 phylink_set(mask, Pause);
1842 phylink_set(mask, Asym_Pause);
1843
1844 /* With the exclusion of MII and Reverse MII, we support Gigabit,
1845 * including Half duplex
1846 */
1847 if (state->interface != PHY_INTERFACE_MODE_MII &&
1848 state->interface != PHY_INTERFACE_MODE_REVMII) {
1849 phylink_set(mask, 1000baseT_Full);
1850 phylink_set(mask, 1000baseT_Half);
1851 }
1852
1853 /* On both the 8380 and 8382, ports 24-27 are SFP ports */
1854 if (port >= 24 && port <= 27)
1855 phylink_set(mask, 1000baseX_Full);
1856
1857 phylink_set(mask, 10baseT_Half);
1858 phylink_set(mask, 10baseT_Full);
1859 phylink_set(mask, 100baseT_Half);
1860 phylink_set(mask, 100baseT_Full);
1861
1862 bitmap_and(supported, supported, mask,
1863 __ETHTOOL_LINK_MODE_MASK_NBITS);
1864 bitmap_and(state->advertising, state->advertising, mask,
1865 __ETHTOOL_LINK_MODE_MASK_NBITS);
1866 }
1867
1868 static int rtl838x_phylink_mac_link_state(struct dsa_switch *ds, int port,
1869 struct phylink_link_state *state)
1870 {
1871 struct rtl838x_switch_priv *priv = ds->priv;
1872 u32 speed;
1873
1874 if (port < 0 || port > priv->cpu_port)
1875 return -EINVAL;
1876
1877 state->link = 0;
1878 if (sw_r32(RTL838X_MAC_LINK_STS) & (1 << port))
1879 state->link = 1;
1880 state->duplex = 0;
1881 if (sw_r32(RTL838X_MAC_LINK_DUP_STS) & (1 << port))
1882 state->duplex = 1;
1883
1884 speed = sw_r32(RTL838X_MAC_LINK_SPD_STS(port));
1885 speed >>= (port % 16) << 1;
1886 switch (speed & 0x3) {
1887 case 0:
1888 state->speed = SPEED_10;
1889 break;
1890 case 1:
1891 state->speed = SPEED_100;
1892 break;
1893 case 2:
1894 state->speed = SPEED_1000;
1895 break;
1896 case 3:
1897 if (port == 24 || port == 26) /* Internal serdes */
1898 state->speed = SPEED_2500;
1899 else
1900 state->speed = SPEED_100; /* Is in fact 500Mbit */
1901 }
1902
1903 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
1904 if (sw_r32(RTL838X_MAC_RX_PAUSE_STS) & (1 << port))
1905 state->pause |= MLO_PAUSE_RX;
1906 if (sw_r32(RTL838X_MAC_TX_PAUSE_STS) & (1 << port))
1907 state->pause |= MLO_PAUSE_TX;
1908 return 1;
1909 }
1910
1911 static int rtl838x_mdio_probe(struct rtl838x_switch_priv *priv)
1912 {
1913 struct device *dev = priv->dev;
1914 struct device_node *dn, *mii_np = dev->of_node;
1915 struct mii_bus *bus;
1916 int ret;
1917 u32 pn;
1918
1919 pr_info("In %s\n", __func__);
1920 mii_np = of_find_compatible_node(NULL, NULL, "realtek,rtl838x-mdio");
1921 if (mii_np) {
1922 pr_info("Found compatible MDIO node!\n");
1923 } else {
1924 dev_err(priv->dev, "no %s child node found", "mdio-bus");
1925 return -ENODEV;
1926 }
1927
1928 priv->mii_bus = of_mdio_find_bus(mii_np);
1929 if (!priv->mii_bus) {
1930 pr_info("Deferring probe of mdio bus\n");
1931 return -EPROBE_DEFER;
1932 }
1933 if (!of_device_is_available(mii_np))
1934 ret = -ENODEV;
1935
1936 bus = devm_mdiobus_alloc(priv->ds->dev);
1937 if (!bus)
1938 return -ENOMEM;
1939
1940 bus->name = "rtl838x slave mii";
1941 bus->read = &rtl838x_mdio_read;
1942 bus->write = &rtl838x_mdio_write;
1943 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d", bus->name, dev->id);
1944 bus->parent = dev;
1945 priv->ds->slave_mii_bus = bus;
1946 priv->ds->slave_mii_bus->priv = priv;
1947
1948 ret = mdiobus_register(priv->ds->slave_mii_bus);
1949 if (ret && mii_np) {
1950 of_node_put(dn);
1951 return ret;
1952 }
1953
1954 dn = mii_np;
1955 for_each_node_by_name(dn, "ethernet-phy") {
1956 if (of_property_read_u32(dn, "reg", &pn))
1957 continue;
1958
1959 // Check for the integrated SerDes of the RTL8380M first
1960 if (of_property_read_bool(dn, "phy-is-integrated")
1961 && priv->id == 0x8380 && pn >= 24) {
1962 pr_info("----> FÓUND A SERDES\n");
1963 priv->ports[pn].phy = PHY_RTL838X_SDS;
1964 continue;
1965 }
1966
1967 if (of_property_read_bool(dn, "phy-is-integrated")
1968 && !of_property_read_bool(dn, "sfp")) {
1969 priv->ports[pn].phy = PHY_RTL8218B_INT;
1970 continue;
1971 }
1972
1973 if (!of_property_read_bool(dn, "phy-is-integrated")
1974 && of_property_read_bool(dn, "sfp")) {
1975 priv->ports[pn].phy = PHY_RTL8214FC;
1976 continue;
1977 }
1978
1979 if (!of_property_read_bool(dn, "phy-is-integrated")
1980 && !of_property_read_bool(dn, "sfp")) {
1981 priv->ports[pn].phy = PHY_RTL8218B_EXT;
1982 continue;
1983 }
1984 }
1985
1986 /* Disable MAC polling the PHY so that we can start configuration */
1987 sw_w32(0x00000000, RTL838X_SMI_POLL_CTRL);
1988
1989 /* Enable PHY control via SoC */
1990 sw_w32_mask(0, 1 << 15, RTL838X_SMI_GLB_CTRL);
1991 /* Power on fibre ports and reset them if necessary */
1992 if (priv->ports[24].phy == PHY_RTL838X_SDS) {
1993 pr_info("Powering on fibre ports & reset\n");
1994 rtl8380_sds_power(24, 1);
1995 rtl8380_sds_power(26, 1);
1996 }
1997
1998 pr_info("%s done\n", __func__);
1999 return 0;
2000 }
2001
2002 static const struct dsa_switch_ops rtl838x_switch_ops = {
2003 .get_tag_protocol = rtl838x_get_tag_protocol,
2004 .setup = rtl838x_setup,
2005 .port_vlan_filtering = rtl838x_vlan_filtering,
2006 .port_vlan_prepare = rtl838x_vlan_prepare,
2007 .port_vlan_add = rtl838x_vlan_add,
2008 .port_vlan_del = rtl838x_vlan_del,
2009 .port_bridge_join = rtl838x_port_bridge_join,
2010 .port_bridge_leave = rtl838x_port_bridge_leave,
2011 .port_stp_state_set = rtl838x_port_stp_state_set,
2012 .set_ageing_time = rtl838x_set_l2aging,
2013 .port_fast_age = rtl838x_fast_age,
2014 .port_fdb_add = rtl838x_port_fdb_add,
2015 .port_fdb_del = rtl838x_port_fdb_del,
2016 .port_fdb_dump = rtl838x_port_fdb_dump,
2017 .port_enable = rtl838x_port_enable,
2018 .port_disable = rtl838x_port_disable,
2019 .port_mirror_add = rtl838x_port_mirror_add,
2020 .port_mirror_del = rtl838x_port_mirror_del,
2021 .phy_read = dsa_phy_read,
2022 .phy_write = dsa_phy_write,
2023 .get_strings = rtl838x_get_strings,
2024 .get_ethtool_stats = rtl838x_get_ethtool_stats,
2025 .get_sset_count = rtl838x_get_sset_count,
2026 .phylink_validate = rtl838x_phylink_validate,
2027 .phylink_mac_link_state = rtl838x_phylink_mac_link_state,
2028 .phylink_mac_config = rtl838x_phylink_mac_config,
2029 .phylink_mac_link_down = rtl838x_phylink_mac_link_down,
2030 .phylink_mac_link_up = rtl838x_phylink_mac_link_up,
2031 .set_mac_eee = rtl838x_set_mac_eee,
2032 .get_mac_eee = rtl838x_get_mac_eee,
2033
2034 };
2035
2036 static int __init rtl838x_sw_probe(struct platform_device *pdev)
2037 {
2038 int err = 0, i;
2039 struct rtl838x_switch_priv *priv;
2040 struct device *dev = &pdev->dev;
2041
2042 pr_info("Probing RTL838X switch device\n");
2043 if (!pdev->dev.of_node) {
2044 dev_err(dev, "No DT found\n");
2045 return -EINVAL;
2046 }
2047
2048 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
2049 if (!priv)
2050 return -ENOMEM;
2051
2052 priv->ds = dsa_switch_alloc(dev, DSA_MAX_PORTS);
2053
2054 if (!priv->ds)
2055 return -ENOMEM;
2056 priv->ds->dev = dev;
2057 priv->ds->priv = priv;
2058 priv->ds->ops = &rtl838x_switch_ops;
2059 priv->dev = dev;
2060
2061 priv->family_id = soc_info.family;
2062 priv->id = soc_info.id;
2063 if (soc_info.family == RTL8380_FAMILY_ID) {
2064 priv->cpu_port = RTL838X_CPU_PORT;
2065 priv->port_mask = 0x1f;
2066 priv->r = &rtl838x_reg;
2067 priv->ds->num_ports = 30;
2068 rtl8380_get_version(priv);
2069 } else {
2070 priv->cpu_port = RTL839X_CPU_PORT;
2071 priv->port_mask = 0x3f;
2072 priv->r = &rtl839x_reg;
2073 priv->ds->num_ports = 53;
2074 rtl8390_get_version(priv);
2075 }
2076 pr_info("Chip version %c\n", priv->version);
2077
2078 err = rtl838x_mdio_probe(priv);
2079 if (err) {
2080 /* Probing fails the 1st time because of missing ethernet driver
2081 * initialization. Use this to disable traffic in case the bootloader left if on
2082 */
2083 return err;
2084 }
2085 err = dsa_register_switch(priv->ds);
2086 if (err) {
2087 dev_err(dev, "Error registering switch: %d\n", err);
2088 return err;
2089 }
2090
2091 /* Enable link and media change interrupts. Are the SERDES masks needed? */
2092 sw_w32_mask(0, 3, priv->r->isr_glb_src);
2093 /* ... for all ports */
2094 priv->r->set_port_reg(0xffffffffffffffff, priv->r->isr_port_link_sts_chg);
2095 priv->r->set_port_reg(0xffffffffffffffff, priv->r->imr_port_link_sts_chg);
2096
2097 priv->link_state_irq = 20;
2098 if (priv->family_id == RTL8380_FAMILY_ID) {
2099 err = request_irq(priv->link_state_irq, rtl838x_switch_irq,
2100 IRQF_SHARED, "rtl8838x-link-state", priv->ds);
2101 } else {
2102 err = request_irq(priv->link_state_irq, rtl839x_switch_irq,
2103 IRQF_SHARED, "rtl8838x-link-state", priv->ds);
2104 }
2105 if (err) {
2106 dev_err(dev, "Error setting up switch interrupt.\n");
2107 /* Need to free allocated switch here */
2108 }
2109
2110 /* Enable interrupts for switch */
2111 sw_w32(0x1, priv->r->imr_glb);
2112
2113 rtl838x_get_l2aging(priv);
2114
2115 /* Clear all destination ports for mirror groups */
2116 for (i = 0; i < 4; i++)
2117 priv->mirror_group_ports[i] = -1;
2118
2119 return err;
2120 }
2121
2122 static int rtl838x_sw_remove(struct platform_device *pdev)
2123 {
2124 pr_info("Removing platform driver for rtl838x-sw\n");
2125 return 0;
2126 }
2127
2128 static const struct of_device_id rtl838x_switch_of_ids[] = {
2129 { .compatible = "realtek,rtl838x-switch"},
2130 { /* sentinel */ }
2131 };
2132
2133
2134 MODULE_DEVICE_TABLE(of, rtl838x_switch_of_ids);
2135
2136 static struct platform_driver rtl838x_switch_driver = {
2137 .probe = rtl838x_sw_probe,
2138 .remove = rtl838x_sw_remove,
2139 .driver = {
2140 .name = "rtl838x-switch",
2141 .pm = NULL,
2142 .of_match_table = rtl838x_switch_of_ids,
2143 },
2144 };
2145
2146 module_platform_driver(rtl838x_switch_driver);
2147
2148 MODULE_AUTHOR("B. Koblitz");
2149 MODULE_DESCRIPTION("RTL838X SoC Switch Driver");
2150 MODULE_LICENSE("GPL");
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