1 // SPDX-License-Identifier: GPL-2.0-only
3 #include <linux/etherdevice.h>
4 #include <linux/if_bridge.h>
5 #include <linux/iopoll.h>
6 #include <linux/mdio.h>
7 #include <linux/mfd/syscon.h>
8 #include <linux/module.h>
9 #include <linux/netdevice.h>
10 #include <linux/of_mdio.h>
11 #include <linux/of_net.h>
12 #include <linux/of_platform.h>
13 #include <linux/phylink.h>
14 #include <linux/phy_fixed.h>
16 #include <net/switchdev.h>
18 #include <asm/mach-rtl838x/mach-rtl838x.h>
21 #define RTL8380_VERSION_A 'A'
22 #define RTL8390_VERSION_A 'A'
23 #define RTL8380_VERSION_B 'B'
25 DEFINE_MUTEX(smi_lock
);
27 #define MIB_DESC(_size, _offset, _name) {.size = _size, .offset = _offset, .name = _name}
28 struct rtl838x_mib_desc
{
34 static inline void rtl838x_mask_port_reg(u64 clear
, u64 set
, int reg
)
36 sw_w32_mask((u32
)clear
, (u32
)set
, reg
);
39 static inline void rtl838x_set_port_reg(u64 set
, int reg
)
44 static inline u64
rtl838x_get_port_reg(int reg
)
46 return ((u64
) sw_r32(reg
));
49 static inline void rtl839x_mask_port_reg_be(u64 clear
, u64 set
, int reg
)
51 sw_w32_mask((u32
)(clear
>> 32), (u32
)(set
>> 32), reg
);
52 sw_w32_mask((u32
)(clear
& 0xffffffff), (u32
)(set
& 0xffffffff), reg
+ 4);
55 static inline void rtl839x_mask_port_reg_le(u64 clear
, u64 set
, int reg
)
57 sw_w32_mask((u32
)clear
, (u32
)set
, reg
);
58 sw_w32_mask((u32
)(clear
>> 32), (u32
)(set
>> 32), reg
+ 4);
61 static inline void rtl839x_set_port_reg_be(u64 set
, int reg
)
63 sw_w32(set
>> 32, reg
);
64 sw_w32(set
& 0xffffffff, reg
+ 4);
67 static inline void rtl839x_set_port_reg_le(u64 set
, int reg
)
70 sw_w32(set
>> 32, reg
+ 4);
73 static inline u64
rtl839x_get_port_reg_be(int reg
)
82 static inline u64
rtl839x_get_port_reg_le(int reg
)
84 u64 v
= sw_r32(reg
+ 4);
91 static inline int rtl838x_stat_port_std_mib(int p
)
93 return RTL838X_STAT_PORT_STD_MIB
+ (p
<< 8);
96 static inline int rtl839x_stat_port_std_mib(int p
)
98 return RTL839X_STAT_PORT_STD_MIB
+ (p
<< 8);
101 static inline int rtl838x_port_iso_ctrl(int p
)
103 return RTL838X_PORT_ISO_CTRL(p
);
106 static inline int rtl839x_port_iso_ctrl(int p
)
108 return RTL839X_PORT_ISO_CTRL(p
);
111 static inline void rtl838x_exec_tbl0_cmd(u32 cmd
)
113 sw_w32(cmd
, RTL838X_TBL_ACCESS_CTRL_0
);
114 do { } while (sw_r32(RTL838X_TBL_ACCESS_CTRL_0
) & (1 << 15));
117 static inline void rtl839x_exec_tbl0_cmd(u32 cmd
)
119 sw_w32(cmd
, RTL839X_TBL_ACCESS_CTRL_0
);
120 do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_0
) & (1 << 16));
123 static inline void rtl838x_exec_tbl1_cmd(u32 cmd
)
125 sw_w32(cmd
, RTL838X_TBL_ACCESS_CTRL_1
);
126 do { } while (sw_r32(RTL838X_TBL_ACCESS_CTRL_1
) & (1 << 15));
129 static inline void rtl839x_exec_tbl1_cmd(u32 cmd
)
131 sw_w32(cmd
, RTL839X_TBL_ACCESS_CTRL_1
);
132 do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_1
) & (1 << 16));
135 static inline int rtl838x_tbl_access_data_0(int i
)
137 return RTL838X_TBL_ACCESS_DATA_0
+ (i
<< 2);
140 static inline int rtl839x_tbl_access_data_0(int i
)
142 return RTL839X_TBL_ACCESS_DATA_0
+ (i
<< 2);
145 static inline int rtl838x_vlan_profile(int profile
)
147 return RTL838X_VLAN_PROFILE
+ (profile
<< 2);
150 static inline int rtl839x_vlan_profile(int profile
)
152 return RTL839X_VLAN_PROFILE
+ (profile
<< 3);
155 static inline int rtl838x_vlan_port_egr_filter(int port
)
157 return RTL838X_VLAN_PORT_EGR_FLTR
;
160 static inline int rtl839x_vlan_port_egr_filter(int port
)
162 return RTL839X_VLAN_PORT_EGR_FLTR
+ ((port
>> 5) << 2);
165 static inline int rtl838x_vlan_port_igr_filter(int port
)
167 return RTL838X_VLAN_PORT_IGR_FLTR
+ ((port
>> 4) << 2);
170 static inline int rtl839x_vlan_port_igr_filter(int port
)
172 return RTL839X_VLAN_PORT_IGR_FLTR
+ ((port
>> 4) << 2);
175 static inline int rtl838x_vlan_port_pb(int port
)
177 return RTL838X_VLAN_PORT_PB_VLAN
+ (port
<< 2);
180 static inline int rtl839x_vlan_port_pb(int port
)
182 return RTL839X_VLAN_PORT_PB_VLAN
+ (port
<< 2);
185 static void rtl839x_vlan_tables_read(u32 vlan
, struct rtl838x_vlan_info
*info
)
191 cmd
= 1 << 16 /* Execute cmd */
193 | 0 << 12 /* Table type 0b000 */
195 rtl839x_exec_tbl0_cmd(cmd
);
197 v
= sw_r32(rtl838x_tbl_access_data_0(0));
199 u
= sw_r32(rtl838x_tbl_access_data_0(1));
201 info
->tagged_ports
= v
>> 11;
203 w
= sw_r32(rtl838x_tbl_access_data_0(2));
205 info
->profile_id
= w
>> 30 | ((u
& 1) << 2);
206 info
->hash_mc
= !!(u
& 2);
207 info
->hash_uc
= !!(u
& 4);
208 info
->fid
= (u
>> 3) & 0xff;
210 cmd
= 1 << 16 /* Execute cmd */
212 | 0 << 12 /* Table type 0b000 */
214 rtl839x_exec_tbl1_cmd(cmd
);
215 v
= sw_r32(RTL838X_TBL_ACCESS_DATA_1(0));
217 v
|= sw_r32(RTL838X_TBL_ACCESS_DATA_1(1));
218 info
->untagged_ports
= v
>> 11;
221 static void rtl838x_vlan_tables_read(u32 vlan
, struct rtl838x_vlan_info
*info
)
225 cmd
= 1 << 15 /* Execute cmd */
227 | 0 << 12 /* Table type 0b00 */
229 rtl838x_exec_tbl0_cmd(cmd
);
230 info
->tagged_ports
= sw_r32(rtl838x_tbl_access_data_0(0));
231 v
= sw_r32(rtl838x_tbl_access_data_0(1));
232 info
->profile_id
= v
& 0x7;
233 info
->hash_mc
= !!(v
& 0x8);
234 info
->hash_uc
= !!(v
& 0x10);
235 info
->fid
= (v
>> 5) & 0x3f;
238 cmd
= 1 << 15 /* Execute cmd */
240 | 0 << 12 /* Table type 0b00 */
242 rtl838x_exec_tbl1_cmd(cmd
);
243 info
->untagged_ports
= sw_r32(RTL838X_TBL_ACCESS_DATA_1(0));
246 static void rtl839x_vlan_set_tagged(u32 vlan
, const struct rtl838x_vlan_info
*info
)
248 u32 cmd
= 1 << 16 /* Execute cmd */
249 | 1 << 15 /* Write */
250 | 0 << 12 /* Table type 0b00 */
253 u64 v
= info
->tagged_ports
<< 11;
255 v
|= info
->profile_id
>> 2;
256 v
|= info
->hash_mc
? 2 : 0;
257 v
|= info
->hash_uc
? 4 : 0;
258 v
|= ((u32
)info
->fid
) << 3;
259 rtl839x_set_port_reg_be(v
, rtl838x_tbl_access_data_0(0));
261 w
= info
->profile_id
;
262 sw_w32(w
<< 30, rtl838x_tbl_access_data_0(2));
263 rtl839x_exec_tbl0_cmd(cmd
);
266 static void rtl838x_vlan_set_tagged(u32 vlan
, const struct rtl838x_vlan_info
*info
)
268 u32 cmd
= 1 << 15 /* Execute cmd */
269 | 0 << 14 /* Write */
270 | 0 << 12 /* Table type 0b00 */
274 sw_w32(info
->tagged_ports
, rtl838x_tbl_access_data_0(0));
276 v
= info
->profile_id
;
277 v
|= info
->hash_mc
? 0x8 : 0;
278 v
|= info
->hash_uc
? 0x10 : 0;
279 v
|= ((u32
)info
->fid
) << 5;
281 sw_w32(v
, rtl838x_tbl_access_data_0(1));
282 rtl838x_exec_tbl0_cmd(cmd
);
285 static void rtl839x_vlan_set_untagged(u32 vlan
, u64 portmask
)
287 u32 cmd
= 1 << 16 /* Execute cmd */
288 | 1 << 15 /* Write */
289 | 0 << 12 /* Table type 0b00 */
291 rtl839x_set_port_reg_be(portmask
<< 11, RTL838X_TBL_ACCESS_DATA_1(0));
292 rtl839x_exec_tbl1_cmd(cmd
);
295 static void rtl838x_vlan_set_untagged(u32 vlan
, u64 portmask
)
297 u32 cmd
= 1 << 15 /* Execute cmd */
298 | 0 << 14 /* Write */
299 | 0 << 12 /* Table type 0b00 */
301 sw_w32(portmask
& 0x1fffffff, RTL838X_TBL_ACCESS_DATA_1(0));
302 rtl838x_exec_tbl1_cmd(cmd
);
305 static inline int rtl838x_mac_force_mode_ctrl(int p
)
307 return RTL838X_MAC_FORCE_MODE_CTRL
+ (p
<< 2);
310 static inline int rtl839x_mac_force_mode_ctrl(int p
)
312 return RTL839X_MAC_FORCE_MODE_CTRL
+ (p
<< 2);
315 static inline int rtl838x_mac_port_ctrl(int p
)
317 return RTL838X_MAC_PORT_CTRL(p
);
320 static inline int rtl839x_mac_port_ctrl(int p
)
322 return RTL839X_MAC_PORT_CTRL(p
);
325 static inline int rtl838x_l2_port_new_salrn(int p
)
327 return RTL838X_L2_PORT_NEW_SALRN(p
);
330 static inline int rtl839x_l2_port_new_salrn(int p
)
332 return RTL839X_L2_PORT_NEW_SALRN(p
);
335 static inline int rtl838x_l2_port_new_sa_fwd(int p
)
337 return RTL838X_L2_PORT_NEW_SA_FWD(p
);
340 static inline int rtl839x_l2_port_new_sa_fwd(int p
)
342 return RTL839X_L2_PORT_NEW_SA_FWD(p
);
345 static inline int rtl838x_mac_link_spd_sts(int p
)
347 return RTL838X_MAC_LINK_SPD_STS(p
);
350 static inline int rtl839x_mac_link_spd_sts(int p
)
352 return RTL839X_MAC_LINK_SPD_STS(p
);
355 static inline int rtl838x_mir_ctrl(int group
)
357 return RTL838X_MIR_CTRL(group
);
360 static inline int rtl839x_mir_ctrl(int group
)
362 return RTL839X_MIR_CTRL(group
);
365 static inline int rtl838x_mir_dpm(int group
)
367 return RTL838X_MIR_DPM_CTRL(group
);
370 static inline int rtl839x_mir_dpm(int group
)
372 return RTL839X_MIR_DPM_CTRL(group
);
375 static inline int rtl838x_mir_spm(int group
)
377 return RTL838X_MIR_SPM_CTRL(group
);
380 static inline int rtl839x_mir_spm(int group
)
382 return RTL839X_MIR_SPM_CTRL(group
);
385 static u64
rtl838x_read_l2_entry_using_hash(u32 hash
, u32 position
, struct rtl838x_l2_entry
*e
)
390 /* Search in SRAM, with hash and at position in hash bucket (0-3) */
391 u32 idx
= (0 << 14) | (hash
<< 2) | position
;
393 u32 cmd
= 1 << 16 /* Execute cmd */
395 | 0 << 13 /* Table type 0b00 */
398 sw_w32(cmd
, RTL838X_TBL_ACCESS_L2_CTRL
);
399 do { } while (sw_r32(RTL838X_TBL_ACCESS_L2_CTRL
) & (1 << 16));
400 r
[0] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(0));
401 r
[1] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(1));
402 r
[2] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(2));
404 e
->mac
[0] = (r
[1] >> 20);
405 e
->mac
[1] = (r
[1] >> 12);
406 e
->mac
[2] = (r
[1] >> 4);
407 e
->mac
[3] = (r
[1] & 0xf) << 4 | (r
[2] >> 28);
408 e
->mac
[4] = (r
[2] >> 20);
409 e
->mac
[5] = (r
[2] >> 12);
410 e
->is_static
= !!((r
[0] >> 19) & 1);
411 e
->vid
= r
[0] & 0xfff;
412 e
->rvid
= r
[2] & 0xfff;
413 e
->port
= (r
[0] >> 12) & 0x1f;
416 if (!(r
[0] >> 17)) /* Check for invalid entry */
420 pr_info("Found in Hash: R1 %x R2 %x R3 %x\n", r
[0], r
[1], r
[2]);
422 entry
= (((u64
) r
[1]) << 32) | (r
[2] & 0xfffff000) | (r
[0] & 0xfff);
426 static u64
rtl839x_read_l2_entry_using_hash(u32 hash
, u32 position
, struct rtl838x_l2_entry
*e
)
431 /* Search in SRAM, with hash and at position in hash bucket (0-3) */
432 u32 idx
= (0 << 14) | (hash
<< 2) | position
;
434 u32 cmd
= 1 << 17 /* Execute cmd */
436 | 0 << 14 /* Table type 0b00 */
439 sw_w32(cmd
, RTL839X_TBL_ACCESS_L2_CTRL
);
440 do { } while (sw_r32(RTL839X_TBL_ACCESS_L2_CTRL
) & (1 << 17));
441 r
[0] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(0));
442 r
[1] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(1));
443 r
[2] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(2));
445 /* Table contains different entry types, we need to identify the right one:
446 * Check for MC entries, first
448 e
->is_ip_mc
= !!(r
[2] & (1 << 31));
449 e
->is_ipv6_mc
= !!(r
[2] & (1 << 30));
450 e
->type
= L2_INVALID
;
452 e
->mac
[0] = (r
[0] >> 12);
453 e
->mac
[1] = (r
[0] >> 4);
454 e
->mac
[2] = ((r
[1] >> 28) | (r
[0] << 4));
455 e
->mac
[3] = (r
[1] >> 20);
456 e
->mac
[4] = (r
[1] >> 12);
457 e
->mac
[5] = (r
[1] >> 4);
459 /* Is it a unicast entry? check multicast bit */
460 if (!(e
->mac
[0] & 1)) {
461 e
->is_static
= !!((r
[2] >> 18) & 1);
462 e
->vid
= (r
[2] >> 4) & 0xfff;
463 e
->rvid
= (r
[0] >> 20) & 0xfff;
464 e
->port
= (r
[2] >> 24) & 0x3f;
465 e
->block_da
= !!(r
[2] & (1 << 19));
466 e
->block_sa
= !!(r
[2] & (1 << 20));
467 e
->suspended
= !!(r
[2] & (1 << 17));
468 e
->next_hop
= !!(r
[2] & (1 << 16));
470 pr_info("Found next hop entry, need to read data\n");
471 e
->age
= (r
[2] >> 21) & 3;
473 if (!(r
[2] & 0xc0fd0000)) /* Check for valid entry */
476 e
->type
= L2_UNICAST
;
479 e
->type
= L2_MULTICAST
;
480 e
->mc_portmask_index
= (r
[2] >> 6) & 0xfff;
485 e
->type
= IP4_MULTICAST
;
489 e
->type
= IP6_MULTICAST
;
492 entry
= (((u64
) r
[0]) << 44) | ((u64
)(r
[1] & 0xfffffff0) << 12) | ((r
[2] >> 4) & 0xfff);
496 static u64
rtl838x_read_cam(int idx
, struct rtl838x_l2_entry
*e
)
501 u32 cmd
= 1 << 16 /* Execute cmd */
503 | 1 << 13 /* Table type 0b01 */
505 sw_w32(cmd
, RTL838X_TBL_ACCESS_L2_CTRL
);
506 do { } while (sw_r32(RTL838X_TBL_ACCESS_L2_CTRL
) & (1 << 16));
507 r
[0] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(0));
508 r
[1] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(1));
509 r
[2] = sw_r32(RTL838X_TBL_ACCESS_L2_DATA(2));
511 e
->mac
[0] = (r
[1] >> 20);
512 e
->mac
[1] = (r
[1] >> 12);
513 e
->mac
[2] = (r
[1] >> 4);
514 e
->mac
[3] = (r
[1] & 0xf) << 4 | (r
[2] >> 28);
515 e
->mac
[4] = (r
[2] >> 20);
516 e
->mac
[5] = (r
[2] >> 12);
517 e
->is_static
= !!((r
[0] >> 19) & 1);
518 e
->vid
= r
[0] & 0xfff;
519 e
->rvid
= r
[2] & 0xfff;
520 e
->port
= (r
[0] >> 12) & 0x1f;
523 if (!(r
[0] >> 17)) /* Check for invalid entry */
527 pr_info("Found in CAM: R1 %x R2 %x R3 %x\n", r
[0], r
[1], r
[2]);
529 entry
= (((u64
) r
[1]) << 32) | (r
[2] & 0xfffff000) | (r
[0] & 0xfff);
533 static u64
rtl839x_read_cam(int idx
, struct rtl838x_l2_entry
*e
)
538 u32 cmd
= 1 << 17 /* Execute cmd */
540 | 1 << 14 /* Table type 0b01 */
542 sw_w32(cmd
, RTL839X_TBL_ACCESS_L2_CTRL
);
543 do { } while (sw_r32(RTL839X_TBL_ACCESS_L2_CTRL
) & (1 << 17));
544 r
[0] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(0));
545 r
[1] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(1));
546 r
[2] = sw_r32(RTL839X_TBL_ACCESS_L2_DATA(2));
548 e
->mac
[0] = (r
[0] >> 12);
549 e
->mac
[1] = (r
[0] >> 4);
550 e
->mac
[2] = ((r
[1] >> 28) | (r
[0] << 4));
551 e
->mac
[3] = (r
[1] >> 20);
552 e
->mac
[4] = (r
[1] >> 12);
553 e
->mac
[5] = (r
[1] >> 4);
554 e
->is_static
= !!((r
[2] >> 18) & 1);
555 e
->vid
= (r
[2] >> 4) & 0xfff;
556 e
->rvid
= (r
[0] >> 20) & 0xfff;
557 e
->port
= (r
[2] >> 24) & 0x3f;
560 if (!(r
[2] & 0x10fd0000)) /* Check for invalid entry */
564 pr_info("Found in CAM: R1 %x R2 %x R3 %x\n", r
[0], r
[1], r
[2]);
566 entry
= (((u64
) r
[0]) << 12) | ((r
[1] & 0xfffffff0) << 12) | ((r
[2] >> 4) & 0xfff);
570 static const struct rtl838x_reg rtl838x_reg
= {
571 .mask_port_reg_be
= rtl838x_mask_port_reg
,
572 .set_port_reg_be
= rtl838x_set_port_reg
,
573 .get_port_reg_be
= rtl838x_get_port_reg
,
574 .mask_port_reg_le
= rtl838x_mask_port_reg
,
575 .set_port_reg_le
= rtl838x_set_port_reg
,
576 .get_port_reg_le
= rtl838x_get_port_reg
,
577 .stat_port_rst
= RTL838X_STAT_PORT_RST
,
578 .stat_rst
= RTL838X_STAT_RST
,
579 .stat_port_std_mib
= rtl838x_stat_port_std_mib
,
580 .port_iso_ctrl
= rtl838x_port_iso_ctrl
,
581 .l2_ctrl_0
= RTL838X_L2_CTRL_0
,
582 .l2_ctrl_1
= RTL838X_L2_CTRL_1
,
583 .l2_port_aging_out
= RTL838X_L2_PORT_AGING_OUT
,
584 .smi_poll_ctrl
= RTL838X_SMI_POLL_CTRL
,
585 .l2_tbl_flush_ctrl
= RTL838X_L2_TBL_FLUSH_CTRL
,
586 .exec_tbl0_cmd
= rtl838x_exec_tbl0_cmd
,
587 .exec_tbl1_cmd
= rtl838x_exec_tbl1_cmd
,
588 .tbl_access_data_0
= rtl838x_tbl_access_data_0
,
589 .isr_glb_src
= RTL838X_ISR_GLB_SRC
,
590 .isr_port_link_sts_chg
= RTL838X_ISR_PORT_LINK_STS_CHG
,
591 .imr_port_link_sts_chg
= RTL838X_IMR_PORT_LINK_STS_CHG
,
592 .imr_glb
= RTL838X_IMR_GLB
,
593 .vlan_tables_read
= rtl838x_vlan_tables_read
,
594 .vlan_set_tagged
= rtl838x_vlan_set_tagged
,
595 .vlan_set_untagged
= rtl838x_vlan_set_untagged
,
596 .mac_force_mode_ctrl
= rtl838x_mac_force_mode_ctrl
,
597 .mac_port_ctrl
= rtl838x_mac_port_ctrl
,
598 .l2_port_new_salrn
= rtl838x_l2_port_new_salrn
,
599 .l2_port_new_sa_fwd
= rtl838x_l2_port_new_sa_fwd
,
600 .mir_ctrl
= rtl838x_mir_ctrl
,
601 .mir_dpm
= rtl838x_mir_dpm
,
602 .mir_spm
= rtl838x_mir_spm
,
603 .mac_link_sts
= RTL838X_MAC_LINK_STS
,
604 .mac_link_dup_sts
= RTL838X_MAC_LINK_DUP_STS
,
605 .mac_link_spd_sts
= rtl838x_mac_link_spd_sts
,
606 .mac_rx_pause_sts
= RTL838X_MAC_RX_PAUSE_STS
,
607 .mac_tx_pause_sts
= RTL838X_MAC_TX_PAUSE_STS
,
608 .read_l2_entry_using_hash
= rtl838x_read_l2_entry_using_hash
,
609 .read_cam
= rtl838x_read_cam
,
610 .vlan_profile
= rtl838x_vlan_profile
,
611 .vlan_port_egr_filter
= rtl838x_vlan_port_egr_filter
,
612 .vlan_port_igr_filter
= rtl838x_vlan_port_igr_filter
,
613 .vlan_port_pb
= rtl838x_vlan_port_pb
,
616 static const struct rtl838x_reg rtl839x_reg
= {
617 .mask_port_reg_be
= rtl839x_mask_port_reg_be
,
618 .set_port_reg_be
= rtl839x_set_port_reg_be
,
619 .get_port_reg_be
= rtl839x_get_port_reg_be
,
620 .mask_port_reg_le
= rtl839x_mask_port_reg_le
,
621 .set_port_reg_le
= rtl839x_set_port_reg_le
,
622 .get_port_reg_le
= rtl839x_get_port_reg_le
,
623 .stat_port_rst
= RTL839X_STAT_PORT_RST
,
624 .stat_rst
= RTL839X_STAT_RST
,
625 .stat_port_std_mib
= rtl839x_stat_port_std_mib
,
626 .port_iso_ctrl
= rtl839x_port_iso_ctrl
,
627 .l2_ctrl_0
= RTL839X_L2_CTRL_0
,
628 .l2_ctrl_1
= RTL839X_L2_CTRL_1
,
629 .l2_port_aging_out
= RTL839X_L2_PORT_AGING_OUT
,
630 .smi_poll_ctrl
= RTL839X_SMI_PORT_POLLING_CTRL
,
631 .l2_tbl_flush_ctrl
= RTL839X_L2_TBL_FLUSH_CTRL
,
632 .exec_tbl0_cmd
= rtl839x_exec_tbl0_cmd
,
633 .exec_tbl1_cmd
= rtl839x_exec_tbl1_cmd
,
634 .tbl_access_data_0
= rtl839x_tbl_access_data_0
,
635 .isr_glb_src
= RTL839X_ISR_GLB_SRC
,
636 .isr_port_link_sts_chg
= RTL839X_ISR_PORT_LINK_STS_CHG
,
637 .imr_port_link_sts_chg
= RTL839X_IMR_PORT_LINK_STS_CHG
,
638 .imr_glb
= RTL839X_IMR_GLB
,
639 .vlan_tables_read
= rtl839x_vlan_tables_read
,
640 .vlan_set_tagged
= rtl839x_vlan_set_tagged
,
641 .vlan_set_untagged
= rtl839x_vlan_set_untagged
,
642 .mac_force_mode_ctrl
= rtl839x_mac_force_mode_ctrl
,
643 .mac_port_ctrl
= rtl839x_mac_port_ctrl
,
644 .l2_port_new_salrn
= rtl839x_l2_port_new_salrn
,
645 .l2_port_new_sa_fwd
= rtl839x_l2_port_new_sa_fwd
,
646 .mir_ctrl
= rtl839x_mir_ctrl
,
647 .mir_dpm
= rtl839x_mir_dpm
,
648 .mir_spm
= rtl839x_mir_spm
,
649 .mac_link_sts
= RTL839X_MAC_LINK_STS
,
650 .mac_link_dup_sts
= RTL839X_MAC_LINK_DUP_STS
,
651 .mac_link_spd_sts
= rtl839x_mac_link_spd_sts
,
652 .mac_rx_pause_sts
= RTL839X_MAC_RX_PAUSE_STS
,
653 .mac_tx_pause_sts
= RTL839X_MAC_TX_PAUSE_STS
,
654 .read_l2_entry_using_hash
= rtl839x_read_l2_entry_using_hash
,
655 .read_cam
= rtl839x_read_cam
,
656 .vlan_profile
= rtl839x_vlan_profile
,
657 .vlan_port_egr_filter
= rtl839x_vlan_port_egr_filter
,
658 .vlan_port_igr_filter
= rtl839x_vlan_port_igr_filter
,
659 .vlan_port_pb
= rtl839x_vlan_port_pb
,
662 static const struct rtl838x_mib_desc rtl838x_mib
[] = {
663 MIB_DESC(2, 0xf8, "ifInOctets"),
664 MIB_DESC(2, 0xf0, "ifOutOctets"),
665 MIB_DESC(1, 0xec, "dot1dTpPortInDiscards"),
666 MIB_DESC(1, 0xe8, "ifInUcastPkts"),
667 MIB_DESC(1, 0xe4, "ifInMulticastPkts"),
668 MIB_DESC(1, 0xe0, "ifInBroadcastPkts"),
669 MIB_DESC(1, 0xdc, "ifOutUcastPkts"),
670 MIB_DESC(1, 0xd8, "ifOutMulticastPkts"),
671 MIB_DESC(1, 0xd4, "ifOutBroadcastPkts"),
672 MIB_DESC(1, 0xd0, "ifOutDiscards"),
673 MIB_DESC(1, 0xcc, ".3SingleCollisionFrames"),
674 MIB_DESC(1, 0xc8, ".3MultipleCollisionFrames"),
675 MIB_DESC(1, 0xc4, ".3DeferredTransmissions"),
676 MIB_DESC(1, 0xc0, ".3LateCollisions"),
677 MIB_DESC(1, 0xbc, ".3ExcessiveCollisions"),
678 MIB_DESC(1, 0xb8, ".3SymbolErrors"),
679 MIB_DESC(1, 0xb4, ".3ControlInUnknownOpcodes"),
680 MIB_DESC(1, 0xb0, ".3InPauseFrames"),
681 MIB_DESC(1, 0xac, ".3OutPauseFrames"),
682 MIB_DESC(1, 0xa8, "DropEvents"),
683 MIB_DESC(1, 0xa4, "tx_BroadcastPkts"),
684 MIB_DESC(1, 0xa0, "tx_MulticastPkts"),
685 MIB_DESC(1, 0x9c, "CRCAlignErrors"),
686 MIB_DESC(1, 0x98, "tx_UndersizePkts"),
687 MIB_DESC(1, 0x94, "rx_UndersizePkts"),
688 MIB_DESC(1, 0x90, "rx_UndersizedropPkts"),
689 MIB_DESC(1, 0x8c, "tx_OversizePkts"),
690 MIB_DESC(1, 0x88, "rx_OversizePkts"),
691 MIB_DESC(1, 0x84, "Fragments"),
692 MIB_DESC(1, 0x80, "Jabbers"),
693 MIB_DESC(1, 0x7c, "Collisions"),
694 MIB_DESC(1, 0x78, "tx_Pkts64Octets"),
695 MIB_DESC(1, 0x74, "rx_Pkts64Octets"),
696 MIB_DESC(1, 0x70, "tx_Pkts65to127Octets"),
697 MIB_DESC(1, 0x6c, "rx_Pkts65to127Octets"),
698 MIB_DESC(1, 0x68, "tx_Pkts128to255Octets"),
699 MIB_DESC(1, 0x64, "rx_Pkts128to255Octets"),
700 MIB_DESC(1, 0x60, "tx_Pkts256to511Octets"),
701 MIB_DESC(1, 0x5c, "rx_Pkts256to511Octets"),
702 MIB_DESC(1, 0x58, "tx_Pkts512to1023Octets"),
703 MIB_DESC(1, 0x54, "rx_Pkts512to1023Octets"),
704 MIB_DESC(1, 0x50, "tx_Pkts1024to1518Octets"),
705 MIB_DESC(1, 0x4c, "rx_StatsPkts1024to1518Octets"),
706 MIB_DESC(1, 0x48, "tx_Pkts1519toMaxOctets"),
707 MIB_DESC(1, 0x44, "rx_Pkts1519toMaxOctets"),
708 MIB_DESC(1, 0x40, "rxMacDiscards")
711 static irqreturn_t
rtl838x_switch_irq(int irq
, void *dev_id
)
713 struct dsa_switch
*ds
= dev_id
;
714 u32 status
= sw_r32(RTL838X_ISR_GLB_SRC
);
715 u32 ports
= sw_r32(RTL838X_ISR_PORT_LINK_STS_CHG
);
720 sw_w32(ports
, RTL838X_ISR_PORT_LINK_STS_CHG
);
721 pr_info("RTL8380 Link change: status: %x, ports %x\n", status
, ports
);
723 for (i
= 0; i
< 28; i
++) {
724 if (ports
& (1 << i
)) {
725 link
= sw_r32(RTL838X_MAC_LINK_STS
);
727 dsa_port_phylink_mac_change(ds
, i
, true);
729 dsa_port_phylink_mac_change(ds
, i
, false);
735 static irqreturn_t
rtl839x_switch_irq(int irq
, void *dev_id
)
737 struct dsa_switch
*ds
= dev_id
;
738 u32 status
= sw_r32(RTL839X_ISR_GLB_SRC
);
739 u64 ports
= rtl839x_get_port_reg_le(RTL839X_ISR_PORT_LINK_STS_CHG
);
744 rtl839x_set_port_reg_le(ports
, RTL839X_ISR_PORT_LINK_STS_CHG
);
745 pr_info("RTL8390 Link change: status: %x, ports %llx\n", status
, ports
);
747 for (i
= 0; i
< 52; i
++) {
748 if (ports
& (1ULL << i
)) {
749 link
= rtl839x_get_port_reg_le(RTL839X_MAC_LINK_STS
);
750 if (link
& (1ULL << i
))
751 dsa_port_phylink_mac_change(ds
, i
, true);
753 dsa_port_phylink_mac_change(ds
, i
, false);
759 struct fdb_update_work
{
760 struct work_struct work
;
761 struct net_device
*ndev
;
765 void rtl838x_fdb_sync(struct work_struct
*work
)
767 const struct fdb_update_work
*uw
=
768 container_of(work
, struct fdb_update_work
, work
);
769 struct switchdev_notifier_fdb_info info
;
774 while (uw
->macs
[i
]) {
775 action
= (uw
->macs
[i
] & (1ULL << 63)) ? SWITCHDEV_FDB_ADD_TO_BRIDGE
776 : SWITCHDEV_FDB_DEL_TO_BRIDGE
;
777 u64_to_ether_addr(uw
->macs
[i
] & 0xffffffffffffULL
, addr
);
778 info
.addr
= &addr
[0];
781 pr_debug("FDB entry %d: %llx, action %d\n", i
, uw
->macs
[0], action
);
782 call_switchdev_notifiers(action
, uw
->ndev
, &info
.info
, NULL
);
788 int rtl8380_sds_power(int mac
, int val
)
790 u32 mode
= (val
== 1) ? 0x4 : 0x9;
791 u32 offset
= (mac
== 24) ? 5 : 0;
793 if ((mac
!= 24) && (mac
!= 26)) {
794 pr_err("%s: not a fibre port: %d\n", __func__
, mac
);
798 sw_w32_mask(0x1f << offset
, mode
<< offset
, RTL838X_SDS_MODE_SEL
);
800 rtl8380_sds_rst(mac
);
805 int rtl8390_sds_power(int mac
, int val
)
807 u32 offset
= (mac
== 48) ? 0x0 : 0x100;
808 u32 mode
= val
? 0 : 1;
810 pr_info("In %s: mac %d, set %d\n", __func__
, mac
, val
);
812 if ((mac
!= 48) && (mac
!= 49)) {
813 pr_err("%s: not an SFP port: %d\n", __func__
, mac
);
817 // Set bit 1003. 1000 starts at 7c
818 sw_w32_mask(1 << 11, mode
<< 11, RTL839X_SDS12_13_PWR0
+ offset
);
823 static int rtl838x_smi_wait_op(int timeout
)
828 } while ((sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_1
) & 0x1) && (timeout
>= 0));
835 * Write to a register in a page of the PHY
837 int rtl838x_write_phy(u32 port
, u32 page
, u32 reg
, u32 val
)
843 if (port
> 31 || page
> 4095 || reg
> 31)
846 mutex_lock(&smi_lock
);
847 if (rtl838x_smi_wait_op(10000))
850 sw_w32(1 << port
, RTL838X_SMI_ACCESS_PHY_CTRL_0
);
853 sw_w32_mask(0xffff0000, val
<< 16, RTL838X_SMI_ACCESS_PHY_CTRL_2
);
855 park_page
= sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_1
) & ((0x1f << 15) | 0x2);
856 v
= reg
<< 20 | page
<< 3 | 0x4;
857 sw_w32(v
| park_page
, RTL838X_SMI_ACCESS_PHY_CTRL_1
);
858 sw_w32_mask(0, 1, RTL838X_SMI_ACCESS_PHY_CTRL_1
);
860 if (rtl838x_smi_wait_op(10000))
863 mutex_unlock(&smi_lock
);
867 mutex_unlock(&smi_lock
);
871 int rtl839x_write_phy(u32 port
, u32 page
, u32 reg
, u32 val
)
877 if (port
> 63 || page
> 4095 || reg
> 31)
880 mutex_lock(&smi_lock
);
881 /* Clear both port registers */
882 sw_w32(0, RTL839X_PHYREG_PORT_CTRL(0));
883 sw_w32(0, RTL839X_PHYREG_PORT_CTRL(0) + 4);
884 sw_w32_mask(0, 1 << port
, RTL839X_PHYREG_PORT_CTRL(port
));
886 sw_w32_mask(0xffff0000, val
<< 16, RTL839X_PHYREG_DATA_CTRL
);
888 v
= reg
<< 5 | page
<< 10 | ((page
== 0x1fff) ? 0x1f : 0) << 23;
889 sw_w32(v
, RTL839X_PHYREG_ACCESS_CTRL
);
891 sw_w32(0x1ff, RTL839X_PHYREG_CTRL
);
893 v
|= 1 << 3 | 1; /* Write operation and execute */
894 sw_w32(v
, RTL839X_PHYREG_ACCESS_CTRL
);
897 } while (sw_r32(RTL839X_PHYREG_ACCESS_CTRL
) & 0x1);
899 if (sw_r32(RTL839X_PHYREG_ACCESS_CTRL
) & 0x2)
902 mutex_unlock(&smi_lock
);
907 * Reads a register in a page from the PHY
909 int rtl838x_read_phy(u32 port
, u32 page
, u32 reg
, u32
*val
)
919 if (page
> 4095 || reg
> 31)
922 mutex_lock(&smi_lock
);
924 if (rtl838x_smi_wait_op(10000))
927 sw_w32_mask(0xffff0000, port
<< 16, RTL838X_SMI_ACCESS_PHY_CTRL_2
);
929 park_page
= sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_1
) & ((0x1f << 15) | 0x2);
930 v
= reg
<< 20 | page
<< 3;
931 sw_w32(v
| park_page
, RTL838X_SMI_ACCESS_PHY_CTRL_1
);
932 sw_w32_mask(0, 1, RTL838X_SMI_ACCESS_PHY_CTRL_1
);
934 if (rtl838x_smi_wait_op(10000))
937 *val
= sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_2
) & 0xffff;
939 mutex_unlock(&smi_lock
);
943 mutex_unlock(&smi_lock
);
947 int rtl839x_read_phy(u32 port
, u32 page
, u32 reg
, u32
*val
)
951 if (port
> 63 || page
> 4095 || reg
> 31)
954 mutex_lock(&smi_lock
);
956 sw_w32_mask(0xffff0000, port
<< 16, RTL839X_PHYREG_DATA_CTRL
);
957 v
= reg
<< 5 | page
<< 10 | ((page
== 0x1fff) ? 0x1f : 0) << 23;
958 sw_w32(v
, RTL839X_PHYREG_ACCESS_CTRL
);
960 sw_w32(0x1ff, RTL839X_PHYREG_CTRL
);
963 sw_w32(v
, RTL839X_PHYREG_ACCESS_CTRL
);
966 } while (sw_r32(RTL839X_PHYREG_ACCESS_CTRL
) & 0x1);
968 *val
= sw_r32(RTL839X_PHYREG_DATA_CTRL
) & 0xffff;
970 mutex_unlock(&smi_lock
);
974 static int read_phy(u32 port
, u32 page
, u32 reg
, u32
*val
)
976 if (soc_info
.family
== RTL8390_FAMILY_ID
)
977 return rtl839x_read_phy(port
, page
, reg
, val
);
979 return rtl838x_read_phy(port
, page
, reg
, val
);
982 static int write_phy(u32 port
, u32 page
, u32 reg
, u32 val
)
984 if (soc_info
.family
== RTL8390_FAMILY_ID
)
985 return rtl839x_write_phy(port
, page
, reg
, val
);
987 return rtl838x_write_phy(port
, page
, reg
, val
);
991 * Write to an mmd register of the PHY
993 int rtl838x_write_mmd_phy(u32 port
, u32 addr
, u32 reg
, u32 val
)
997 pr_debug("MMD write: port %d, dev %d, reg %d, val %x\n", port
, addr
, reg
, val
);
999 mutex_lock(&smi_lock
);
1001 if (rtl838x_smi_wait_op(10000))
1004 sw_w32(1 << port
, RTL838X_SMI_ACCESS_PHY_CTRL_0
);
1007 sw_w32_mask(0xffff0000, val
<< 16, RTL838X_SMI_ACCESS_PHY_CTRL_2
);
1009 sw_w32_mask(0x1f << 16, addr
<< 16, RTL838X_SMI_ACCESS_PHY_CTRL_3
);
1010 sw_w32_mask(0xffff, reg
, RTL838X_SMI_ACCESS_PHY_CTRL_3
);
1011 /* mmd-access | write | cmd-start */
1012 v
= 1 << 1 | 1 << 2 | 1;
1013 sw_w32(v
, RTL838X_SMI_ACCESS_PHY_CTRL_1
);
1015 if (rtl838x_smi_wait_op(10000))
1018 mutex_unlock(&smi_lock
);
1022 mutex_unlock(&smi_lock
);
1027 * Read an mmd register of the PHY
1029 int rtl838x_read_mmd_phy(u32 port
, u32 addr
, u32 reg
, u32
*val
)
1033 mutex_lock(&smi_lock
);
1035 if (rtl838x_smi_wait_op(10000))
1038 sw_w32(1 << port
, RTL838X_SMI_ACCESS_PHY_CTRL_0
);
1041 sw_w32_mask(0xffff0000, port
<< 16, RTL838X_SMI_ACCESS_PHY_CTRL_2
);
1043 v
= addr
<< 16 | reg
;
1044 sw_w32(v
, RTL838X_SMI_ACCESS_PHY_CTRL_3
);
1046 /* mmd-access | read | cmd-start */
1047 v
= 1 << 1 | 0 << 2 | 1;
1048 sw_w32(v
, RTL838X_SMI_ACCESS_PHY_CTRL_1
);
1050 if (rtl838x_smi_wait_op(10000))
1053 *val
= sw_r32(RTL838X_SMI_ACCESS_PHY_CTRL_2
) & 0xffff;
1055 mutex_unlock(&smi_lock
);
1059 mutex_unlock(&smi_lock
);
1063 static void rtl8380_get_version(struct rtl838x_switch_priv
*priv
)
1065 u32 rw_save
, info_save
;
1069 pr_debug("SoC ID: %4x: %s\n", priv
->id
, soc_info
.name
);
1071 pr_err("Unknown chip id (%04x)\n", priv
->id
);
1073 rw_save
= sw_r32(RTL838X_INT_RW_CTRL
);
1074 sw_w32(rw_save
| 0x3, RTL838X_INT_RW_CTRL
);
1076 info_save
= sw_r32(RTL838X_CHIP_INFO
);
1077 sw_w32(info_save
| 0xA0000000, RTL838X_CHIP_INFO
);
1079 info
= sw_r32(RTL838X_CHIP_INFO
);
1080 sw_w32(info_save
, RTL838X_CHIP_INFO
);
1081 sw_w32(rw_save
, RTL838X_INT_RW_CTRL
);
1083 if ((info
& 0xFFFF) == 0x6275) {
1084 if (((info
>> 16) & 0x1F) == 0x1)
1085 priv
->version
= RTL8380_VERSION_A
;
1086 else if (((info
>> 16) & 0x1F) == 0x2)
1087 priv
->version
= RTL8380_VERSION_B
;
1089 priv
->version
= RTL8380_VERSION_B
;
1091 priv
->version
= '-';
1095 static void rtl8390_get_version(struct rtl838x_switch_priv
*priv
)
1099 sw_w32_mask(0xf << 28, 0xa << 28, RTL839X_CHIP_INFO
);
1100 info
= sw_r32(RTL839X_CHIP_INFO
);
1101 pr_info("Chip-Info: %x\n", info
);
1102 priv
->version
= RTL8390_VERSION_A
;
1105 int dsa_phy_read(struct dsa_switch
*ds
, int phy_addr
, int phy_reg
)
1109 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1111 if (phy_addr
>= 24 && phy_addr
<= 27
1112 && priv
->ports
[24].phy
== PHY_RTL838X_SDS
) {
1115 val
= sw_r32(MAPLE_SDS4_FIB_REG0r
+ offset
+ (phy_reg
<< 2)) & 0xffff;
1119 read_phy(phy_addr
, 0, phy_reg
, &val
);
1123 int dsa_phy_write(struct dsa_switch
*ds
, int phy_addr
, int phy_reg
, u16 val
)
1126 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1128 if (phy_addr
>= 24 && phy_addr
<= 27
1129 && priv
->ports
[24].phy
== PHY_RTL838X_SDS
) {
1132 sw_w32(val
, MAPLE_SDS4_FIB_REG0r
+ offset
+ (phy_reg
<< 2));
1135 return write_phy(phy_addr
, 0, phy_reg
, val
);
1138 static int rtl838x_mdio_read(struct mii_bus
*bus
, int addr
, int regnum
)
1141 struct rtl838x_switch_priv
*priv
= bus
->priv
;
1143 ret
= dsa_phy_read(priv
->ds
, addr
, regnum
);
1147 static int rtl838x_mdio_write(struct mii_bus
*bus
, int addr
, int regnum
,
1150 struct rtl838x_switch_priv
*priv
= bus
->priv
;
1152 return dsa_phy_write(priv
->ds
, addr
, regnum
, val
);
1155 static void rtl838x_enable_phy_polling(struct rtl838x_switch_priv
*priv
)
1161 /* Enable all ports with a PHY, including the SFP-ports */
1162 for (i
= 0; i
< priv
->cpu_port
; i
++) {
1163 if (priv
->ports
[i
].phy
)
1167 pr_info("%s: %16llx\n", __func__
, v
);
1168 priv
->r
->set_port_reg_le(v
, priv
->r
->smi_poll_ctrl
);
1170 /* PHY update complete */
1171 if (priv
->family_id
== RTL8390_FAMILY_ID
)
1172 sw_w32_mask(0, 1 << 7, RTL839X_SMI_GLB_CTRL
);
1174 sw_w32_mask(0, 0x8000, RTL838X_SMI_GLB_CTRL
);
1177 void rtl839x_print_matrix(void)
1179 volatile u64
*ptr
= RTL838X_SW_BASE
+ RTL839X_PORT_ISO_CTRL(0);
1182 for (i
= 0; i
< 52; i
+= 4)
1183 pr_info("> %16llx %16llx %16llx %16llx\n",
1184 ptr
[i
+ 0], ptr
[i
+ 1], ptr
[i
+ 2], ptr
[i
+ 3]);
1185 pr_info("CPU_PORT> %16llx\n", ptr
[52]);
1188 void rtl838x_print_matrix(void)
1190 unsigned volatile int *ptr
= RTL838X_SW_BASE
+ RTL838X_PORT_ISO_CTRL(0);
1193 if (soc_info
.family
== RTL8390_FAMILY_ID
)
1194 return rtl839x_print_matrix();
1196 for (i
= 0; i
< 28; i
+= 8)
1197 pr_info("> %8x %8x %8x %8x %8x %8x %8x %8x\n",
1198 ptr
[i
+ 0], ptr
[i
+ 1], ptr
[i
+ 2], ptr
[i
+ 3], ptr
[i
+ 4], ptr
[i
+ 5],
1199 ptr
[i
+ 6], ptr
[i
+ 7]);
1200 pr_info("CPU_PORT> %8x\n", ptr
[28]);
1203 static void rtl838x_init_stats(struct rtl838x_switch_priv
*priv
)
1205 mutex_lock(&priv
->reg_mutex
);
1207 /* Enable statistics module: all counters plus debug.
1208 * On RTL839x all counters are enabled by default
1210 if (priv
->family_id
== RTL8380_FAMILY_ID
)
1211 sw_w32_mask(0, 3, RTL838X_STAT_CTRL
);
1213 /* Reset statistics counters */
1214 sw_w32_mask(0, 1, priv
->r
->stat_rst
);
1216 mutex_unlock(&priv
->reg_mutex
);
1219 static int rtl838x_setup(struct dsa_switch
*ds
)
1222 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1223 u64 port_bitmap
= 1ULL << priv
->cpu_port
;
1225 pr_info("%s called\n", __func__
);
1227 /* Disable MAC polling the PHY so that we can start configuration */
1228 priv
->r
->set_port_reg_le(0ULL, priv
->r
->smi_poll_ctrl
);
1230 for (i
= 0; i
< ds
->num_ports
; i
++)
1231 priv
->ports
[i
].enable
= false;
1232 priv
->ports
[priv
->cpu_port
].enable
= true;
1234 /* Isolate ports from each other: traffic only CPU <-> port */
1235 /* Setting bit j in register RTL838X_PORT_ISO_CTRL(i) allows
1236 * traffic from source port i to destination port j
1238 for (i
= 0; i
< priv
->cpu_port
; i
++) {
1239 if (priv
->ports
[i
].phy
) {
1240 priv
->r
->set_port_reg_be(1ULL << priv
->cpu_port
| 1ULL << i
,
1241 priv
->r
->port_iso_ctrl(i
));
1242 port_bitmap
|= 1ULL << i
;
1245 priv
->r
->set_port_reg_be(port_bitmap
, priv
->r
->port_iso_ctrl(priv
->cpu_port
));
1247 rtl838x_print_matrix();
1249 rtl838x_init_stats(priv
);
1251 /* Enable MAC Polling PHY again */
1252 rtl838x_enable_phy_polling(priv
);
1253 pr_info("Please wait until PHY is settled\n");
1258 static void rtl838x_get_strings(struct dsa_switch
*ds
,
1259 int port
, u32 stringset
, u8
*data
)
1263 if (stringset
!= ETH_SS_STATS
)
1266 for (i
= 0; i
< ARRAY_SIZE(rtl838x_mib
); i
++)
1267 strncpy(data
+ i
* ETH_GSTRING_LEN
, rtl838x_mib
[i
].name
,
1271 static void rtl838x_get_ethtool_stats(struct dsa_switch
*ds
, int port
,
1274 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1275 const struct rtl838x_mib_desc
*mib
;
1279 for (i
= 0; i
< ARRAY_SIZE(rtl838x_mib
); i
++) {
1280 mib
= &rtl838x_mib
[i
];
1282 data
[i
] = sw_r32(priv
->r
->stat_port_std_mib(port
) + 252 - mib
->offset
);
1283 if (mib
->size
== 2) {
1284 high
= sw_r32(priv
->r
->stat_port_std_mib(port
) + 252 - mib
->offset
- 4);
1285 data
[i
] |= high
<< 32;
1290 static int rtl838x_get_sset_count(struct dsa_switch
*ds
, int port
, int sset
)
1292 if (sset
!= ETH_SS_STATS
)
1295 return ARRAY_SIZE(rtl838x_mib
);
1298 static enum dsa_tag_protocol
1299 rtl838x_get_tag_protocol(struct dsa_switch
*ds
, int port
)
1301 /* The switch does not tag the frames, instead internally the header
1302 * structure for each packet is tagged accordingly.
1304 return DSA_TAG_PROTO_TRAILER
;
1307 static int rtl838x_get_l2aging(struct rtl838x_switch_priv
*priv
)
1309 int t
= sw_r32(priv
->r
->l2_ctrl_1
);
1311 t
&= priv
->family_id
== RTL8380_FAMILY_ID
? 0x7fffff : 0x1FFFFF;
1313 if (priv
->family_id
== RTL8380_FAMILY_ID
)
1314 t
= t
* 128 / 625; /* Aging time in seconds. 0: L2 aging disabled */
1318 pr_info("L2 AGING time: %d sec\n", t
);
1319 pr_info("Dynamic aging for ports: %x\n", sw_r32(priv
->r
->l2_port_aging_out
));
1324 * Set Switch L2 Aging time, t is time in milliseconds
1325 * t = 0: aging is disabled
1327 static int rtl838x_set_l2aging(struct dsa_switch
*ds
, u32 t
)
1329 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1330 int t_max
= priv
->family_id
== RTL8380_FAMILY_ID
? 0x7fffff : 0x1FFFFF;
1332 /* Convert time in mseconds to internal value */
1333 if (t
> 0x10000000) { /* Set to maximum */
1336 if (priv
->family_id
== RTL8380_FAMILY_ID
)
1337 t
= ((t
* 625) / 1000 + 127) / 128;
1339 t
= (t
* 5 + 2) / 3;
1341 sw_w32(t
, priv
->r
->l2_ctrl_1
);
1345 static void rtl838x_fast_age(struct dsa_switch
*ds
, int port
)
1347 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1348 int s
= priv
->family_id
== RTL8390_FAMILY_ID
? 2 : 0;
1350 pr_info("FAST AGE port %d\n", port
);
1351 mutex_lock(&priv
->reg_mutex
);
1352 /* RTL838X_L2_TBL_FLUSH_CTRL register bits, 839x has 1 bit larger
1354 * 0-4: Replacing port
1355 * 5-9: Flushed/replaced port
1357 * 22: Entry types: 1: dynamic, 0: also static
1358 * 23: Match flush port
1360 * 25: Flush (0) or replace (1) L2 entries
1361 * 26: Status of action (1: Start, 0: Done)
1363 sw_w32(1 << (26 + s
) | 1 << (23 + s
) | port
<< (5 + (s
/ 2)), priv
->r
->l2_tbl_flush_ctrl
);
1365 do { } while (sw_r32(priv
->r
->l2_tbl_flush_ctrl
) & (1 << (26 + s
)));
1367 mutex_unlock(&priv
->reg_mutex
);
1371 * Applies the same hash algorithm as the one used currently by the ASIC
1373 static u32
rtl838x_hash(struct rtl838x_switch_priv
*priv
, u64 seed
)
1377 if (sw_r32(priv
->r
->l2_ctrl_0
) & 1) {
1378 h1
= (seed
>> 11) & 0x7ff;
1379 h1
= ((h1
& 0x1f) << 6) | ((h1
>> 5) & 0x3f);
1381 h2
= (seed
>> 33) & 0x7ff;
1382 h2
= ((h2
& 0x3f) << 5) | ((h2
>> 6) & 0x1f);
1384 h3
= (seed
>> 44) & 0x7ff;
1385 h3
= ((h3
& 0x7f) << 4) | ((h3
>> 7) & 0xf);
1387 h
= h1
^ h2
^ h3
^ ((seed
>> 55) & 0x1ff);
1388 h
^= ((seed
>> 22) & 0x7ff) ^ (seed
& 0x7ff);
1390 h
= ((seed
>> 55) & 0x1ff) ^ ((seed
>> 44) & 0x7ff)
1391 ^ ((seed
>> 33) & 0x7ff) ^ ((seed
>> 22) & 0x7ff)
1392 ^ ((seed
>> 11) & 0x7ff) ^ (seed
& 0x7ff);
1398 static u32
rtl839x_hash(struct rtl838x_switch_priv
*priv
, u64 seed
)
1402 if (sw_r32(priv
->r
->l2_ctrl_0
) & 1) {
1403 h1
= (u32
) (((seed
>> 60) & 0x3f) ^ ((seed
>> 54) & 0x3f)
1404 ^ ((seed
>> 36) & 0x3f) ^ ((seed
>> 30) & 0x3f)
1405 ^ ((seed
>> 12) & 0x3f) ^ ((seed
>> 6) & 0x3f));
1406 h2
= (u32
) (((seed
>> 48) & 0x3f) ^ ((seed
>> 42) & 0x3f)
1407 ^ ((seed
>> 24) & 0x3f) ^ ((seed
>> 18) & 0x3f)
1412 ^ ((((seed
>> 48) & 0x3f) << 6) | ((seed
>> 54) & 0x3f))
1413 ^ ((seed
>> 36) & 0xfff) ^ ((seed
>> 24) & 0xfff)
1414 ^ ((seed
>> 12) & 0xfff) ^ (seed
& 0xfff);
1420 static u64
rtl838x_hash_key(struct rtl838x_switch_priv
*priv
, u64 mac
, u32 vid
)
1422 if (priv
->family_id
== RTL8380_FAMILY_ID
)
1423 return rtl838x_hash(priv
, mac
<< 12 | vid
);
1425 return rtl839x_hash(priv
, mac
<< 12 | vid
);
1428 static void rtl838x_write_cam(int idx
, u32
*r
)
1430 u32 cmd
= 1 << 16 /* Execute cmd */
1431 | 1 << 15 /* Read */
1432 | 1 << 13 /* Table type 0b01 */
1435 sw_w32(r
[0], RTL838X_TBL_ACCESS_L2_DATA(0));
1436 sw_w32(r
[1], RTL838X_TBL_ACCESS_L2_DATA(1));
1437 sw_w32(r
[2], RTL838X_TBL_ACCESS_L2_DATA(2));
1439 sw_w32(cmd
, RTL838X_TBL_ACCESS_L2_CTRL
);
1440 do { } while (sw_r32(RTL838X_TBL_ACCESS_L2_CTRL
) & (1 << 16));
1443 static void rtl838x_write_hash(int idx
, u32
*r
)
1445 u32 cmd
= 1 << 16 /* Execute cmd */
1446 | 0 << 15 /* Write */
1447 | 0 << 13 /* Table type 0b00 */
1450 sw_w32(0, RTL838X_TBL_ACCESS_L2_DATA(0));
1451 sw_w32(0, RTL838X_TBL_ACCESS_L2_DATA(1));
1452 sw_w32(0, RTL838X_TBL_ACCESS_L2_DATA(2));
1453 sw_w32(cmd
, RTL838X_TBL_ACCESS_L2_CTRL
);
1454 do { } while (sw_r32(RTL838X_TBL_ACCESS_L2_CTRL
) & (1 << 16));
1457 static void dump_fdb(struct rtl838x_switch_priv
*priv
)
1459 struct rtl838x_l2_entry e
;
1462 mutex_lock(&priv
->reg_mutex
);
1464 for (i
= 0; i
< priv
->fib_entries
; i
++) {
1465 priv
->r
->read_l2_entry_using_hash(i
>> 2, i
& 0x3, &e
);
1467 if (!e
.valid
) /* Check for invalid entry */
1470 pr_info("-> port %02d: mac %pM, vid: %d, rvid: %d, MC: %d, %d\n",
1471 e
.port
, &e
.mac
[0], e
.vid
, e
.rvid
, e
.is_ip_mc
, e
.is_ipv6_mc
);
1474 mutex_unlock(&priv
->reg_mutex
);
1477 static void rtl838x_port_get_stp_state(struct rtl838x_switch_priv
*priv
, int port
)
1483 int n
= priv
->family_id
== RTL8380_FAMILY_ID
? 2 : 4;
1485 /* CPU PORT can only be configured on RTL838x */
1486 if (port
>= priv
->cpu_port
|| port
> 51)
1489 mutex_lock(&priv
->reg_mutex
);
1491 /* For the RTL839x, the bits are left-aligned in the 128 bit field */
1492 if (priv
->family_id
== RTL8390_FAMILY_ID
)
1495 index
= n
- (pos
>> 4) - 1;
1496 bit
= (pos
<< 1) % 32;
1498 if (priv
->family_id
== RTL8380_FAMILY_ID
) {
1499 cmd
= 1 << 15 /* Execute cmd */
1500 | 1 << 14 /* Read */
1501 | 2 << 12 /* Table type 0b10 */
1504 cmd
= 1 << 16 /* Execute cmd */
1505 | 0 << 15 /* Read */
1506 | 5 << 12 /* Table type 0b101 */
1509 priv
->r
->exec_tbl0_cmd(cmd
);
1511 for (i
= 0; i
< n
; i
++)
1512 port_state
[i
] = sw_r32(priv
->r
->tbl_access_data_0(i
));
1514 mutex_unlock(&priv
->reg_mutex
);
1517 static int rtl838x_port_fdb_dump(struct dsa_switch
*ds
, int port
,
1518 dsa_fdb_dump_cb_t
*cb
, void *data
)
1520 struct rtl838x_l2_entry e
;
1521 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1527 mutex_lock(&priv
->reg_mutex
);
1529 for (i
= 0; i
< priv
->fib_entries
; i
++) {
1530 priv
->r
->read_l2_entry_using_hash(i
>> 2, i
& 0x3, &e
);
1535 if (e
.port
== port
) {
1536 fid
= (i
& 0x3ff) | (e
.rvid
& ~0x3ff);
1537 mac
= ether_addr_to_u64(&e
.mac
[0]);
1538 pkey
= rtl838x_hash(priv
, mac
<< 12 | fid
);
1539 fid
= (pkey
& 0x3ff) | (fid
& ~0x3ff);
1540 pr_info("-> mac %016llx, fid: %d\n", mac
, fid
);
1541 cb(e
.mac
, e
.vid
, e
.is_static
, data
);
1545 for (i
= 0; i
< 64; i
++) {
1546 priv
->r
->read_cam(i
, &e
);
1552 cb(e
.mac
, e
.vid
, e
.is_static
, data
);
1555 mutex_unlock(&priv
->reg_mutex
);
1559 static int rtl838x_port_fdb_del(struct dsa_switch
*ds
, int port
,
1560 const unsigned char *addr
, u16 vid
)
1562 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1563 u64 mac
= ether_addr_to_u64(addr
);
1564 u32 key
= rtl838x_hash_key(priv
, mac
, vid
);
1565 struct rtl838x_l2_entry e
;
1568 int idx
= -1, err
= 0, i
;
1570 pr_info("In %s, mac %llx, vid: %d, key: %x\n", __func__
, mac
, vid
, key
);
1571 mutex_lock(&priv
->reg_mutex
);
1572 for (i
= 0; i
< 4; i
++) {
1573 entry
= priv
->r
->read_l2_entry_using_hash(key
, i
, &e
);
1576 if ((entry
& 0x0fffffffffffffffULL
) == ((mac
<< 12) | vid
)) {
1577 idx
= (key
<< 2) | i
;
1583 r
[0] = r
[1] = r
[2] = 0;
1584 rtl838x_write_hash(idx
, r
);
1588 /* Check CAM for spillover from hash buckets */
1589 for (i
= 0; i
< 64; i
++) {
1590 entry
= priv
->r
->read_cam(i
, &e
);
1591 if ((entry
& 0x0fffffffffffffffULL
) == ((mac
<< 12) | vid
)) {
1597 r
[0] = r
[1] = r
[2] = 0;
1598 rtl838x_write_cam(idx
, r
);
1603 mutex_unlock(&priv
->reg_mutex
);
1607 static int rtl838x_port_fdb_add(struct dsa_switch
*ds
, int port
,
1608 const unsigned char *addr
, u16 vid
)
1610 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1611 u64 mac
= ether_addr_to_u64(addr
);
1612 u32 key
= rtl838x_hash_key(priv
, mac
, vid
);
1613 struct rtl838x_l2_entry e
;
1616 int idx
= -1, err
= 0, i
;
1618 mutex_lock(&priv
->reg_mutex
);
1619 for (i
= 0; i
< 4; i
++) {
1620 entry
= priv
->r
->read_l2_entry_using_hash(key
, i
, &e
);
1622 idx
= (key
<< 2) | i
;
1625 if ((entry
& 0x0fffffffffffffffULL
) == ((mac
<< 12) | vid
)) {
1626 idx
= (key
<< 2) | i
;
1631 r
[0] = 3 << 17 | port
<< 12; // Aging and port
1634 r
[2] = (mac
& 0xffff) << 12; /* rvid = 0 */
1635 rtl838x_write_hash(idx
, r
);
1639 /* Hash buckets full, try CAM */
1640 for (i
= 0; i
< 64; i
++) {
1641 entry
= rtl838x_read_cam(i
, &e
);
1643 if (idx
< 0) /* First empty entry? */
1646 } else if ((entry
& 0x0fffffffffffffffULL
) == ((mac
<< 12) | vid
)) {
1647 pr_debug("Found entry in CAM\n");
1653 r
[0] = 3 << 17 | port
<< 12; // Aging
1656 r
[2] = (mac
& 0xffff) << 12; /* rvid = 0 */
1657 rtl838x_write_cam(idx
, r
);
1662 mutex_unlock(&priv
->reg_mutex
);
1666 static void rtl838x_port_stp_state_set(struct dsa_switch
*ds
, int port
,
1673 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1674 int n
= priv
->family_id
== RTL8380_FAMILY_ID
? 2 : 4;
1676 pr_info("%s: port %d state %2x\n", __func__
, port
, state
);
1678 /* CPU PORT can only be configured on RTL838x */
1679 if (port
>= priv
->cpu_port
|| port
> 51)
1682 mutex_lock(&priv
->reg_mutex
);
1684 /* For the RTL839x, the bits are left-aligned in the 128 bit field */
1685 if (priv
->family_id
== RTL8390_FAMILY_ID
)
1688 index
= n
- (pos
>> 4) - 1;
1689 bit
= (pos
<< 1) % 32;
1691 if (priv
->family_id
== RTL8380_FAMILY_ID
) {
1692 cmd
= 1 << 15 /* Execute cmd */
1693 | 1 << 14 /* Read */
1694 | 2 << 12 /* Table type 0b10 */
1697 cmd
= 1 << 16 /* Execute cmd */
1698 | 0 << 15 /* Read */
1699 | 5 << 12 /* Table type 0b101 */
1702 priv
->r
->exec_tbl0_cmd(cmd
);
1704 for (i
= 0; i
< n
; i
++)
1705 port_state
[i
] = sw_r32(priv
->r
->tbl_access_data_0(i
));
1707 pr_debug("Current state, port %d: %d\n", port
, (port_state
[index
] >> bit
) & 3);
1708 port_state
[index
] &= ~(3 << bit
);
1711 case BR_STATE_DISABLED
: /* 0 */
1712 port_state
[index
] |= (0 << bit
);
1714 case BR_STATE_BLOCKING
: /* 4 */
1715 case BR_STATE_LISTENING
: /* 1 */
1716 port_state
[index
] |= (1 << bit
);
1718 case BR_STATE_LEARNING
: /* 2 */
1719 port_state
[index
] |= (2 << bit
);
1721 case BR_STATE_FORWARDING
: /* 3*/
1722 port_state
[index
] |= (3 << bit
);
1727 if (priv
->family_id
== RTL8380_FAMILY_ID
) {
1728 cmd
= 1 << 15 /* Execute cmd */
1729 | 0 << 14 /* Write */
1730 | 2 << 12 /* Table type 0b10 */
1733 cmd
= 1 << 16 /* Execute cmd */
1734 | 1 << 15 /* Write */
1735 | 5 << 12 /* Table type 0b101 */
1738 for (i
= 0; i
< n
; i
++)
1739 sw_w32(port_state
[i
], priv
->r
->tbl_access_data_0(i
));
1740 priv
->r
->exec_tbl0_cmd(cmd
);
1742 mutex_unlock(&priv
->reg_mutex
);
1745 static int rtl838x_port_mirror_add(struct dsa_switch
*ds
, int port
,
1746 struct dsa_mall_mirror_tc_entry
*mirror
,
1749 /* We support 4 mirror groups, one destination port per group */
1751 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1753 pr_info("In %s\n", __func__
);
1755 for (group
= 0; group
< 4; group
++) {
1756 if (priv
->mirror_group_ports
[group
] == mirror
->to_local_port
)
1760 for (group
= 0; group
< 4; group
++) {
1761 if (priv
->mirror_group_ports
[group
] < 0)
1769 pr_debug("Using group %d\n", group
);
1770 mutex_lock(&priv
->reg_mutex
);
1772 if (priv
->family_id
== RTL8380_FAMILY_ID
) {
1773 /* Enable mirroring to port across VLANs (bit 11) */
1774 sw_w32(1 << 11 | (mirror
->to_local_port
<< 4) | 1, RTL838X_MIR_CTRL(group
));
1776 /* Enable mirroring to destination port */
1777 sw_w32((mirror
->to_local_port
<< 4) | 1, RTL839X_MIR_CTRL(group
));
1780 if (ingress
&& (priv
->r
->get_port_reg_be(priv
->r
->mir_spm(group
)) & (1ULL << port
))) {
1781 mutex_unlock(&priv
->reg_mutex
);
1784 if ((!ingress
) && (priv
->r
->get_port_reg_be(priv
->r
->mir_dpm(group
)) & (1ULL << port
))) {
1785 mutex_unlock(&priv
->reg_mutex
);
1790 priv
->r
->mask_port_reg_be(0, 1ULL << port
, priv
->r
->mir_spm(group
));
1792 priv
->r
->mask_port_reg_be(0, 1ULL << port
, priv
->r
->mir_dpm(group
));
1794 priv
->mirror_group_ports
[group
] = mirror
->to_local_port
;
1795 mutex_unlock(&priv
->reg_mutex
);
1799 static void rtl838x_port_mirror_del(struct dsa_switch
*ds
, int port
,
1800 struct dsa_mall_mirror_tc_entry
*mirror
)
1803 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1805 pr_info("In %s\n", __func__
);
1806 for (group
= 0; group
< 4; group
++) {
1807 if (priv
->mirror_group_ports
[group
] == mirror
->to_local_port
)
1813 mutex_lock(&priv
->reg_mutex
);
1814 if (mirror
->ingress
) {
1815 /* Ingress, clear source port matrix */
1816 priv
->r
->mask_port_reg_be(1ULL << port
, 0, priv
->r
->mir_spm(group
));
1818 /* Egress, clear destination port matrix */
1819 priv
->r
->mask_port_reg_be(1ULL << port
, 0, priv
->r
->mir_dpm(group
));
1822 if (!(sw_r32(priv
->r
->mir_spm(group
)) || sw_r32(priv
->r
->mir_dpm(group
)))) {
1823 priv
->mirror_group_ports
[group
] = -1;
1824 sw_w32(0, priv
->r
->mir_ctrl(group
));
1827 mutex_unlock(&priv
->reg_mutex
);
1830 void rtl838x_vlan_profile_dump(int index
)
1834 if (index
< 0 || index
> 7)
1837 profile
= sw_r32(rtl838x_vlan_profile(index
));
1839 pr_info("VLAN %d: L2 learning: %d, L2 Unknown MultiCast Field %x, \
1840 IPv4 Unknown MultiCast Field %x, IPv6 Unknown MultiCast Field: %x",
1841 index
, profile
& 1, (profile
>> 1) & 0x1ff, (profile
>> 10) & 0x1ff,
1842 (profile
>> 19) & 0x1ff);
1845 void rtl839x_vlan_profile_dump(int index
)
1847 u32 profile
, profile1
;
1849 if (index
< 0 || index
> 7)
1852 profile1
= sw_r32(rtl839x_vlan_profile(index
) + 4);
1853 profile
= sw_r32(rtl839x_vlan_profile(index
));
1855 pr_info("VLAN %d: L2 learning: %d, L2 Unknown MultiCast Field %x, \
1856 IPv4 Unknown MultiCast Field %x, IPv6 Unknown MultiCast Field: %x",
1857 index
, profile
& 1, (profile
>> 1) & 0xfff, (profile
>> 13) & 0xfff,
1858 (profile1
) & 0xfff);
1861 static int rtl838x_vlan_filtering(struct dsa_switch
*ds
, int port
,
1862 bool vlan_filtering
)
1864 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1866 pr_info("%s: port %d\n", __func__
, port
);
1867 mutex_lock(&priv
->reg_mutex
);
1869 if (vlan_filtering
) {
1870 /* Enable ingress and egress filtering */
1871 if (port
!= priv
->cpu_port
)
1872 sw_w32_mask(0b10 << ((port
% 16) << 1), 0b01 << ((port
% 16) << 1),
1873 priv
->r
->vlan_port_igr_filter(port
));
1874 sw_w32_mask(0, 1 << (port
% 32), priv
->r
->vlan_port_egr_filter(port
));
1876 /* Disable ingress and egress filtering */
1877 if (port
!= priv
->cpu_port
)
1878 sw_w32_mask(0b11 << ((port
% 16) << 1), 0,
1879 priv
->r
->vlan_port_igr_filter(port
));
1880 sw_w32_mask(1 << (port
% 32), 0, priv
->r
->vlan_port_egr_filter(port
));
1883 /* Do we need to do something to the CPU-Port, too? */
1884 mutex_unlock(&priv
->reg_mutex
);
1889 static int rtl838x_vlan_prepare(struct dsa_switch
*ds
, int port
,
1890 const struct switchdev_obj_port_vlan
*vlan
)
1892 struct rtl838x_vlan_info info
;
1893 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1895 pr_info("%s: port %d\n", __func__
, port
);
1897 mutex_lock(&priv
->reg_mutex
);
1899 if (priv
->family_id
== RTL8380_FAMILY_ID
)
1900 rtl839x_vlan_profile_dump(0);
1902 rtl839x_vlan_profile_dump(0);
1904 priv
->r
->vlan_tables_read(0, &info
);
1906 pr_info("Tagged ports %llx, untag %llx, prof %x, MC# %d, UC# %d, FID %x\n",
1907 info
.tagged_ports
, info
.untagged_ports
, info
.profile_id
,
1908 info
.hash_mc
, info
.hash_uc
, info
.fid
);
1910 mutex_unlock(&priv
->reg_mutex
);
1914 static void rtl838x_vlan_add(struct dsa_switch
*ds
, int port
,
1915 const struct switchdev_obj_port_vlan
*vlan
)
1917 struct rtl838x_vlan_info info
;
1918 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1922 pr_info("%s port %d, vid_end %d, vid_end %d, flags %x\n", __func__
,
1923 port
, vlan
->vid_begin
, vlan
->vid_end
, vlan
->flags
);
1925 if (vlan
->vid_begin
> 4095 || vlan
->vid_end
> 4095) {
1926 dev_err(priv
->dev
, "VLAN out of range: %d - %d",
1927 vlan
->vid_begin
, vlan
->vid_end
);
1931 mutex_lock(&priv
->reg_mutex
);
1933 if (vlan
->flags
& BRIDGE_VLAN_INFO_PVID
) {
1934 for (v
= vlan
->vid_begin
; v
<= vlan
->vid_end
; v
++) {
1935 /* Set both inner and outer PVID of the port */
1936 sw_w32((v
<< 16) | v
, priv
->r
->vlan_port_pb(port
));
1940 if (vlan
->flags
& BRIDGE_VLAN_INFO_UNTAGGED
) {
1941 for (v
= vlan
->vid_begin
; v
<= vlan
->vid_end
; v
++) {
1942 /* Get untagged port memberships of this vlan */
1943 priv
->r
->vlan_tables_read(v
, &info
);
1944 portmask
= info
.untagged_ports
| (1 << port
);
1945 pr_debug("Untagged ports, VLAN %d: %llx\n", v
, portmask
);
1946 priv
->r
->vlan_set_untagged(v
, portmask
);
1949 for (v
= vlan
->vid_begin
; v
<= vlan
->vid_end
; v
++) {
1950 /* Get tagged port memberships of this vlan */
1951 priv
->r
->vlan_tables_read(v
, &info
);
1952 info
.tagged_ports
|= (1 << port
);
1953 pr_debug("Tagged ports, VLAN %d: %llx\n", v
, info
.tagged_ports
);
1954 priv
->r
->vlan_set_tagged(v
, &info
);
1958 mutex_unlock(&priv
->reg_mutex
);
1961 static int rtl838x_vlan_del(struct dsa_switch
*ds
, int port
,
1962 const struct switchdev_obj_port_vlan
*vlan
)
1964 struct rtl838x_vlan_info info
;
1965 struct rtl838x_switch_priv
*priv
= ds
->priv
;
1969 pr_info("%s: port %d, vid_end %d, vid_end %d, flags %x\n", __func__
,
1970 port
, vlan
->vid_begin
, vlan
->vid_end
, vlan
->flags
);
1972 if (vlan
->vid_begin
> 4095 || vlan
->vid_end
> 4095) {
1973 dev_err(priv
->dev
, "VLAN out of range: %d - %d",
1974 vlan
->vid_begin
, vlan
->vid_end
);
1978 mutex_lock(&priv
->reg_mutex
);
1980 for (v
= vlan
->vid_begin
; v
<= vlan
->vid_end
; v
++) {
1981 /* Reset both inner and out PVID of the port */
1982 sw_w32(0, priv
->r
->vlan_port_pb(port
));
1984 if (vlan
->flags
& BRIDGE_VLAN_INFO_UNTAGGED
) {
1985 /* Get untagged port memberships of this vlan */
1986 priv
->r
->vlan_tables_read(v
, &info
);
1987 portmask
= info
.untagged_ports
& (~(1ULL << port
));
1988 pr_info("Untagged ports, VLAN %d: %llx\n", v
, portmask
);
1989 priv
->r
->vlan_set_untagged(v
, portmask
);
1992 /* Get tagged port memberships of this vlan */
1993 priv
->r
->vlan_tables_read(v
, &info
);
1994 info
.tagged_ports
&= (~(1ULL << port
));
1995 pr_info("Tagged ports, VLAN %d: %llx\n", v
, info
.tagged_ports
);
1996 priv
->r
->vlan_set_tagged(v
, &info
);
1998 mutex_unlock(&priv
->reg_mutex
);
2003 static void rtl838x_port_bridge_leave(struct dsa_switch
*ds
, int port
,
2004 struct net_device
*bridge
)
2006 struct rtl838x_switch_priv
*priv
= ds
->priv
;
2007 u64 port_bitmap
= 1ULL << priv
->cpu_port
;
2010 pr_info("%s %x: %d", __func__
, (u32
)priv
, port
);
2011 mutex_lock(&priv
->reg_mutex
);
2012 for (i
= 0; i
< ds
->num_ports
; i
++) {
2013 /* Remove this port from the port matrix of the other ports
2014 * in the same bridge. If the port is disabled, port matrix
2015 * is kept and not being setup until the port becomes enabled.
2016 * And the other port's port matrix cannot be broken when the
2017 * other port is still a VLAN-aware port.
2019 if (dsa_is_user_port(ds
, i
) && i
!= port
) {
2020 if (dsa_to_port(ds
, i
)->bridge_dev
!= bridge
)
2022 if (priv
->ports
[i
].enable
)
2023 priv
->r
->mask_port_reg_be(1ULL << port
, 0,
2024 priv
->r
->port_iso_ctrl(i
));
2025 priv
->ports
[i
].pm
|= 1ULL << port
;
2027 port_bitmap
&= ~(1ULL << i
);
2031 /* Add all other ports to this port matrix. */
2032 if (priv
->ports
[port
].enable
)
2033 priv
->r
->mask_port_reg_be(0, port_bitmap
, priv
->r
->port_iso_ctrl(port
));
2034 priv
->ports
[port
].pm
&= ~port_bitmap
;
2035 mutex_unlock(&priv
->reg_mutex
);
2038 static int rtl838x_port_bridge_join(struct dsa_switch
*ds
, int port
,
2039 struct net_device
*bridge
)
2041 struct rtl838x_switch_priv
*priv
= ds
->priv
;
2042 u64 port_bitmap
= 1ULL << priv
->cpu_port
;
2045 pr_info("%s %x: %d %llx", __func__
, (u32
)priv
, port
, port_bitmap
);
2046 mutex_lock(&priv
->reg_mutex
);
2047 for (i
= 0; i
< ds
->num_ports
; i
++) {
2048 /* Add this port to the port matrix of the other ports in the
2049 * same bridge. If the port is disabled, port matrix is kept
2050 * and not being setup until the port becomes enabled.
2052 if (dsa_is_user_port(ds
, i
) && i
!= port
) {
2053 if (dsa_to_port(ds
, i
)->bridge_dev
!= bridge
)
2055 if (priv
->ports
[i
].enable
)
2056 priv
->r
->mask_port_reg_be(0, 1ULL << port
,
2057 priv
->r
->port_iso_ctrl(i
));
2058 priv
->ports
[i
].pm
|= 1ULL << port
;
2060 port_bitmap
|= 1ULL << i
;
2064 /* Add all other ports to this port matrix. */
2065 if (priv
->ports
[port
].enable
) {
2066 priv
->r
->mask_port_reg_be(0, 1ULL << port
,
2067 priv
->r
->port_iso_ctrl(priv
->cpu_port
));
2068 priv
->r
->mask_port_reg_be(0, port_bitmap
,
2069 priv
->r
->port_iso_ctrl(port
));
2071 priv
->ports
[port
].pm
|= port_bitmap
;
2072 mutex_unlock(&priv
->reg_mutex
);
2077 static int rtl838x_port_enable(struct dsa_switch
*ds
, int port
,
2078 struct phy_device
*phydev
)
2080 struct rtl838x_switch_priv
*priv
= ds
->priv
;
2082 pr_info("%s: %x %d", __func__
, (u32
) priv
, port
);
2083 priv
->ports
[port
].enable
= true;
2085 if (dsa_is_cpu_port(ds
, port
))
2088 /* add port to switch mask of CPU_PORT */
2089 priv
->r
->mask_port_reg_be(0, 1ULL << port
, priv
->r
->port_iso_ctrl(priv
->cpu_port
));
2091 /* add all other ports in the same bridge to switch mask of port */
2092 priv
->r
->mask_port_reg_be(0, priv
->ports
[port
].pm
, priv
->r
->port_iso_ctrl(port
));
2097 static void rtl838x_port_disable(struct dsa_switch
*ds
, int port
)
2099 struct rtl838x_switch_priv
*priv
= ds
->priv
;
2101 pr_info("%s %x: %d", __func__
, (u32
)priv
, port
);
2102 /* you can only disable user ports */
2103 if (!dsa_is_user_port(ds
, port
))
2106 /* remove port from switch mask of CPU_PORT */
2107 priv
->r
->mask_port_reg_be(1ULL << port
, 0, priv
->r
->port_iso_ctrl(priv
->cpu_port
));
2109 /* remove all other ports in the same bridge from switch mask of port */
2110 priv
->r
->mask_port_reg_be(priv
->ports
[port
].pm
, 0LL, priv
->r
->port_iso_ctrl(port
));
2112 priv
->ports
[port
].enable
= false;
2115 static int rtl838x_get_mac_eee(struct dsa_switch
*ds
, int port
,
2116 struct ethtool_eee
*e
)
2118 struct rtl838x_switch_priv
*priv
= ds
->priv
;
2120 pr_info("%s: port %d", __func__
, port
);
2121 e
->supported
= SUPPORTED_100baseT_Full
| SUPPORTED_1000baseT_Full
;
2122 if (sw_r32(priv
->r
->mac_force_mode_ctrl(port
)) & (1 << 9))
2123 e
->advertised
|= ADVERTISED_100baseT_Full
;
2125 if (sw_r32(priv
->r
->mac_force_mode_ctrl(port
)) & (1 << 10))
2126 e
->advertised
|= ADVERTISED_1000baseT_Full
;
2128 e
->eee_enabled
= priv
->ports
[port
].eee_enabled
;
2129 pr_info("enabled: %d, active %x\n", e
->eee_enabled
, e
->advertised
);
2131 if (sw_r32(RTL838X_MAC_EEE_ABLTY
) & (1 << port
)) {
2132 e
->lp_advertised
= ADVERTISED_100baseT_Full
;
2133 e
->lp_advertised
|= ADVERTISED_1000baseT_Full
;
2136 e
->eee_active
= !!(e
->advertised
& e
->lp_advertised
);
2137 pr_info("active: %d, lp %x\n", e
->eee_active
, e
->lp_advertised
);
2142 static int rtl838x_set_mac_eee(struct dsa_switch
*ds
, int port
,
2143 struct ethtool_eee
*e
)
2145 struct rtl838x_switch_priv
*priv
= ds
->priv
;
2147 pr_info("%s: port %d", __func__
, port
);
2148 if (e
->eee_enabled
) {
2149 pr_info("Globally enabling EEE\n");
2150 sw_w32_mask(0x4, 0, RTL838X_SMI_GLB_CTRL
);
2152 if (e
->eee_enabled
) {
2153 pr_info("Enabling EEE for MAC %d\n", port
);
2154 sw_w32_mask(0, 3 << 9, priv
->r
->mac_force_mode_ctrl(port
));
2155 sw_w32_mask(0, 1 << port
, RTL838X_EEE_PORT_TX_EN
);
2156 sw_w32_mask(0, 1 << port
, RTL838X_EEE_PORT_RX_EN
);
2157 priv
->ports
[port
].eee_enabled
= true;
2158 e
->eee_enabled
= true;
2160 pr_info("Disabling EEE for MAC %d\n", port
);
2161 sw_w32_mask(3 << 9, 0, priv
->r
->mac_force_mode_ctrl(port
));
2162 sw_w32_mask(1 << port
, 0, RTL838X_EEE_PORT_TX_EN
);
2163 sw_w32_mask(1 << port
, 0, RTL838X_EEE_PORT_RX_EN
);
2164 priv
->ports
[port
].eee_enabled
= false;
2165 e
->eee_enabled
= false;
2170 static void rtl838x_phylink_mac_config(struct dsa_switch
*ds
, int port
,
2172 const struct phylink_link_state
*state
)
2174 struct rtl838x_switch_priv
*priv
= ds
->priv
;
2176 int speed_bit
= priv
->family_id
== RTL8380_FAMILY_ID
? 4 : 3;
2178 pr_info("%s port %d, mode %x\n", __func__
, port
, mode
);
2180 if (port
== priv
->cpu_port
) {
2181 /* Set Speed, duplex, flow control
2182 * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL
2183 * | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN
2186 if (priv
->family_id
== RTL8380_FAMILY_ID
) {
2187 sw_w32(0x6192F, priv
->r
->mac_force_mode_ctrl(priv
->cpu_port
));
2188 /* allow CRC errors on CPU-port */
2189 sw_w32_mask(0, 0x8, RTL838X_MAC_PORT_CTRL(priv
->cpu_port
));
2191 sw_w32_mask(0, 3, priv
->r
->mac_force_mode_ctrl(priv
->cpu_port
));
2196 reg
= sw_r32(priv
->r
->mac_force_mode_ctrl(port
));
2197 /* Auto-Negotiation does not work for MAC in RTL8390 */
2198 if (priv
->family_id
== RTL8380_FAMILY_ID
) {
2199 if (mode
== MLO_AN_PHY
) {
2200 pr_info("PHY autonegotiates\n");
2202 sw_w32(reg
, priv
->r
->mac_force_mode_ctrl(port
));
2207 if (mode
!= MLO_AN_FIXED
)
2208 pr_info("Fixed state.\n");
2210 if (priv
->family_id
== RTL8380_FAMILY_ID
) {
2211 /* Clear id_mode_dis bit, and the existing port mode, let
2212 * RGMII_MODE_EN bet set by mac_link_{up,down}
2214 reg
&= ~(RX_PAUSE_EN
| TX_PAUSE_EN
);
2216 if (state
->pause
& MLO_PAUSE_TXRX_MASK
) {
2217 if (state
->pause
& MLO_PAUSE_TX
)
2223 reg
&= ~(3 << speed_bit
);
2224 switch (state
->speed
) {
2226 reg
|= 2 << speed_bit
;
2229 reg
|= 1 << speed_bit
;
2233 if (priv
->family_id
== RTL8380_FAMILY_ID
) {
2234 reg
&= ~(DUPLEX_FULL
| FORCE_LINK_EN
);
2236 reg
|= FORCE_LINK_EN
;
2237 if (state
->duplex
== DUPLEX_FULL
)
2242 if (priv
->family_id
== RTL8380_FAMILY_ID
)
2244 sw_w32(reg
, priv
->r
->mac_force_mode_ctrl(port
));
2247 static void rtl838x_phylink_mac_link_down(struct dsa_switch
*ds
, int port
,
2249 phy_interface_t interface
)
2251 struct rtl838x_switch_priv
*priv
= ds
->priv
;
2252 /* Stop TX/RX to port */
2253 sw_w32_mask(0x3, 0, priv
->r
->mac_port_ctrl(port
));
2256 static void rtl838x_phylink_mac_link_up(struct dsa_switch
*ds
, int port
,
2258 phy_interface_t interface
,
2259 struct phy_device
*phydev
)
2261 struct rtl838x_switch_priv
*priv
= ds
->priv
;
2262 /* Restart TX/RX to port */
2263 sw_w32_mask(0, 0x3, priv
->r
->mac_port_ctrl(port
));
2266 static void rtl838x_phylink_validate(struct dsa_switch
*ds
, int port
,
2267 unsigned long *supported
,
2268 struct phylink_link_state
*state
)
2270 struct rtl838x_switch_priv
*priv
= ds
->priv
;
2271 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask
) = { 0, };
2273 pr_info("In %s port %d", __func__
, port
);
2275 if (!phy_interface_mode_is_rgmii(state
->interface
) &&
2276 state
->interface
!= PHY_INTERFACE_MODE_1000BASEX
&&
2277 state
->interface
!= PHY_INTERFACE_MODE_MII
&&
2278 state
->interface
!= PHY_INTERFACE_MODE_REVMII
&&
2279 state
->interface
!= PHY_INTERFACE_MODE_GMII
&&
2280 state
->interface
!= PHY_INTERFACE_MODE_QSGMII
&&
2281 state
->interface
!= PHY_INTERFACE_MODE_INTERNAL
&&
2282 state
->interface
!= PHY_INTERFACE_MODE_SGMII
) {
2283 bitmap_zero(supported
, __ETHTOOL_LINK_MODE_MASK_NBITS
);
2285 "Unsupported interface: %d for port %d\n",
2286 state
->interface
, port
);
2290 /* Allow all the expected bits */
2291 phylink_set(mask
, Autoneg
);
2292 phylink_set_port_modes(mask
);
2293 phylink_set(mask
, Pause
);
2294 phylink_set(mask
, Asym_Pause
);
2296 /* With the exclusion of MII and Reverse MII, we support Gigabit,
2297 * including Half duplex
2299 if (state
->interface
!= PHY_INTERFACE_MODE_MII
&&
2300 state
->interface
!= PHY_INTERFACE_MODE_REVMII
) {
2301 phylink_set(mask
, 1000baseT_Full
);
2302 phylink_set(mask
, 1000baseT_Half
);
2305 /* On both the 8380 and 8382, ports 24-27 are SFP ports */
2306 if (port
>= 24 && port
<= 27 && priv
->family_id
== RTL8380_FAMILY_ID
)
2307 phylink_set(mask
, 1000baseX_Full
);
2309 phylink_set(mask
, 10baseT_Half
);
2310 phylink_set(mask
, 10baseT_Full
);
2311 phylink_set(mask
, 100baseT_Half
);
2312 phylink_set(mask
, 100baseT_Full
);
2314 bitmap_and(supported
, supported
, mask
,
2315 __ETHTOOL_LINK_MODE_MASK_NBITS
);
2316 bitmap_and(state
->advertising
, state
->advertising
, mask
,
2317 __ETHTOOL_LINK_MODE_MASK_NBITS
);
2320 static int rtl838x_phylink_mac_link_state(struct dsa_switch
*ds
, int port
,
2321 struct phylink_link_state
*state
)
2323 struct rtl838x_switch_priv
*priv
= ds
->priv
;
2326 if (port
< 0 || port
> priv
->cpu_port
)
2330 if (priv
->r
->get_port_reg_le(priv
->r
->mac_link_sts
) & (1ULL << port
))
2333 if (priv
->r
->get_port_reg_le(priv
->r
->mac_link_dup_sts
) & (1ULL << port
))
2336 speed
= priv
->r
->get_port_reg_le(priv
->r
->mac_link_spd_sts(port
));
2337 speed
>>= (port
% 16) << 1;
2338 switch (speed
& 0x3) {
2340 state
->speed
= SPEED_10
;
2343 state
->speed
= SPEED_100
;
2346 state
->speed
= SPEED_1000
;
2349 if (port
== 24 || port
== 26) /* Internal serdes */
2350 state
->speed
= SPEED_2500
;
2352 state
->speed
= SPEED_100
; /* Is in fact 500Mbit */
2355 state
->pause
&= (MLO_PAUSE_RX
| MLO_PAUSE_TX
);
2356 if (priv
->r
->get_port_reg_le(priv
->r
->mac_rx_pause_sts
) & (1ULL << port
))
2357 state
->pause
|= MLO_PAUSE_RX
;
2358 if (priv
->r
->get_port_reg_le(priv
->r
->mac_tx_pause_sts
) & (1ULL << port
))
2359 state
->pause
|= MLO_PAUSE_TX
;
2363 static int rtl838x_mdio_probe(struct rtl838x_switch_priv
*priv
)
2365 struct device
*dev
= priv
->dev
;
2366 struct device_node
*dn
, *mii_np
= dev
->of_node
;
2367 struct mii_bus
*bus
;
2371 pr_info("In %s\n", __func__
);
2372 mii_np
= of_find_compatible_node(NULL
, NULL
, "realtek,rtl838x-mdio");
2374 pr_info("Found compatible MDIO node!\n");
2376 dev_err(priv
->dev
, "no %s child node found", "mdio-bus");
2380 priv
->mii_bus
= of_mdio_find_bus(mii_np
);
2381 if (!priv
->mii_bus
) {
2382 pr_info("Deferring probe of mdio bus\n");
2383 return -EPROBE_DEFER
;
2385 if (!of_device_is_available(mii_np
))
2388 bus
= devm_mdiobus_alloc(priv
->ds
->dev
);
2392 bus
->name
= "rtl838x slave mii";
2393 bus
->read
= &rtl838x_mdio_read
;
2394 bus
->write
= &rtl838x_mdio_write
;
2395 snprintf(bus
->id
, MII_BUS_ID_SIZE
, "%s-%d", bus
->name
, dev
->id
);
2397 priv
->ds
->slave_mii_bus
= bus
;
2398 priv
->ds
->slave_mii_bus
->priv
= priv
;
2400 ret
= mdiobus_register(priv
->ds
->slave_mii_bus
);
2401 if (ret
&& mii_np
) {
2407 for_each_node_by_name(dn
, "ethernet-phy") {
2408 if (of_property_read_u32(dn
, "reg", &pn
))
2411 // Check for the integrated SerDes of the RTL8380M first
2412 if (of_property_read_bool(dn
, "phy-is-integrated")
2413 && priv
->id
== 0x8380 && pn
>= 24) {
2414 pr_info("----> FÓUND A SERDES\n");
2415 priv
->ports
[pn
].phy
= PHY_RTL838X_SDS
;
2419 if (of_property_read_bool(dn
, "phy-is-integrated")
2420 && !of_property_read_bool(dn
, "sfp")) {
2421 priv
->ports
[pn
].phy
= PHY_RTL8218B_INT
;
2425 if (!of_property_read_bool(dn
, "phy-is-integrated")
2426 && of_property_read_bool(dn
, "sfp")) {
2427 priv
->ports
[pn
].phy
= PHY_RTL8214FC
;
2431 if (!of_property_read_bool(dn
, "phy-is-integrated")
2432 && !of_property_read_bool(dn
, "sfp")) {
2433 priv
->ports
[pn
].phy
= PHY_RTL8218B_EXT
;
2438 /* Disable MAC polling the PHY so that we can start configuration */
2439 priv
->r
->set_port_reg_le(0ULL, priv
->r
->smi_poll_ctrl
);
2441 /* Enable PHY control via SoC */
2442 if (priv
->family_id
== RTL8380_FAMILY_ID
) {
2443 /* Enable PHY control via SoC */
2444 sw_w32_mask(0, 1 << 15, RTL838X_SMI_GLB_CTRL
);
2446 /* Disable PHY polling via SoC */
2447 sw_w32_mask(1 << 7, 0, RTL839X_SMI_GLB_CTRL
);
2450 /* Power on fibre ports and reset them if necessary */
2451 if (priv
->ports
[24].phy
== PHY_RTL838X_SDS
) {
2452 pr_info("Powering on fibre ports & reset\n");
2453 rtl8380_sds_power(24, 1);
2454 rtl8380_sds_power(26, 1);
2457 pr_info("%s done\n", __func__
);
2461 static const struct dsa_switch_ops rtl838x_switch_ops
= {
2462 .get_tag_protocol
= rtl838x_get_tag_protocol
,
2463 .setup
= rtl838x_setup
,
2464 .port_vlan_filtering
= rtl838x_vlan_filtering
,
2465 .port_vlan_prepare
= rtl838x_vlan_prepare
,
2466 .port_vlan_add
= rtl838x_vlan_add
,
2467 .port_vlan_del
= rtl838x_vlan_del
,
2468 .port_bridge_join
= rtl838x_port_bridge_join
,
2469 .port_bridge_leave
= rtl838x_port_bridge_leave
,
2470 .port_stp_state_set
= rtl838x_port_stp_state_set
,
2471 .set_ageing_time
= rtl838x_set_l2aging
,
2472 .port_fast_age
= rtl838x_fast_age
,
2473 .port_fdb_add
= rtl838x_port_fdb_add
,
2474 .port_fdb_del
= rtl838x_port_fdb_del
,
2475 .port_fdb_dump
= rtl838x_port_fdb_dump
,
2476 .port_enable
= rtl838x_port_enable
,
2477 .port_disable
= rtl838x_port_disable
,
2478 .port_mirror_add
= rtl838x_port_mirror_add
,
2479 .port_mirror_del
= rtl838x_port_mirror_del
,
2480 .phy_read
= dsa_phy_read
,
2481 .phy_write
= dsa_phy_write
,
2482 .get_strings
= rtl838x_get_strings
,
2483 .get_ethtool_stats
= rtl838x_get_ethtool_stats
,
2484 .get_sset_count
= rtl838x_get_sset_count
,
2485 .phylink_validate
= rtl838x_phylink_validate
,
2486 .phylink_mac_link_state
= rtl838x_phylink_mac_link_state
,
2487 .phylink_mac_config
= rtl838x_phylink_mac_config
,
2488 .phylink_mac_link_down
= rtl838x_phylink_mac_link_down
,
2489 .phylink_mac_link_up
= rtl838x_phylink_mac_link_up
,
2490 .set_mac_eee
= rtl838x_set_mac_eee
,
2491 .get_mac_eee
= rtl838x_get_mac_eee
,
2494 static int __init
rtl838x_sw_probe(struct platform_device
*pdev
)
2497 struct rtl838x_switch_priv
*priv
;
2498 struct device
*dev
= &pdev
->dev
;
2501 pr_info("Probing RTL838X switch device\n");
2502 if (!pdev
->dev
.of_node
) {
2503 dev_err(dev
, "No DT found\n");
2507 priv
= devm_kzalloc(dev
, sizeof(*priv
), GFP_KERNEL
);
2511 priv
->ds
= dsa_switch_alloc(dev
, DSA_MAX_PORTS
);
2515 priv
->ds
->dev
= dev
;
2516 priv
->ds
->priv
= priv
;
2517 priv
->ds
->ops
= &rtl838x_switch_ops
;
2520 priv
->family_id
= soc_info
.family
;
2521 priv
->id
= soc_info
.id
;
2522 if (soc_info
.family
== RTL8380_FAMILY_ID
) {
2523 priv
->cpu_port
= RTL838X_CPU_PORT
;
2524 priv
->port_mask
= 0x1f;
2525 priv
->r
= &rtl838x_reg
;
2526 priv
->ds
->num_ports
= 30;
2527 priv
->fib_entries
= 8192;
2528 rtl8380_get_version(priv
);
2530 priv
->cpu_port
= RTL839X_CPU_PORT
;
2531 priv
->port_mask
= 0x3f;
2532 priv
->r
= &rtl839x_reg
;
2533 priv
->ds
->num_ports
= 53;
2534 priv
->fib_entries
= 16384;
2535 rtl8390_get_version(priv
);
2537 pr_info("Chip version %c\n", priv
->version
);
2539 err
= rtl838x_mdio_probe(priv
);
2541 /* Probing fails the 1st time because of missing ethernet driver
2542 * initialization. Use this to disable traffic in case the bootloader left if on
2546 err
= dsa_register_switch(priv
->ds
);
2548 dev_err(dev
, "Error registering switch: %d\n", err
);
2552 /* Enable link and media change interrupts. Are the SERDES masks needed? */
2553 sw_w32_mask(0, 3, priv
->r
->isr_glb_src
);
2554 /* ... for all ports */
2555 irq_mask
= soc_info
.family
== RTL8380_FAMILY_ID
? 0x0FFFFFFF : 0xFFFFFFFFFFFFFULL
;
2556 priv
->r
->set_port_reg_le(irq_mask
, priv
->r
->isr_port_link_sts_chg
);
2557 priv
->r
->set_port_reg_le(irq_mask
, priv
->r
->imr_port_link_sts_chg
);
2559 priv
->link_state_irq
= 20;
2560 if (priv
->family_id
== RTL8380_FAMILY_ID
) {
2561 err
= request_irq(priv
->link_state_irq
, rtl838x_switch_irq
,
2562 IRQF_SHARED
, "rtl838x-link-state", priv
->ds
);
2564 err
= request_irq(priv
->link_state_irq
, rtl839x_switch_irq
,
2565 IRQF_SHARED
, "rtl838x-link-state", priv
->ds
);
2568 dev_err(dev
, "Error setting up switch interrupt.\n");
2569 /* Need to free allocated switch here */
2572 /* Enable interrupts for switch */
2573 sw_w32(0x1, priv
->r
->imr_glb
);
2575 rtl838x_get_l2aging(priv
);
2577 /* Clear all destination ports for mirror groups */
2578 for (i
= 0; i
< 4; i
++)
2579 priv
->mirror_group_ports
[i
] = -1;
2584 static int rtl838x_sw_remove(struct platform_device
*pdev
)
2586 pr_info("Removing platform driver for rtl838x-sw\n");
2590 static const struct of_device_id rtl838x_switch_of_ids
[] = {
2591 { .compatible
= "realtek,rtl838x-switch"},
2596 MODULE_DEVICE_TABLE(of
, rtl838x_switch_of_ids
);
2598 static struct platform_driver rtl838x_switch_driver
= {
2599 .probe
= rtl838x_sw_probe
,
2600 .remove
= rtl838x_sw_remove
,
2602 .name
= "rtl838x-switch",
2604 .of_match_table
= rtl838x_switch_of_ids
,
2608 module_platform_driver(rtl838x_switch_driver
);
2610 MODULE_AUTHOR("B. Koblitz");
2611 MODULE_DESCRIPTION("RTL838X SoC Switch Driver");
2612 MODULE_LICENSE("GPL");