target/linux/rtl838x/files-5.4/drivers/net/ethernet/rtl838x_eth.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #ifndef _RTL838X_ETH_H
   4 #define _RTL838X_ETH_H
   5
   6 /*
   7  * Register definition
   8  */
   9
  10 #define RTL838X_CPU_PORT                        28
  11 #define RTL839X_CPU_PORT                        52
  12
  13 #define RTL838X_MAC_PORT_CTRL                   (0xd560)
  14 #define RTL839X_MAC_PORT_CTRL                   (0x8004)
  15 #define RTL838X_DMA_IF_INTR_STS                 (0x9f54)
  16 #define RTL839X_DMA_IF_INTR_STS                 (0x7868)
  17 #define RTL838X_DMA_IF_INTR_MSK                 (0x9f50)
  18 #define RTL839X_DMA_IF_INTR_MSK                 (0x7864)
  19 #define RTL838X_DMA_IF_CTRL                     (0x9f58)
  20 #define RTL839X_DMA_IF_CTRL                     (0x786c)
  21 #define RTL838X_RST_GLB_CTRL_0                  (0x003c)
  22 #define RTL838X_MAC_FORCE_MODE_CTRL             (0xa104)
  23 #define RTL839X_MAC_FORCE_MODE_CTRL             (0x02bc)
  24
  25 /* MAC address settings */
  26 #define RTL838X_MAC                             (0xa9ec)
  27 #define RTL839X_MAC                             (0x02b4)
  28 #define RTL838X_MAC_ALE                         (0x6b04)
  29 #define RTL838X_MAC2                            (0xa320)
  30
  31 #define RTL838X_DMA_RX_BASE                     (0x9f00)
  32 #define RTL839X_DMA_RX_BASE                     (0x780c)
  33 #define RTL838X_DMA_TX_BASE                     (0x9f40)
  34 #define RTL839X_DMA_TX_BASE                     (0x784c)
  35 #define RTL838X_DMA_IF_RX_RING_SIZE             (0xB7E4)
  36 #define RTL839X_DMA_IF_RX_RING_SIZE             (0x6038)
  37 #define RTL838X_DMA_IF_RX_RING_CNTR             (0xB7E8)
  38 #define RTL839X_DMA_IF_RX_RING_CNTR             (0x603c)
  39 #define RTL838X_DMA_IF_RX_CUR                   (0x9F20)
  40 #define RTL839X_DMA_IF_RX_CUR                   (0x782c)
  41
  42 #define RTL838X_DMY_REG31                       (0x3b28)
  43 #define RTL838X_SDS_MODE_SEL                    (0x0028)
  44 #define RTL838X_SDS_CFG_REG                     (0x0034)
  45 #define RTL838X_INT_MODE_CTRL                   (0x005c)
  46 #define RTL838X_CHIP_INFO                       (0x00d8)
  47 #define RTL838X_SDS4_REG28                      (0xef80)
  48 #define RTL838X_SDS4_DUMMY0                     (0xef8c)
  49 #define RTL838X_SDS5_EXT_REG6                   (0xf18c)
  50 #define RTL838X_PORT_ISO_CTRL(port)             (0x4100 + ((port) << 2))
  51 #define RTL838X_STAT_PORT_STD_MIB(port)         (0x1200 + (((port) << 8)))
  52 #define RTL838X_STAT_RST                        (0x3100)
  53 #define RTL838X_STAT_CTRL                       (0x3108)
  54
  55 /* Registers of the internal Serdes of the 8380 */
  56 #define MAPLE_SDS4_REG0r                        RTL838X_SDS4_REG28
  57 #define MAPLE_SDS5_REG0r                        (RTL838X_SDS4_REG28 + 0x100)
  58 #define MAPLE_SDS4_REG3r                        RTL838X_SDS4_DUMMY0
  59 #define MAPLE_SDS5_REG3r                        (RTL838X_SDS4_REG28 + 0x100)
  60 #define MAPLE_SDS4_FIB_REG0r                    (RTL838X_SDS4_REG28 + 0x880)
  61 #define MAPLE_SDS5_FIB_REG0r                    (RTL838X_SDS4_REG28 + 0x980)
  62
  63 /* VLAN registers */
  64 #define RTL838X_VLAN_PROFILE(idx)               (0x3A88 + ((idx) << 2))
  65 #define RTL838X_VLAN_PORT_EGR_FLTR              (0x3A84)
  66 #define RTL838X_VLAN_PORT_PB_VLAN(port)         (0x3C00 + ((port) << 2))
  67 #define RTL838X_VLAN_PORT_IGR_FLTR_0            (0x3A7C)
  68 #define RTL838X_VLAN_PORT_IGR_FLTR_1            (0x3A7C + 4)
  69 #define RTL838X_TBL_ACCESS_CTRL_0               (0x6914)
  70 #define RTL838X_TBL_ACCESS_DATA_0(idx)          (0x6918 + ((idx) << 2))
  71 #define RTL838X_TBL_ACCESS_CTRL_1               (0xA4C8)
  72 #define RTL838X_TBL_ACCESS_DATA_1(idx)          (0xA4CC + ((idx) << 2))
  73 #define RTL839X_TBL_ACCESS_L2_CTRL              (0x1180)
  74 #define RTL839X_TBL_ACCESS_L2_DATA(idx)         (0x1184 + ((idx) << 2))
  75 /* MAC handling */
  76 #define RTL838X_MAC_LINK_STS                    (0xa188)
  77 #define RTL839X_MAC_LINK_STS                    (0x0390)
  78 #define RTL838X_MAC_LINK_SPD_STS                (0xa190)
  79 #define RTL839X_MAC_LINK_SPD_STS                (0x03a0)
  80 #define RTL838X_MAC_LINK_DUP_STS                (0xa19c)
  81 #define RTL839X_MAC_LINK_DUP_STS                (0x03b0)
  82 // TODO: RTL8390_MAC_LINK_MEDIA_STS_ADDR ???
  83 #define RTL838X_MAC_TX_PAUSE_STS                (0xa1a0)
  84 #define RTL839X_MAC_TX_PAUSE_STS                (0x03b8)
  85 #define RTL838X_MAC_RX_PAUSE_STS                (0xa1a4)
  86 #define RTL839X_MAC_RX_PAUSE_STS                (0x03c0)
  87 #define RTL838X_EEE_TX_TIMER_GIGA_CTRL          (0xaa04)
  88 #define RTL838X_EEE_TX_TIMER_GELITE_CTRL        (0xaa08)
  89 #define RTL839X_MAC_GLB_CTRL                    (0x02a8)
  90 #define RTL839X_SCHED_LB_TICK_TKN_CTRL          (0x60f8)
  91
  92 #define RTL838X_L2_TBL_FLUSH_CTRL               (0x3370)
  93 #define RTL839X_L2_TBL_FLUSH_CTRL               (0x3ba0)
  94
  95 /* MAC link state bits */
  96 #define FORCE_EN                                (1 << 0)
  97 #define FORCE_LINK_EN                           (1 << 1)
  98 #define NWAY_EN                                 (1 << 2)
  99 #define DUPLX_MODE                              (1 << 3)
 100 #define TX_PAUSE_EN                             (1 << 6)
 101 #define RX_PAUSE_EN                             (1 << 7)
 102
 103 inline int rtl838x_mac_port_ctrl(int p)
 104 {
 105         return RTL838X_MAC_PORT_CTRL + (p << 7);
 106 }
 107
 108 inline int rtl839x_mac_port_ctrl(int p)
 109 {
 110         return RTL839X_MAC_PORT_CTRL + (p << 7);
 111 }
 112
 113 static inline int rtl838x_mac_force_mode_ctrl(int p)
 114 {
 115         return RTL838X_MAC_FORCE_MODE_CTRL + (p << 2);
 116 }
 117
 118 static inline int rtl839x_mac_force_mode_ctrl(int p)
 119 {
 120         return RTL839X_MAC_FORCE_MODE_CTRL + (p << 2);
 121 }
 122
 123 inline int rtl838x_dma_rx_base(int i)
 124 {
 125         return RTL838X_DMA_RX_BASE + (i << 2);
 126 }
 127
 128 inline int rtl839x_dma_rx_base(int i)
 129 {
 130         return RTL839X_DMA_RX_BASE + (i << 2);
 131 }
 132
 133 inline int rtl838x_dma_tx_base(int i)
 134 {
 135         return RTL838X_DMA_TX_BASE + (i << 2);
 136 }
 137
 138 inline int rtl839x_dma_tx_base(int i)
 139 {
 140         return RTL839X_DMA_TX_BASE + (i << 2);
 141 }
 142
 143 inline int rtl838x_dma_if_rx_ring_size(int i)
 144 {
 145         return RTL838X_DMA_IF_RX_RING_SIZE + ((i >> 3) << 2);
 146 }
 147
 148 inline int rtl839x_dma_if_rx_ring_size(int i)
 149 {
 150         return RTL839X_DMA_IF_RX_RING_SIZE + ((i >> 3) << 2);
 151 }
 152
 153 inline int rtl838x_dma_if_rx_ring_cntr(int i)
 154 {
 155         return RTL838X_DMA_IF_RX_RING_CNTR + ((i >> 3) << 2);
 156 }
 157
 158 inline int rtl839x_dma_if_rx_ring_cntr(int i)
 159 {
 160         return RTL839X_DMA_IF_RX_RING_CNTR + ((i >> 3) << 2);
 161 }
 162
 163
 164 inline int rtl838x_dma_if_rx_cur(int i)
 165 {
 166         return RTL838X_DMA_IF_RX_CUR + (i << 2);
 167 }
 168
 169 inline int rtl839x_dma_if_rx_cur(int i)
 170 {
 171         return RTL839X_DMA_IF_RX_CUR + (i << 2);
 172 }
 173
 174 inline u32 rtl838x_get_mac_link_sts(int port)
 175 {
 176         return (sw_r32(RTL838X_MAC_LINK_STS) & (1 << port));
 177 }
 178
 179 inline u32 rtl839x_get_mac_link_sts(int p)
 180 {
 181         return (sw_r32(RTL839X_MAC_LINK_STS + ((p >> 5) << 2)) & (1 << p));
 182 }
 183
 184 inline u32 rtl838x_get_mac_link_dup_sts(int port)
 185 {
 186         return (sw_r32(RTL838X_MAC_LINK_DUP_STS) & (1 << port));
 187 }
 188
 189 inline u32 rtl839x_get_mac_link_dup_sts(int p)
 190 {
 191         return (sw_r32(RTL839X_MAC_LINK_DUP_STS + ((p >> 5) << 2)) & (1 << p));
 192 }
 193
 194 inline u32 rtl838x_get_mac_link_spd_sts(int port)
 195 {
 196         int r = RTL838X_MAC_LINK_SPD_STS + ((port >> 4) << 2);
 197         u32 speed = sw_r32(r);
 198
 199         speed >>= (port % 16) << 1;
 200         return (speed & 0x3);
 201 }
 202
 203 inline u32 rtl839x_get_mac_link_spd_sts(int port)
 204 {
 205         int r = RTL839X_MAC_LINK_SPD_STS + ((port >> 4) << 2);
 206         u32 speed = sw_r32(r);
 207
 208         speed >>= (port % 16) << 1;
 209         return (speed & 0x3);
 210 }
 211
 212 inline u32 rtl838x_get_mac_rx_pause_sts(int port)
 213 {
 214         return (sw_r32(RTL838X_MAC_RX_PAUSE_STS) & (1 << port));
 215 }
 216
 217 inline u32 rtl839x_get_mac_rx_pause_sts(int p)
 218 {
 219         return (sw_r32(RTL839X_MAC_RX_PAUSE_STS + ((p >> 5) << 2)) & (1 << p));
 220 }
 221
 222 inline u32 rtl838x_get_mac_tx_pause_sts(int port)
 223 {
 224         return (sw_r32(RTL838X_MAC_TX_PAUSE_STS) & (1 << port));
 225 }
 226
 227 inline u32 rtl839x_get_mac_tx_pause_sts(int p)
 228 {
 229         return (sw_r32(RTL839X_MAC_TX_PAUSE_STS + ((p >> 5) << 2)) & (1 << p));
 230 }
 231
 232
 233 struct rtl838x_reg {
 234         int (*mac_port_ctrl)(int port);
 235         int dma_if_intr_sts;
 236         int dma_if_intr_msk;
 237         int dma_if_ctrl;
 238         int  (*mac_force_mode_ctrl)(int port);
 239         int  (*dma_rx_base)(int ring);
 240         int  (*dma_tx_base)(int ring);
 241         int  (*dma_if_rx_ring_size)(int ring);
 242         int  (*dma_if_rx_ring_cntr)(int ring);
 243         int  (*dma_if_rx_cur)(int ring);
 244         int rst_glb_ctrl;
 245         u32 (*get_mac_link_sts)(int port);
 246         u32 (*get_mac_link_dup_sts)(int port);
 247         u32 (*get_mac_link_spd_sts)(int port);
 248         u32 (*get_mac_rx_pause_sts)(int port);
 249         u32 (*get_mac_tx_pause_sts)(int port);
 250         int mac;
 251         int l2_tbl_flush_ctrl;
 252 };
 253
 254 int rtl838x_write_phy(u32 port, u32 page, u32 reg, u32 val);
 255 int rtl838x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
 256 int rtl839x_write_phy(u32 port, u32 page, u32 reg, u32 val);
 257 int rtl839x_read_phy(u32 port, u32 page, u32 reg, u32 *val);
 258
 259 extern int rtl8380_sds_power(int mac, int val);
 260
 261 #endif /* _RTL838X_ETH_H */