1 /* Smedia Glamo 336x/337x driver
3 * (C) 2007 by Openmoko, Inc.
4 * Author: Harald Welte <laforge@openmoko.org>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/errno.h>
26 #include <linux/string.h>
28 #include <linux/tty.h>
29 #include <linux/slab.h>
30 #include <linux/delay.h>
32 #include <linux/init.h>
33 #include <linux/irq.h>
34 #include <linux/interrupt.h>
35 #include <linux/workqueue.h>
36 #include <linux/wait.h>
37 #include <linux/platform_device.h>
38 #include <linux/kernel_stat.h>
39 #include <linux/spinlock.h>
40 #include <linux/glamofb.h>
41 #include <linux/mmc/mmc.h>
42 #include <linux/mmc/host.h>
43 #include <linux/mfd/core.h>
46 #include <asm/uaccess.h>
47 #include <asm/div64.h>
53 #include "glamo-regs.h"
54 #include "glamo-core.h"
56 #define GLAMO_MEM_REFRESH_COUNT 0x100
59 * Glamo internal settings
61 * We run the memory interface from the faster PLLB on 2.6.28 kernels and
62 * above. Couple of GTA02 users report trouble with memory bus when they
63 * upgraded from 2.6.24. So this parameter allows reversion to 2.6.24
64 * scheme if their Glamo chip needs it.
66 * you can override the faster default on kernel commandline using
68 * glamo3362.slow_memory=1
73 static int slow_memory
= 0;
74 module_param(slow_memory
, int, 0644);
82 struct reg_range reg_range
[] = {
83 { 0x0000, 0x76, "General", 1 },
84 { 0x0200, 0x16, "Host Bus", 1 },
85 { 0x0300, 0x38, "Memory", 1 },
86 /* { 0x0400, 0x100, "Sensor", 0 }, */
87 /* { 0x0500, 0x300, "ISP", 0 }, */
88 /* { 0x0800, 0x400, "JPEG", 0 }, */
89 /* { 0x0c00, 0xcc, "MPEG", 0 }, */
90 { 0x1100, 0xb2, "LCD 1", 1 },
91 { 0x1200, 0x64, "LCD 2", 1 },
92 { 0x1400, 0x40, "MMC", 1 },
93 /* { 0x1500, 0x080, "MPU 0", 0 },
94 { 0x1580, 0x080, "MPU 1", 0 },
95 { 0x1600, 0x080, "Cmd Queue", 0 },
96 { 0x1680, 0x080, "RISC CPU", 0 },
97 { 0x1700, 0x400, "2D Unit", 0 },
98 { 0x1b00, 0x900, "3D Unit", 0 }, */
101 static inline void __reg_write(struct glamo_core
*glamo
,
102 u_int16_t reg
, u_int16_t val
)
104 writew(val
, glamo
->base
+ reg
);
107 static inline u_int16_t
__reg_read(struct glamo_core
*glamo
,
110 return readw(glamo
->base
+ reg
);
113 static void __reg_set_bit_mask(struct glamo_core
*glamo
,
114 u_int16_t reg
, u_int16_t mask
,
121 tmp
= __reg_read(glamo
, reg
);
124 __reg_write(glamo
, reg
, tmp
);
127 static void reg_set_bit_mask(struct glamo_core
*glamo
,
128 u_int16_t reg
, u_int16_t mask
,
131 spin_lock(&glamo
->lock
);
132 __reg_set_bit_mask(glamo
, reg
, mask
, val
);
133 spin_unlock(&glamo
->lock
);
136 static inline void __reg_set_bit(struct glamo_core
*glamo
,
137 u_int16_t reg
, u_int16_t bit
)
139 __reg_set_bit_mask(glamo
, reg
, bit
, 0xffff);
142 static inline void __reg_clear_bit(struct glamo_core
*glamo
,
143 u_int16_t reg
, u_int16_t bit
)
145 __reg_set_bit_mask(glamo
, reg
, bit
, 0);
148 /***********************************************************************
149 * resources of sibling devices
150 ***********************************************************************/
152 static struct resource glamo_fb_resources
[] = {
154 .name
= "glamo-fb-regs",
155 .start
= GLAMO_REGOFS_LCD
,
156 .end
= GLAMO_REGOFS_MMC
- 1,
157 .flags
= IORESOURCE_MEM
,
159 .name
= "glamo-fb-mem",
160 .start
= GLAMO_OFFSET_FB
,
161 .end
= GLAMO_OFFSET_FB
+ GLAMO_FB_SIZE
- 1,
162 .flags
= IORESOURCE_MEM
,
166 static struct resource glamo_mmc_resources
[] = {
168 .start
= GLAMO_REGOFS_MMC
,
169 .end
= GLAMO_REGOFS_MPROC0
- 1,
170 .flags
= IORESOURCE_MEM
172 .start
= IRQ_GLAMO_MMC
,
173 .end
= IRQ_GLAMO_MMC
,
174 .flags
= IORESOURCE_IRQ
,
175 }, { /* our data buffer for MMC transfers */
176 .start
= GLAMO_OFFSET_FB
+ GLAMO_FB_SIZE
,
177 .end
= GLAMO_OFFSET_FB
+ GLAMO_FB_SIZE
+
178 GLAMO_MMC_BUFFER_SIZE
- 1,
179 .flags
= IORESOURCE_MEM
183 static struct glamo_mci_pdata glamo_mci_def_pdata
= {
185 .glamo_can_set_mci_power
= NULL
, /* filled in from MFD platform data */
186 .glamo_irq_is_wired
= NULL
, /* filled in from MFD platform data */
187 .mci_suspending
= NULL
, /* filled in from MFD platform data */
188 .mci_all_dependencies_resumed
= NULL
, /* filled in from MFD platform data */
197 static struct mfd_cell glamo_cells
[] = {
200 .num_resources
= ARRAY_SIZE(glamo_fb_resources
),
201 .resources
= glamo_fb_resources
,
205 .num_resources
= ARRAY_SIZE(glamo_mmc_resources
),
206 .resources
= glamo_mmc_resources
,
208 [GLAMO_CELL_SPI_GPIO
] = {
209 .name
= "glamo-spi-gpio",
214 /***********************************************************************
216 ***********************************************************************/
217 #define irq2glamo(x) (x - IRQ_GLAMO(0))
219 static void glamo_ack_irq(unsigned int irq
)
221 struct glamo_core
*glamo
= (struct glamo_core
*)get_irq_chip_data(irq
);
222 /* clear interrupt source */
223 __reg_write(glamo
, GLAMO_REG_IRQ_CLEAR
,
224 1 << irq2glamo(irq
));
227 static void glamo_mask_irq(unsigned int irq
)
229 struct glamo_core
*glamo
= (struct glamo_core
*)get_irq_chip_data(irq
);
232 /* clear bit in enable register */
233 tmp
= __reg_read(glamo
, GLAMO_REG_IRQ_ENABLE
);
234 tmp
&= ~(1 << irq2glamo(irq
));
235 __reg_write(glamo
, GLAMO_REG_IRQ_ENABLE
, tmp
);
238 static void glamo_unmask_irq(unsigned int irq
)
240 struct glamo_core
*glamo
= (struct glamo_core
*)get_irq_chip_data(irq
);
243 /* set bit in enable register */
244 tmp
= __reg_read(glamo
, GLAMO_REG_IRQ_ENABLE
);
245 tmp
|= (1 << irq2glamo(irq
));
246 __reg_write(glamo
, GLAMO_REG_IRQ_ENABLE
, tmp
);
249 static struct irq_chip glamo_irq_chip
= {
251 .ack
= glamo_ack_irq
,
252 .mask
= glamo_mask_irq
,
253 .unmask
= glamo_unmask_irq
,
256 static void glamo_irq_demux_handler(unsigned int irq
, struct irq_desc
*desc
)
258 struct glamo_core
*glamo
= get_irq_desc_chip_data(desc
);
259 desc
->status
&= ~(IRQ_REPLAY
| IRQ_WAITING
);
261 if (unlikely(desc
->status
& IRQ_INPROGRESS
)) {
262 desc
->status
|= (IRQ_PENDING
| IRQ_MASKED
);
263 desc
->chip
->mask(irq
);
264 desc
->chip
->ack(irq
);
267 kstat_incr_irqs_this_cpu(irq
, desc
);
269 desc
->chip
->ack(irq
);
270 desc
->status
|= IRQ_INPROGRESS
;
276 if (unlikely((desc
->status
&
277 (IRQ_PENDING
| IRQ_MASKED
| IRQ_DISABLED
)) ==
278 (IRQ_PENDING
| IRQ_MASKED
))) {
279 /* dealing with pending IRQ, unmasking */
280 desc
->chip
->unmask(irq
);
281 desc
->status
&= ~IRQ_MASKED
;
284 desc
->status
&= ~IRQ_PENDING
;
286 /* read IRQ status register */
287 irqstatus
= __reg_read(glamo
, GLAMO_REG_IRQ_STATUS
);
288 for (i
= 0; i
< 9; i
++)
289 if (irqstatus
& (1 << i
))
290 desc_handle_irq(IRQ_GLAMO(i
),
291 irq_desc
+IRQ_GLAMO(i
));
293 } while ((desc
->status
& (IRQ_PENDING
| IRQ_DISABLED
)) == IRQ_PENDING
);
295 desc
->status
&= ~IRQ_INPROGRESS
;
299 static ssize_t
regs_write(struct device
*dev
, struct device_attribute
*attr
,
300 const char *buf
, size_t count
)
302 unsigned long reg
= simple_strtoul(buf
, NULL
, 10);
303 struct glamo_core
*glamo
= dev_get_drvdata(dev
);
305 while (*buf
&& (*buf
!= ' '))
309 while (*buf
&& (*buf
== ' '))
314 printk(KERN_INFO
"reg 0x%02lX <-- 0x%04lX\n",
315 reg
, simple_strtoul(buf
, NULL
, 10));
317 __reg_write(glamo
, reg
, simple_strtoul(buf
, NULL
, 10));
322 static ssize_t
regs_read(struct device
*dev
, struct device_attribute
*attr
,
325 struct glamo_core
*glamo
= dev_get_drvdata(dev
);
329 spin_lock(&glamo
->lock
);
331 for (r
= 0; r
< ARRAY_SIZE(reg_range
); r
++) {
332 if (!reg_range
[r
].dump
)
335 end
+= sprintf(end
, "\n%s\n", reg_range
[r
].name
);
336 for (n
= reg_range
[r
].start
;
337 n
< reg_range
[r
].start
+ reg_range
[r
].count
; n
+= 2) {
338 if (((n1
++) & 7) == 0)
339 end
+= sprintf(end
, "\n%04X: ", n
);
340 end
+= sprintf(end
, "%04x ", __reg_read(glamo
, n
));
342 end
+= sprintf(end
, "\n");
348 spin_unlock(&glamo
->lock
);
353 static DEVICE_ATTR(regs
, 0644, regs_read
, regs_write
);
354 static struct attribute
*glamo_sysfs_entries
[] = {
358 static struct attribute_group glamo_attr_group
= {
360 .attrs
= glamo_sysfs_entries
,
365 /***********************************************************************
367 ***********************************************************************/
369 int __glamo_engine_enable(struct glamo_core
*glamo
, enum glamo_engine engine
)
372 case GLAMO_ENGINE_LCD
:
373 __reg_set_bit_mask(glamo
, GLAMO_REG_HOSTBUS(2),
374 GLAMO_HOSTBUS2_MMIO_EN_LCD
,
375 GLAMO_HOSTBUS2_MMIO_EN_LCD
);
376 __reg_write(glamo
, GLAMO_REG_CLOCK_LCD
,
377 GLAMO_CLOCK_LCD_EN_M5CLK
|
378 GLAMO_CLOCK_LCD_EN_DHCLK
|
379 GLAMO_CLOCK_LCD_EN_DMCLK
|
380 GLAMO_CLOCK_LCD_EN_DCLK
|
381 GLAMO_CLOCK_LCD_DG_M5CLK
|
382 GLAMO_CLOCK_LCD_DG_DMCLK
);
383 __reg_set_bit_mask(glamo
, GLAMO_REG_CLOCK_GEN5_1
,
384 GLAMO_CLOCK_GEN51_EN_DIV_DHCLK
|
385 GLAMO_CLOCK_GEN51_EN_DIV_DMCLK
|
386 GLAMO_CLOCK_GEN51_EN_DIV_DCLK
, 0xffff);
388 case GLAMO_ENGINE_MMC
:
389 __reg_set_bit_mask(glamo
, GLAMO_REG_HOSTBUS(2),
390 GLAMO_HOSTBUS2_MMIO_EN_MMC
,
391 GLAMO_HOSTBUS2_MMIO_EN_MMC
);
392 __reg_set_bit_mask(glamo
, GLAMO_REG_CLOCK_MMC
,
393 GLAMO_CLOCK_MMC_EN_M9CLK
|
394 GLAMO_CLOCK_MMC_EN_TCLK
|
395 GLAMO_CLOCK_MMC_DG_M9CLK
|
396 GLAMO_CLOCK_MMC_DG_TCLK
, 0xffff);
397 /* enable the TCLK divider clk input */
398 __reg_set_bit_mask(glamo
, GLAMO_REG_CLOCK_GEN5_1
,
399 GLAMO_CLOCK_GEN51_EN_DIV_TCLK
,
400 GLAMO_CLOCK_GEN51_EN_DIV_TCLK
);
402 case GLAMO_ENGINE_2D
:
403 __reg_set_bit_mask(glamo
, GLAMO_REG_CLOCK_2D
,
404 GLAMO_CLOCK_2D_EN_M7CLK
|
405 GLAMO_CLOCK_2D_EN_GCLK
|
406 GLAMO_CLOCK_2D_DG_M7CLK
|
407 GLAMO_CLOCK_2D_DG_GCLK
, 0xffff);
408 __reg_set_bit_mask(glamo
, GLAMO_REG_HOSTBUS(2),
409 GLAMO_HOSTBUS2_MMIO_EN_2D
,
410 GLAMO_HOSTBUS2_MMIO_EN_2D
);
411 __reg_set_bit_mask(glamo
, GLAMO_REG_CLOCK_GEN5_1
,
412 GLAMO_CLOCK_GEN51_EN_DIV_GCLK
,
415 case GLAMO_ENGINE_CMDQ
:
416 __reg_set_bit_mask(glamo
, GLAMO_REG_CLOCK_2D
,
417 GLAMO_CLOCK_2D_EN_M6CLK
, 0xffff);
418 __reg_set_bit_mask(glamo
, GLAMO_REG_HOSTBUS(2),
419 GLAMO_HOSTBUS2_MMIO_EN_CQ
,
420 GLAMO_HOSTBUS2_MMIO_EN_CQ
);
421 __reg_set_bit_mask(glamo
, GLAMO_REG_CLOCK_GEN5_1
,
422 GLAMO_CLOCK_GEN51_EN_DIV_MCLK
,
425 /* FIXME: Implementation */
430 glamo
->engine_enabled_bitfield
|= 1 << engine
;
435 int glamo_engine_enable(struct glamo_core
*glamo
, enum glamo_engine engine
)
439 spin_lock(&glamo
->lock
);
441 ret
= __glamo_engine_enable(glamo
, engine
);
443 spin_unlock(&glamo
->lock
);
447 EXPORT_SYMBOL_GPL(glamo_engine_enable
);
449 int __glamo_engine_disable(struct glamo_core
*glamo
, enum glamo_engine engine
)
452 case GLAMO_ENGINE_LCD
:
453 /* remove pixel clock to LCM */
454 __reg_set_bit_mask(glamo
, GLAMO_REG_CLOCK_LCD
,
455 GLAMO_CLOCK_LCD_EN_DCLK
, 0);
456 __reg_set_bit_mask(glamo
, GLAMO_REG_CLOCK_LCD
,
457 GLAMO_CLOCK_LCD_EN_DHCLK
|
458 GLAMO_CLOCK_LCD_EN_DMCLK
, 0);
459 /* kill memory clock */
460 __reg_set_bit_mask(glamo
, GLAMO_REG_CLOCK_LCD
,
461 GLAMO_CLOCK_LCD_EN_M5CLK
, 0);
462 /* stop dividing the clocks */
463 __reg_set_bit_mask(glamo
, GLAMO_REG_CLOCK_GEN5_1
,
464 GLAMO_CLOCK_GEN51_EN_DIV_DHCLK
|
465 GLAMO_CLOCK_GEN51_EN_DIV_DMCLK
|
466 GLAMO_CLOCK_GEN51_EN_DIV_DCLK
, 0);
469 case GLAMO_ENGINE_MMC
:
470 __reg_set_bit_mask(glamo
, GLAMO_REG_CLOCK_MMC
,
471 GLAMO_CLOCK_MMC_EN_M9CLK
|
472 GLAMO_CLOCK_MMC_EN_TCLK
|
473 GLAMO_CLOCK_MMC_DG_M9CLK
|
474 GLAMO_CLOCK_MMC_DG_TCLK
, 0);
475 /* disable the TCLK divider clk input */
476 __reg_set_bit_mask(glamo
, GLAMO_REG_CLOCK_GEN5_1
,
477 GLAMO_CLOCK_GEN51_EN_DIV_TCLK
, 0);
479 case GLAMO_ENGINE_CMDQ
:
480 __reg_set_bit_mask(glamo
, GLAMO_REG_CLOCK_2D
,
481 GLAMO_CLOCK_2D_EN_M6CLK
,
483 __reg_set_bit_mask(glamo
, GLAMO_REG_HOSTBUS(2),
484 GLAMO_HOSTBUS2_MMIO_EN_CQ
,
485 GLAMO_HOSTBUS2_MMIO_EN_CQ
);
486 /* __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
487 GLAMO_CLOCK_GEN51_EN_DIV_MCLK,
490 case GLAMO_ENGINE_2D
:
491 __reg_set_bit_mask(glamo
, GLAMO_REG_CLOCK_2D
,
492 GLAMO_CLOCK_2D_EN_M7CLK
|
493 GLAMO_CLOCK_2D_EN_GCLK
|
494 GLAMO_CLOCK_2D_DG_M7CLK
|
495 GLAMO_CLOCK_2D_DG_GCLK
,
497 __reg_set_bit_mask(glamo
, GLAMO_REG_HOSTBUS(2),
498 GLAMO_HOSTBUS2_MMIO_EN_2D
,
499 GLAMO_HOSTBUS2_MMIO_EN_2D
);
500 __reg_set_bit_mask(glamo
, GLAMO_REG_CLOCK_GEN5_1
,
501 GLAMO_CLOCK_GEN51_EN_DIV_GCLK
,
508 glamo
->engine_enabled_bitfield
&= ~(1 << engine
);
512 int glamo_engine_disable(struct glamo_core
*glamo
, enum glamo_engine engine
)
516 spin_lock(&glamo
->lock
);
518 ret
= __glamo_engine_disable(glamo
, engine
);
520 spin_unlock(&glamo
->lock
);
524 EXPORT_SYMBOL_GPL(glamo_engine_disable
);
526 static const u_int16_t engine_clock_regs
[__NUM_GLAMO_ENGINES
] = {
527 [GLAMO_ENGINE_LCD
] = GLAMO_REG_CLOCK_LCD
,
528 [GLAMO_ENGINE_MMC
] = GLAMO_REG_CLOCK_MMC
,
529 [GLAMO_ENGINE_ISP
] = GLAMO_REG_CLOCK_ISP
,
530 [GLAMO_ENGINE_JPEG
] = GLAMO_REG_CLOCK_JPEG
,
531 [GLAMO_ENGINE_3D
] = GLAMO_REG_CLOCK_3D
,
532 [GLAMO_ENGINE_2D
] = GLAMO_REG_CLOCK_2D
,
533 [GLAMO_ENGINE_MPEG_ENC
] = GLAMO_REG_CLOCK_MPEG
,
534 [GLAMO_ENGINE_MPEG_DEC
] = GLAMO_REG_CLOCK_MPEG
,
537 void glamo_engine_clkreg_set(struct glamo_core
*glamo
,
538 enum glamo_engine engine
,
539 u_int16_t mask
, u_int16_t val
)
541 reg_set_bit_mask(glamo
, engine_clock_regs
[engine
], mask
, val
);
543 EXPORT_SYMBOL_GPL(glamo_engine_clkreg_set
);
545 u_int16_t
glamo_engine_clkreg_get(struct glamo_core
*glamo
,
546 enum glamo_engine engine
)
550 spin_lock(&glamo
->lock
);
551 val
= __reg_read(glamo
, engine_clock_regs
[engine
]);
552 spin_unlock(&glamo
->lock
);
556 EXPORT_SYMBOL_GPL(glamo_engine_clkreg_get
);
558 struct glamo_script reset_regs
[] = {
559 [GLAMO_ENGINE_LCD
] = {
560 GLAMO_REG_CLOCK_LCD
, GLAMO_CLOCK_LCD_RESET
563 [GLAMO_ENGINE_HOST
] = {
564 GLAMO_REG_CLOCK_HOST
, GLAMO_CLOCK_HOST_RESET
566 [GLAMO_ENGINE_MEM
] = {
567 GLAMO_REG_CLOCK_MEM
, GLAMO_CLOCK_MEM_RESET
570 [GLAMO_ENGINE_MMC
] = {
571 GLAMO_REG_CLOCK_MMC
, GLAMO_CLOCK_MMC_RESET
573 [GLAMO_ENGINE_CMDQ
] = {
574 GLAMO_REG_CLOCK_2D
, GLAMO_CLOCK_2D_CQ_RESET
576 [GLAMO_ENGINE_2D
] = {
577 GLAMO_REG_CLOCK_2D
, GLAMO_CLOCK_2D_RESET
579 [GLAMO_ENGINE_JPEG
] = {
580 GLAMO_REG_CLOCK_JPEG
, GLAMO_CLOCK_JPEG_RESET
584 void glamo_engine_reset(struct glamo_core
*glamo
, enum glamo_engine engine
)
586 struct glamo_script
*rst
;
588 if (engine
>= ARRAY_SIZE(reset_regs
)) {
589 dev_warn(&glamo
->pdev
->dev
, "unknown engine %u ", engine
);
593 rst
= &reset_regs
[engine
];
595 spin_lock(&glamo
->lock
);
596 __reg_set_bit(glamo
, rst
->reg
, rst
->val
);
597 __reg_clear_bit(glamo
, rst
->reg
, rst
->val
);
598 spin_unlock(&glamo
->lock
);
600 EXPORT_SYMBOL_GPL(glamo_engine_reset
);
602 void glamo_lcm_reset(struct platform_device
*pdev
, int level
)
604 struct glamo_core
*glamo
= dev_get_drvdata(&pdev
->dev
);
608 glamo_gpio_setpin(glamo
, GLAMO_GPIO4
, level
);
609 glamo_gpio_cfgpin(glamo
, GLAMO_GPIO4_OUTPUT
);
611 EXPORT_SYMBOL_GPL(glamo_lcm_reset
);
618 static int glamo_pll_rate(struct glamo_core
*glamo
,
622 unsigned int div
= 512;
623 /* FIXME: move osci into platform_data */
624 unsigned int osci
= 32768;
631 reg
= __reg_read(glamo
, GLAMO_REG_PLL_GEN1
);
634 reg
= __reg_read(glamo
, GLAMO_REG_PLL_GEN3
);
639 return (osci
/div
)*reg
;
642 int glamo_engine_reclock(struct glamo_core
*glamo
,
643 enum glamo_engine engine
,
647 u_int16_t reg
, mask
, val
= 0;
653 case GLAMO_ENGINE_LCD
:
655 reg
= GLAMO_REG_CLOCK_GEN7
;
659 dev_warn(&glamo
->pdev
->dev
,
660 "reclock of engine 0x%x not supported\n", engine
);
665 pll
= glamo_pll_rate(glamo
, pll
);
666 khz
= 1000000000UL / ps
;
669 val
= (pll
/ khz
) / 1000;
671 dev_dbg(&glamo
->pdev
->dev
,
672 "PLL %d, kHZ %d, div %d\n", pll
, khz
, val
);
676 reg_set_bit_mask(glamo
, reg
, mask
, val
);
677 mdelay(5); /* wait some time to stabilize */
684 EXPORT_SYMBOL_GPL(glamo_engine_reclock
);
686 /***********************************************************************
688 ***********************************************************************/
690 int glamo_run_script(struct glamo_core
*glamo
, struct glamo_script
*script
,
691 int len
, int may_sleep
)
695 for (i
= 0; i
< len
; i
++) {
696 struct glamo_script
*line
= &script
[i
];
705 mdelay(line
->val
* 4);
708 /* spin until PLLs lock */
709 while ((__reg_read(glamo
, GLAMO_REG_PLL_GEN5
) & 3) != 3)
714 * couple of people reported artefacts with 2.6.28 changes, this
715 * allows reversion to 2.6.24 settings
719 switch (slow_memory
) {
720 /* choice 1 is the most conservative */
721 case 1: /* 3 waits on Async BB R & W, Use PLL 1 for mem bus */
722 __reg_write(glamo
, script
[i
].reg
, 0xef0);
724 case 2: /* 2 waits on Async BB R & W, Use PLL 1 for mem bus */
725 __reg_write(glamo
, script
[i
].reg
, 0xea0);
727 case 3: /* 1 waits on Async BB R & W, Use PLL 1 for mem bus */
728 __reg_write(glamo
, script
[i
].reg
, 0xe50);
730 case 4: /* 0 waits on Async BB R & W, Use PLL 1 for mem bus */
731 __reg_write(glamo
, script
[i
].reg
, 0xe00);
734 /* using PLL2 for memory bus increases CPU bandwidth significantly */
735 case 5: /* 3 waits on Async BB R & W, Use PLL 2 for mem bus */
736 __reg_write(glamo
, script
[i
].reg
, 0xef3);
738 case 6: /* 2 waits on Async BB R & W, Use PLL 2 for mem bus */
739 __reg_write(glamo
, script
[i
].reg
, 0xea3);
741 case 7: /* 1 waits on Async BB R & W, Use PLL 2 for mem bus */
742 __reg_write(glamo
, script
[i
].reg
, 0xe53);
744 /* default of 0 or >7 is fastest */
745 default: /* 0 waits on Async BB R & W, Use PLL 2 for mem bus */
746 __reg_write(glamo
, script
[i
].reg
, 0xe03);
752 __reg_write(glamo
, script
[i
].reg
, script
[i
].val
);
759 EXPORT_SYMBOL(glamo_run_script
);
761 static struct glamo_script glamo_init_script
[] = {
762 { GLAMO_REG_CLOCK_HOST
, 0x1000 },
764 { GLAMO_REG_CLOCK_MEMORY
, 0x1000 },
765 { GLAMO_REG_CLOCK_MEMORY
, 0x2000 },
766 { GLAMO_REG_CLOCK_LCD
, 0x1000 },
767 { GLAMO_REG_CLOCK_MMC
, 0x1000 },
768 { GLAMO_REG_CLOCK_ISP
, 0x1000 },
769 { GLAMO_REG_CLOCK_ISP
, 0x3000 },
770 { GLAMO_REG_CLOCK_JPEG
, 0x1000 },
771 { GLAMO_REG_CLOCK_3D
, 0x1000 },
772 { GLAMO_REG_CLOCK_3D
, 0x3000 },
773 { GLAMO_REG_CLOCK_2D
, 0x1000 },
774 { GLAMO_REG_CLOCK_2D
, 0x3000 },
775 { GLAMO_REG_CLOCK_RISC1
, 0x1000 },
776 { GLAMO_REG_CLOCK_MPEG
, 0x3000 },
777 { GLAMO_REG_CLOCK_MPEG
, 0x3000 },
778 { GLAMO_REG_CLOCK_MPROC
, 0x1000 /*0x100f*/ },
780 { GLAMO_REG_CLOCK_HOST
, 0x0000 },
781 { GLAMO_REG_CLOCK_MEMORY
, 0x0000 },
782 { GLAMO_REG_CLOCK_LCD
, 0x0000 },
783 { GLAMO_REG_CLOCK_MMC
, 0x0000 },
785 /* unused engines must be left in reset to stop MMC block read "blackouts" */
786 { GLAMO_REG_CLOCK_ISP
, 0x0000 },
787 { GLAMO_REG_CLOCK_ISP
, 0x0000 },
788 { GLAMO_REG_CLOCK_JPEG
, 0x0000 },
789 { GLAMO_REG_CLOCK_3D
, 0x0000 },
790 { GLAMO_REG_CLOCK_3D
, 0x0000 },
791 { GLAMO_REG_CLOCK_2D
, 0x0000 },
792 { GLAMO_REG_CLOCK_2D
, 0x0000 },
793 { GLAMO_REG_CLOCK_RISC1
, 0x0000 },
794 { GLAMO_REG_CLOCK_MPEG
, 0x0000 },
795 { GLAMO_REG_CLOCK_MPEG
, 0x0000 },
797 { GLAMO_REG_PLL_GEN1
, 0x05db }, /* 48MHz */
798 { GLAMO_REG_PLL_GEN3
, 0x0aba }, /* 90MHz */
801 * b9 of this register MUST be zero to get any interrupts on INT#
802 * the other set bits enable all the engine interrupt sources
804 { GLAMO_REG_IRQ_ENABLE
, 0x01ff },
805 { GLAMO_REG_CLOCK_GEN6
, 0x2000 },
806 { GLAMO_REG_CLOCK_GEN7
, 0x0101 },
807 { GLAMO_REG_CLOCK_GEN8
, 0x0100 },
808 { GLAMO_REG_CLOCK_HOST
, 0x000d },
810 * b7..b4 = 0 = no wait states on read or write
811 * b0 = 1 select PLL2 for Host interface, b1 = enable it
813 { 0x200, 0x0e03 /* this is replaced by script parser */ },
819 /* S-Media recommended "set tiling mode to 512 mode for memory access
820 * more efficiency when 640x480" */
821 { GLAMO_REG_MEM_TYPE
, 0x0c74 }, /* 8MB, 16 word pg wr+rd */
822 { GLAMO_REG_MEM_GEN
, 0xafaf }, /* 63 grants min + max */
824 { GLAMO_REGOFS_HOSTBUS
+ 2, 0xffff }, /* enable on MMIO*/
826 { GLAMO_REG_MEM_TIMING1
, 0x0108 },
827 { GLAMO_REG_MEM_TIMING2
, 0x0010 }, /* Taa = 3 MCLK */
828 { GLAMO_REG_MEM_TIMING3
, 0x0000 },
829 { GLAMO_REG_MEM_TIMING4
, 0x0000 }, /* CE1# delay fall/rise */
830 { GLAMO_REG_MEM_TIMING5
, 0x0000 }, /* UB# LB# */
831 { GLAMO_REG_MEM_TIMING6
, 0x0000 }, /* OE# */
832 { GLAMO_REG_MEM_TIMING7
, 0x0000 }, /* WE# */
833 { GLAMO_REG_MEM_TIMING8
, 0x1002 }, /* MCLK delay, was 0x1000 */
834 { GLAMO_REG_MEM_TIMING9
, 0x6006 },
835 { GLAMO_REG_MEM_TIMING10
, 0x00ff },
836 { GLAMO_REG_MEM_TIMING11
, 0x0001 },
837 { GLAMO_REG_MEM_POWER1
, 0x0020 },
838 { GLAMO_REG_MEM_POWER2
, 0x0000 },
839 { GLAMO_REG_MEM_DRAM1
, 0x0000 },
841 { GLAMO_REG_MEM_DRAM1
, 0xc100 },
843 { GLAMO_REG_MEM_DRAM1
, 0xe100 },
844 { GLAMO_REG_MEM_DRAM2
, 0x01d6 },
845 { GLAMO_REG_CLOCK_MEMORY
, 0x000b },
846 { GLAMO_REG_GPIO_GEN1
, 0x000f },
847 { GLAMO_REG_GPIO_GEN2
, 0x111e },
848 { GLAMO_REG_GPIO_GEN3
, 0xccc3 },
849 { GLAMO_REG_GPIO_GEN4
, 0x111e },
850 { GLAMO_REG_GPIO_GEN5
, 0x000f },
853 static struct glamo_script glamo_resume_script
[] = {
855 { GLAMO_REG_PLL_GEN1
, 0x05db }, /* 48MHz */
856 { GLAMO_REG_PLL_GEN3
, 0x0aba }, /* 90MHz */
857 { GLAMO_REG_DFT_GEN6
, 1 },
863 * b9 of this register MUST be zero to get any interrupts on INT#
864 * the other set bits enable all the engine interrupt sources
866 { GLAMO_REG_IRQ_ENABLE
, 0x01ff },
867 { GLAMO_REG_CLOCK_HOST
, 0x0018 },
868 { GLAMO_REG_CLOCK_GEN5_1
, 0x18b1 },
870 { GLAMO_REG_MEM_DRAM1
, 0x0000 },
872 { GLAMO_REG_MEM_DRAM1
, 0xc100 },
874 { GLAMO_REG_MEM_DRAM1
, 0xe100 },
875 { GLAMO_REG_MEM_DRAM2
, 0x01d6 },
876 { GLAMO_REG_CLOCK_MEMORY
, 0x000b },
885 static void glamo_power(struct glamo_core
*glamo
,
886 enum glamo_power new_state
)
891 spin_lock_irqsave(&glamo
->lock
, flags
);
893 dev_info(&glamo
->pdev
->dev
, "***** glamo_power -> %d\n", new_state
);
897 static const REG_VALUE_MASK_TYPE reg_powerOn[] =
899 { REG_GEN_DFT6, REG_BIT_ALL, REG_DATA(1u << 0) },
900 { REG_GEN_PLL3, 0u, REG_DATA(1u << 13) },
901 { REG_GEN_MEM_CLK, REG_BIT_ALL, REG_BIT_EN_MOCACLK },
902 { REG_MEM_DRAM2, 0u, REG_BIT_EN_DEEP_POWER_DOWN },
903 { REG_MEM_DRAM1, 0u, REG_BIT_SELF_REFRESH }
906 static const REG_VALUE_MASK_TYPE reg_powerStandby[] =
908 { REG_MEM_DRAM1, REG_BIT_ALL, REG_BIT_SELF_REFRESH },
909 { REG_GEN_MEM_CLK, 0u, REG_BIT_EN_MOCACLK },
910 { REG_GEN_PLL3, REG_BIT_ALL, REG_DATA(1u << 13) },
911 { REG_GEN_DFT5, REG_BIT_ALL, REG_DATA(1u << 0) }
914 static const REG_VALUE_MASK_TYPE reg_powerSuspend[] =
916 { REG_MEM_DRAM2, REG_BIT_ALL, REG_BIT_EN_DEEP_POWER_DOWN },
917 { REG_GEN_MEM_CLK, 0u, REG_BIT_EN_MOCACLK },
918 { REG_GEN_PLL3, REG_BIT_ALL, REG_DATA(1u << 13) },
919 { REG_GEN_DFT5, REG_BIT_ALL, REG_DATA(1u << 0) }
927 * glamo state on resume is nondeterministic in some
928 * fundamental way, it has also been observed that the
929 * Glamo reset pin can get asserted by, eg, touching it with
930 * a scope probe. So the only answer is to roll with it and
931 * force an external reset on the Glamo during resume.
934 (glamo
->pdata
->glamo_external_reset
)(0);
936 (glamo
->pdata
->glamo_external_reset
)(1);
939 glamo_run_script(glamo
, glamo_init_script
,
940 ARRAY_SIZE(glamo_init_script
), 0);
944 case GLAMO_POWER_SUSPEND
:
946 /* nuke interrupts */
947 __reg_write(glamo
, GLAMO_REG_IRQ_ENABLE
, 0x200);
949 /* stash a copy of which engines were running */
950 glamo
->engine_enabled_bitfield_suspend
=
951 glamo
->engine_enabled_bitfield
;
953 /* take down each engine before we kill mem and pll */
954 for (n
= 0; n
< __NUM_GLAMO_ENGINES
; n
++)
955 if (glamo
->engine_enabled_bitfield
& (1 << n
))
956 __glamo_engine_disable(glamo
, n
);
958 /* enable self-refresh */
960 __reg_write(glamo
, GLAMO_REG_MEM_DRAM1
,
961 GLAMO_MEM_DRAM1_EN_DRAM_REFRESH
|
962 GLAMO_MEM_DRAM1_EN_GATE_CKE
|
963 GLAMO_MEM_DRAM1_SELF_REFRESH
|
964 GLAMO_MEM_REFRESH_COUNT
);
965 __reg_write(glamo
, GLAMO_REG_MEM_DRAM1
,
966 GLAMO_MEM_DRAM1_EN_MODEREG_SET
|
967 GLAMO_MEM_DRAM1_EN_DRAM_REFRESH
|
968 GLAMO_MEM_DRAM1_EN_GATE_CKE
|
969 GLAMO_MEM_DRAM1_SELF_REFRESH
|
970 GLAMO_MEM_REFRESH_COUNT
);
972 /* force RAM into deep powerdown */
974 __reg_write(glamo
, GLAMO_REG_MEM_DRAM2
,
975 GLAMO_MEM_DRAM2_DEEP_PWRDOWN
|
978 (1 << 2) | /* tRCD */
979 2); /* CAS latency */
981 /* disable clocks to memory */
982 __reg_write(glamo
, GLAMO_REG_CLOCK_MEMORY
, 0);
984 /* all dividers from OSCI */
985 __reg_set_bit_mask(glamo
, GLAMO_REG_CLOCK_GEN5_1
, 0x400, 0x400);
987 /* PLL2 into bypass */
988 __reg_set_bit_mask(glamo
, GLAMO_REG_PLL_GEN3
, 1 << 12, 1 << 12);
990 __reg_write(glamo
, 0x200, 0x0e00);
993 /* kill PLLS 1 then 2 */
994 __reg_write(glamo
, GLAMO_REG_DFT_GEN5
, 0x0001);
995 __reg_set_bit_mask(glamo
, GLAMO_REG_PLL_GEN3
, 1 << 13, 1 << 13);
1000 spin_unlock_irqrestore(&glamo
->lock
, flags
);
1004 #define MEMDETECT_RETRY 6
1005 static unsigned int detect_memsize(struct glamo_core
*glamo
)
1009 /*static const u_int16_t pattern[] = {
1010 0x1111, 0x8a8a, 0x2222, 0x7a7a,
1011 0x3333, 0x6a6a, 0x4444, 0x5a5a,
1012 0x5555, 0x4a4a, 0x6666, 0x3a3a,
1013 0x7777, 0x2a2a, 0x8888, 0x1a1a
1016 for (i
= 0; i
< MEMDETECT_RETRY
; i
++) {
1017 switch (glamo
->type
) {
1019 __reg_write(glamo
, GLAMO_REG_MEM_TYPE
, 0x0072);
1020 __reg_write(glamo
, GLAMO_REG_MEM_DRAM1
, 0xc100);
1023 switch (glamo
->revision
) {
1024 case GLAMO_CORE_REV_A0
:
1026 __reg_write(glamo
, GLAMO_REG_MEM_TYPE
,
1029 __reg_write(glamo
, GLAMO_REG_MEM_TYPE
,
1032 __reg_write(glamo
, GLAMO_REG_MEM_DRAM1
, 0x0000);
1034 __reg_write(glamo
, GLAMO_REG_MEM_DRAM1
, 0xc100);
1038 __reg_write(glamo
, GLAMO_REG_MEM_TYPE
,
1041 __reg_write(glamo
, GLAMO_REG_MEM_TYPE
,
1044 __reg_write(glamo
, GLAMO_REG_MEM_DRAM1
, 0x0000);
1046 __reg_write(glamo
, GLAMO_REG_MEM_DRAM1
, 0xe100);
1057 /* FIXME: finish implementation */
1058 for (j
= 0; j
< 8; j
++) {
1067 /* Find out if we can support this version of the Glamo chip */
1068 static int glamo_supported(struct glamo_core
*glamo
)
1070 u_int16_t dev_id
, rev_id
; /*, memsize; */
1072 dev_id
= __reg_read(glamo
, GLAMO_REG_DEVICE_ID
);
1073 rev_id
= __reg_read(glamo
, GLAMO_REG_REVISION_ID
);
1078 case GLAMO_CORE_REV_A2
:
1080 case GLAMO_CORE_REV_A0
:
1081 case GLAMO_CORE_REV_A1
:
1082 case GLAMO_CORE_REV_A3
:
1083 dev_warn(&glamo
->pdev
->dev
, "untested core revision "
1084 "%04x, your mileage may vary\n", rev_id
);
1087 dev_warn(&glamo
->pdev
->dev
, "unknown glamo revision "
1088 "%04x, your mileage may vary\n", rev_id
);
1089 /* maybe should abort ? */
1095 dev_err(&glamo
->pdev
->dev
, "unsupported Glamo device %04x\n",
1100 dev_dbg(&glamo
->pdev
->dev
, "Detected Glamo core %04x Revision %04x "
1101 "(%uHz CPU / %uHz Memory)\n", dev_id
, rev_id
,
1102 glamo_pll_rate(glamo
, GLAMO_PLL1
),
1103 glamo_pll_rate(glamo
, GLAMO_PLL2
));
1108 static int __init
glamo_probe(struct platform_device
*pdev
)
1111 struct glamo_core
*glamo
;
1113 glamo
= kmalloc(GFP_KERNEL
, sizeof(*glamo
));
1117 spin_lock_init(&glamo
->lock
);
1119 glamo
->mem
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1120 glamo
->irq
= platform_get_irq(pdev
, 0);
1121 glamo
->pdata
= pdev
->dev
.platform_data
;
1122 if (!glamo
->mem
|| !glamo
->pdata
) {
1123 dev_err(&pdev
->dev
, "platform device with no MEM/PDATA ?\n");
1128 /* register a number of sibling devices whoise IOMEM resources
1129 * are siblings of pdev's IOMEM resource */
1131 /* only remap the generic, hostbus and memory controller registers */
1132 glamo
->base
= ioremap(glamo
->mem
->start
, 0x4000 /*GLAMO_REGOFS_VIDCAP*/);
1134 dev_err(&pdev
->dev
, "failed to ioremap() memory region\n");
1138 platform_set_drvdata(pdev
, glamo
);
1140 (glamo
->pdata
->glamo_external_reset
)(0);
1142 (glamo
->pdata
->glamo_external_reset
)(1);
1146 * finally set the mfd interrupts up
1147 * can't do them earlier or sibling probes blow up
1150 for (irq
= IRQ_GLAMO(0); irq
<= IRQ_GLAMO(8); irq
++) {
1151 set_irq_chip_and_handler(irq
, &glamo_irq_chip
, handle_level_irq
);
1152 set_irq_flags(irq
, IRQF_VALID
);
1153 set_irq_chip_data(irq
, glamo
);
1156 if (glamo
->pdata
->glamo_irq_is_wired
&&
1157 !glamo
->pdata
->glamo_irq_is_wired()) {
1158 set_irq_chained_handler(glamo
->irq
, glamo_irq_demux_handler
);
1159 set_irq_type(glamo
->irq
, IRQ_TYPE_EDGE_FALLING
);
1160 set_irq_chip_data(glamo
->irq
, glamo
);
1161 dev_info(&pdev
->dev
, "Glamo interrupt registered\n");
1162 glamo
->irq_works
= 1;
1164 dev_err(&pdev
->dev
, "Glamo interrupt not used\n");
1165 glamo
->irq_works
= 0;
1168 /* confirm it isn't insane version */
1169 if (!glamo_supported(glamo
)) {
1170 dev_err(&pdev
->dev
, "This Glamo is not supported\n");
1175 rc
= sysfs_create_group(&pdev
->dev
.kobj
, &glamo_attr_group
);
1177 dev_err(&pdev
->dev
, "cannot create sysfs group\n");
1181 /* init the chip with canned register set */
1183 dev_dbg(&glamo
->pdev
->dev
, "running init script\n");
1184 glamo_run_script(glamo
, glamo_init_script
,
1185 ARRAY_SIZE(glamo_init_script
), 1);
1187 dev_info(&glamo
->pdev
->dev
, "Glamo core PLL1: %uHz, PLL2: %uHz\n",
1188 glamo_pll_rate(glamo
, GLAMO_PLL1
),
1189 glamo_pll_rate(glamo
, GLAMO_PLL2
));
1191 glamo
->pdata
->glamo
= glamo
;
1193 /* bring MCI specific stuff over from our MFD platform data */
1194 glamo_mci_def_pdata
.glamo_can_set_mci_power
=
1195 glamo
->pdata
->glamo_can_set_mci_power
;
1196 glamo_mci_def_pdata
.glamo_mci_use_slow
=
1197 glamo
->pdata
->glamo_mci_use_slow
;
1198 glamo_mci_def_pdata
.glamo_irq_is_wired
=
1199 glamo
->pdata
->glamo_irq_is_wired
;
1200 glamo_mci_def_pdata
.pglamo
= glamo
;
1202 /* register siblings */
1203 glamo_cells
[GLAMO_CELL_MMC
].platform_data
= &glamo_mci_def_pdata
;
1204 glamo_cells
[GLAMO_CELL_MMC
].data_size
= sizeof(glamo_mci_def_pdata
);
1206 glamo_cells
[GLAMO_CELL_FB
].platform_data
= glamo
->pdata
;
1207 glamo_cells
[GLAMO_CELL_FB
].data_size
= sizeof(struct glamofb_platform_data
);
1209 glamo
->pdata
->spigpio_info
->glamo
= glamo
;
1210 glamo_cells
[GLAMO_CELL_SPI_GPIO
].platform_data
= glamo
->pdata
->spigpio_info
;
1211 glamo_cells
[GLAMO_CELL_SPI_GPIO
].data_size
=
1212 sizeof(struct glamo_spigpio_info
);
1214 mfd_add_devices(&pdev
->dev
, pdev
->id
, glamo_cells
,
1215 ARRAY_SIZE(glamo_cells
),
1218 /* only request the generic, hostbus and memory controller MMIO */
1219 glamo
->mem
= request_mem_region(glamo
->mem
->start
,
1220 GLAMO_REGOFS_VIDCAP
, "glamo-core");
1222 dev_err(&pdev
->dev
, "failed to request memory region\n");
1229 disable_irq(glamo
->irq
);
1230 set_irq_chained_handler(glamo
->irq
, NULL
);
1231 set_irq_chip_data(glamo
->irq
, NULL
);
1233 for (irq
= IRQ_GLAMO(0); irq
<= IRQ_GLAMO(8); irq
++) {
1234 set_irq_flags(irq
, 0);
1235 set_irq_chip(irq
, NULL
);
1236 set_irq_chip_data(irq
, NULL
);
1239 iounmap(glamo
->base
);
1241 platform_set_drvdata(pdev
, NULL
);
1247 static int glamo_remove(struct platform_device
*pdev
)
1249 struct glamo_core
*glamo
= platform_get_drvdata(pdev
);
1252 disable_irq(glamo
->irq
);
1253 set_irq_chained_handler(glamo
->irq
, NULL
);
1254 set_irq_chip_data(glamo
->irq
, NULL
);
1256 for (irq
= IRQ_GLAMO(0); irq
<= IRQ_GLAMO(8); irq
++) {
1257 set_irq_flags(irq
, 0);
1258 set_irq_chip(irq
, NULL
);
1259 set_irq_chip_data(irq
, NULL
);
1262 platform_set_drvdata(pdev
, NULL
);
1263 mfd_remove_devices(&pdev
->dev
);
1264 iounmap(glamo
->base
);
1265 release_mem_region(glamo
->mem
->start
, GLAMO_REGOFS_VIDCAP
);
1273 static int glamo_suspend(struct platform_device
*pdev
, pm_message_t state
)
1275 struct glamo_core
*glamo
= dev_get_drvdata(&pdev
->dev
);
1276 glamo
->suspending
= 1;
1277 glamo_power(glamo
, GLAMO_POWER_SUSPEND
);
1282 static int glamo_resume(struct platform_device
*pdev
)
1284 struct glamo_core
*glamo
= dev_get_drvdata(&pdev
->dev
);
1285 glamo_power(glamo
, GLAMO_POWER_ON
);
1286 glamo
->suspending
= 0;
1292 #define glamo_suspend NULL
1293 #define glamo_resume NULL
1296 static struct platform_driver glamo_driver
= {
1297 .probe
= glamo_probe
,
1298 .remove
= glamo_remove
,
1299 .suspend
= glamo_suspend
,
1300 .resume
= glamo_resume
,
1302 .name
= "glamo3362",
1303 .owner
= THIS_MODULE
,
1307 static int __devinit
glamo_init(void)
1309 return platform_driver_register(&glamo_driver
);
1312 static void __exit
glamo_cleanup(void)
1314 platform_driver_unregister(&glamo_driver
);
1317 module_init(glamo_init
);
1318 module_exit(glamo_cleanup
);
1320 MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
1321 MODULE_DESCRIPTION("Smedia Glamo 336x/337x core/resource driver");
1322 MODULE_LICENSE("GPL");