1 From ab5c8f5492cce16ff2104393e2f1fa64a3ff6e88 Mon Sep 17 00:00:00 2001
2 From: David Abdurachmanov <david.abdurachmanov@sifive.com>
3 Date: Wed, 17 Feb 2021 06:06:14 -0800
4 Subject: [PATCH 1/7] riscv: sifive: fu740: cpu{1,2,3,4} set compatible to
7 Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
9 arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 8 ++++----
10 1 file changed, 4 insertions(+), 4 deletions(-)
12 --- a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
13 +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
18 - compatible = "sifive,bullet0", "riscv";
19 + compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
20 d-cache-block-size = <64>;
22 d-cache-size = <32768>;
27 - compatible = "sifive,bullet0", "riscv";
28 + compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
29 d-cache-block-size = <64>;
31 d-cache-size = <32768>;
36 - compatible = "sifive,bullet0", "riscv";
37 + compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
38 d-cache-block-size = <64>;
40 d-cache-size = <32768>;
45 - compatible = "sifive,bullet0", "riscv";
46 + compatible = "sifive,u74-mc", "sifive,bullet0", "riscv";
47 d-cache-block-size = <64>;
49 d-cache-size = <32768>;