1 From cd833f484009f37be57a2aa09257af6e8c1b25b6 Mon Sep 17 00:00:00 2001
2 From: Emil Renner Berthing <kernel@esmil.dk>
3 Date: Sat, 1 Apr 2023 19:19:14 +0800
4 Subject: [PATCH 002/122] dt-bindings: clock: Add StarFive JH7110 always-on
5 clock and reset generator
7 Add bindings for the always-on clock and reset generator (AONCRG) on the
8 JH7110 RISC-V SoC by StarFive Ltd.
10 Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
11 Reviewed-by: Rob Herring <robh@kernel.org>
12 Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
13 Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
14 Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
15 Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
17 .../clock/starfive,jh7110-aoncrg.yaml | 107 ++++++++++++++++++
18 .../dt-bindings/clock/starfive,jh7110-crg.h | 18 +++
19 .../dt-bindings/reset/starfive,jh7110-crg.h | 12 ++
20 3 files changed, 137 insertions(+)
21 create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml
24 +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml
26 +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
29 +$id: http://devicetree.org/schemas/clock/starfive,jh7110-aoncrg.yaml#
30 +$schema: http://devicetree.org/meta-schemas/core.yaml#
32 +title: StarFive JH7110 Always-On Clock and Reset Generator
35 + - Emil Renner Berthing <kernel@esmil.dk>
39 + const: starfive,jh7110-aoncrg
47 + - description: Main Oscillator (24 MHz)
48 + - description: GMAC0 RMII reference or GMAC0 RGMII RX
49 + - description: STG AXI/AHB
50 + - description: APB Bus
51 + - description: GMAC0 GTX
54 + - description: Main Oscillator (24 MHz)
55 + - description: GMAC0 RMII reference or GMAC0 RGMII RX
56 + - description: STG AXI/AHB or GMAC0 RGMII RX
57 + - description: APB Bus or STG AXI/AHB
58 + - description: GMAC0 GTX or APB Bus
59 + - description: RTC Oscillator (32.768 kHz) or GMAC0 GTX
62 + - description: Main Oscillator (24 MHz)
63 + - description: GMAC0 RMII reference
64 + - description: GMAC0 RGMII RX
65 + - description: STG AXI/AHB
66 + - description: APB Bus
67 + - description: GMAC0 GTX
68 + - description: RTC Oscillator (32.768 kHz)
80 + - const: gmac0_gtxclk
86 + - const: gmac0_rmii_refin
87 + - const: gmac0_rgmii_rxin
90 + - const: gmac0_gtxclk
96 + See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
101 + See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
111 +additionalProperties: false
115 + #include <dt-bindings/clock/starfive,jh7110-crg.h>
117 + clock-controller@17000000 {
118 + compatible = "starfive,jh7110-aoncrg";
119 + reg = <0x17000000 0x10000>;
120 + clocks = <&osc>, <&gmac0_rmii_refin>,
121 + <&gmac0_rgmii_rxin>,
122 + <&syscrg JH7110_SYSCLK_STG_AXIAHB>,
123 + <&syscrg JH7110_SYSCLK_APB_BUS>,
124 + <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>,
126 + clock-names = "osc", "gmac0_rmii_refin",
127 + "gmac0_rgmii_rxin", "stg_axiahb",
128 + "apb_bus", "gmac0_gtxclk",
130 + #clock-cells = <1>;
131 + #reset-cells = <1>;
133 --- a/include/dt-bindings/clock/starfive,jh7110-crg.h
134 +++ b/include/dt-bindings/clock/starfive,jh7110-crg.h
137 #define JH7110_SYSCLK_END 190
140 +#define JH7110_AONCLK_OSC_DIV4 0
141 +#define JH7110_AONCLK_APB_FUNC 1
142 +#define JH7110_AONCLK_GMAC0_AHB 2
143 +#define JH7110_AONCLK_GMAC0_AXI 3
144 +#define JH7110_AONCLK_GMAC0_RMII_RTX 4
145 +#define JH7110_AONCLK_GMAC0_TX 5
146 +#define JH7110_AONCLK_GMAC0_TX_INV 6
147 +#define JH7110_AONCLK_GMAC0_RX 7
148 +#define JH7110_AONCLK_GMAC0_RX_INV 8
149 +#define JH7110_AONCLK_OTPC_APB 9
150 +#define JH7110_AONCLK_RTC_APB 10
151 +#define JH7110_AONCLK_RTC_INTERNAL 11
152 +#define JH7110_AONCLK_RTC_32K 12
153 +#define JH7110_AONCLK_RTC_CAL 13
155 +#define JH7110_AONCLK_END 14
157 #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ */
158 --- a/include/dt-bindings/reset/starfive,jh7110-crg.h
159 +++ b/include/dt-bindings/reset/starfive,jh7110-crg.h
162 #define JH7110_SYSRST_END 126
165 +#define JH7110_AONRST_GMAC0_AXI 0
166 +#define JH7110_AONRST_GMAC0_AHB 1
167 +#define JH7110_AONRST_IOMUX 2
168 +#define JH7110_AONRST_PMU_APB 3
169 +#define JH7110_AONRST_PMU_WKUP 4
170 +#define JH7110_AONRST_RTC_APB 5
171 +#define JH7110_AONRST_RTC_CAL 6
172 +#define JH7110_AONRST_RTC_32K 7
174 +#define JH7110_AONRST_END 8
176 #endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ */