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starfive: add new target for StarFive JH7100/7110 SoC
[openwrt/staging/981213.git] / target / linux / starfive / patches-6.1 / 0023-riscv-dts-starfive-Add-StarFive-JH7110-VisionFive-2-.patch
1 From 76bc84c399f11c7d6a37fe68cbd5f182e4c18369 Mon Sep 17 00:00:00 2001
2 From: Emil Renner Berthing <kernel@esmil.dk>
3 Date: Sat, 1 Apr 2023 19:19:33 +0800
4 Subject: [PATCH 023/122] riscv: dts: starfive: Add StarFive JH7110 VisionFive
5 2 board device tree
6
7 Add a minimal device tree for StarFive JH7110 VisionFive 2 board
8 which has version A and version B. Support booting and basic
9 clock/reset/pinctrl/uart drivers.
10
11 Tested-by: Tommaso Merciai <tomm.merciai@gmail.com>
12 Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
13 Acked-by: Conor Dooley <conor.dooley@microchip.com>
14 Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
15 Co-developed-by: Jianlong Huang <jianlong.huang@starfivetech.com>
16 Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
17 Co-developed-by: Hal Feng <hal.feng@starfivetech.com>
18 Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
19 Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
20 Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
21 ---
22 arch/riscv/boot/dts/starfive/Makefile | 6 +-
23 .../jh7110-starfive-visionfive-2-v1.2a.dts | 13 ++
24 .../jh7110-starfive-visionfive-2-v1.3b.dts | 13 ++
25 .../jh7110-starfive-visionfive-2.dtsi | 215 ++++++++++++++++++
26 4 files changed, 246 insertions(+), 1 deletion(-)
27 create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts
28 create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts
29 create mode 100644 arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
30
31 --- a/arch/riscv/boot/dts/starfive/Makefile
32 +++ b/arch/riscv/boot/dts/starfive/Makefile
33 @@ -1,2 +1,6 @@
34 # SPDX-License-Identifier: GPL-2.0
35 -dtb-$(CONFIG_SOC_STARFIVE) += jh7100-beaglev-starlight.dtb
36 +dtb-$(CONFIG_ARCH_STARFIVE) += jh7100-beaglev-starlight.dtb
37 +dtb-$(CONFIG_ARCH_STARFIVE) += jh7100-starfive-visionfive-v1.dtb
38 +
39 +dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.2a.dtb
40 +dtb-$(CONFIG_ARCH_STARFIVE) += jh7110-starfive-visionfive-2-v1.3b.dtb
41 --- /dev/null
42 +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts
43 @@ -0,0 +1,13 @@
44 +// SPDX-License-Identifier: GPL-2.0 OR MIT
45 +/*
46 + * Copyright (C) 2022 StarFive Technology Co., Ltd.
47 + * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
48 + */
49 +
50 +/dts-v1/;
51 +#include "jh7110-starfive-visionfive-2.dtsi"
52 +
53 +/ {
54 + model = "StarFive VisionFive 2 v1.2A";
55 + compatible = "starfive,visionfive-2-v1.2a", "starfive,jh7110";
56 +};
57 --- /dev/null
58 +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts
59 @@ -0,0 +1,13 @@
60 +// SPDX-License-Identifier: GPL-2.0 OR MIT
61 +/*
62 + * Copyright (C) 2022 StarFive Technology Co., Ltd.
63 + * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
64 + */
65 +
66 +/dts-v1/;
67 +#include "jh7110-starfive-visionfive-2.dtsi"
68 +
69 +/ {
70 + model = "StarFive VisionFive 2 v1.3B";
71 + compatible = "starfive,visionfive-2-v1.3b", "starfive,jh7110";
72 +};
73 --- /dev/null
74 +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
75 @@ -0,0 +1,215 @@
76 +// SPDX-License-Identifier: GPL-2.0 OR MIT
77 +/*
78 + * Copyright (C) 2022 StarFive Technology Co., Ltd.
79 + * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
80 + */
81 +
82 +/dts-v1/;
83 +#include "jh7110.dtsi"
84 +#include "jh7110-pinfunc.h"
85 +#include <dt-bindings/gpio/gpio.h>
86 +
87 +/ {
88 + aliases {
89 + i2c0 = &i2c0;
90 + i2c2 = &i2c2;
91 + i2c5 = &i2c5;
92 + i2c6 = &i2c6;
93 + serial0 = &uart0;
94 + };
95 +
96 + chosen {
97 + stdout-path = "serial0:115200n8";
98 + };
99 +
100 + cpus {
101 + timebase-frequency = <4000000>;
102 + };
103 +
104 + memory@40000000 {
105 + device_type = "memory";
106 + reg = <0x0 0x40000000 0x1 0x0>;
107 + };
108 +
109 + gpio-restart {
110 + compatible = "gpio-restart";
111 + gpios = <&sysgpio 35 GPIO_ACTIVE_HIGH>;
112 + priority = <224>;
113 + };
114 +};
115 +
116 +&gmac0_rgmii_rxin {
117 + clock-frequency = <125000000>;
118 +};
119 +
120 +&gmac0_rmii_refin {
121 + clock-frequency = <50000000>;
122 +};
123 +
124 +&gmac1_rgmii_rxin {
125 + clock-frequency = <125000000>;
126 +};
127 +
128 +&gmac1_rmii_refin {
129 + clock-frequency = <50000000>;
130 +};
131 +
132 +&i2srx_bclk_ext {
133 + clock-frequency = <12288000>;
134 +};
135 +
136 +&i2srx_lrck_ext {
137 + clock-frequency = <192000>;
138 +};
139 +
140 +&i2stx_bclk_ext {
141 + clock-frequency = <12288000>;
142 +};
143 +
144 +&i2stx_lrck_ext {
145 + clock-frequency = <192000>;
146 +};
147 +
148 +&mclk_ext {
149 + clock-frequency = <12288000>;
150 +};
151 +
152 +&osc {
153 + clock-frequency = <24000000>;
154 +};
155 +
156 +&rtc_osc {
157 + clock-frequency = <32768>;
158 +};
159 +
160 +&tdm_ext {
161 + clock-frequency = <49152000>;
162 +};
163 +
164 +&i2c0 {
165 + clock-frequency = <100000>;
166 + i2c-sda-hold-time-ns = <300>;
167 + i2c-sda-falling-time-ns = <510>;
168 + i2c-scl-falling-time-ns = <510>;
169 + pinctrl-names = "default";
170 + pinctrl-0 = <&i2c0_pins>;
171 + status = "okay";
172 +};
173 +
174 +&i2c2 {
175 + clock-frequency = <100000>;
176 + i2c-sda-hold-time-ns = <300>;
177 + i2c-sda-falling-time-ns = <510>;
178 + i2c-scl-falling-time-ns = <510>;
179 + pinctrl-names = "default";
180 + pinctrl-0 = <&i2c2_pins>;
181 + status = "okay";
182 +};
183 +
184 +&i2c5 {
185 + clock-frequency = <100000>;
186 + i2c-sda-hold-time-ns = <300>;
187 + i2c-sda-falling-time-ns = <510>;
188 + i2c-scl-falling-time-ns = <510>;
189 + pinctrl-names = "default";
190 + pinctrl-0 = <&i2c5_pins>;
191 + status = "okay";
192 +};
193 +
194 +&i2c6 {
195 + clock-frequency = <100000>;
196 + i2c-sda-hold-time-ns = <300>;
197 + i2c-sda-falling-time-ns = <510>;
198 + i2c-scl-falling-time-ns = <510>;
199 + pinctrl-names = "default";
200 + pinctrl-0 = <&i2c6_pins>;
201 + status = "okay";
202 +};
203 +
204 +&sysgpio {
205 + i2c0_pins: i2c0-0 {
206 + i2c-pins {
207 + pinmux = <GPIOMUX(57, GPOUT_LOW,
208 + GPOEN_SYS_I2C0_CLK,
209 + GPI_SYS_I2C0_CLK)>,
210 + <GPIOMUX(58, GPOUT_LOW,
211 + GPOEN_SYS_I2C0_DATA,
212 + GPI_SYS_I2C0_DATA)>;
213 + bias-disable; /* external pull-up */
214 + input-enable;
215 + input-schmitt-enable;
216 + };
217 + };
218 +
219 + i2c2_pins: i2c2-0 {
220 + i2c-pins {
221 + pinmux = <GPIOMUX(3, GPOUT_LOW,
222 + GPOEN_SYS_I2C2_CLK,
223 + GPI_SYS_I2C2_CLK)>,
224 + <GPIOMUX(2, GPOUT_LOW,
225 + GPOEN_SYS_I2C2_DATA,
226 + GPI_SYS_I2C2_DATA)>;
227 + bias-disable; /* external pull-up */
228 + input-enable;
229 + input-schmitt-enable;
230 + };
231 + };
232 +
233 + i2c5_pins: i2c5-0 {
234 + i2c-pins {
235 + pinmux = <GPIOMUX(19, GPOUT_LOW,
236 + GPOEN_SYS_I2C5_CLK,
237 + GPI_SYS_I2C5_CLK)>,
238 + <GPIOMUX(20, GPOUT_LOW,
239 + GPOEN_SYS_I2C5_DATA,
240 + GPI_SYS_I2C5_DATA)>;
241 + bias-disable; /* external pull-up */
242 + input-enable;
243 + input-schmitt-enable;
244 + };
245 + };
246 +
247 + i2c6_pins: i2c6-0 {
248 + i2c-pins {
249 + pinmux = <GPIOMUX(16, GPOUT_LOW,
250 + GPOEN_SYS_I2C6_CLK,
251 + GPI_SYS_I2C6_CLK)>,
252 + <GPIOMUX(17, GPOUT_LOW,
253 + GPOEN_SYS_I2C6_DATA,
254 + GPI_SYS_I2C6_DATA)>;
255 + bias-disable; /* external pull-up */
256 + input-enable;
257 + input-schmitt-enable;
258 + };
259 + };
260 +
261 + uart0_pins: uart0-0 {
262 + tx-pins {
263 + pinmux = <GPIOMUX(5, GPOUT_SYS_UART0_TX,
264 + GPOEN_ENABLE,
265 + GPI_NONE)>;
266 + bias-disable;
267 + drive-strength = <12>;
268 + input-disable;
269 + input-schmitt-disable;
270 + slew-rate = <0>;
271 + };
272 +
273 + rx-pins {
274 + pinmux = <GPIOMUX(6, GPOUT_LOW,
275 + GPOEN_DISABLE,
276 + GPI_SYS_UART0_RX)>;
277 + bias-disable; /* external pull-up */
278 + drive-strength = <2>;
279 + input-enable;
280 + input-schmitt-enable;
281 + slew-rate = <0>;
282 + };
283 + };
284 +};
285 +
286 +&uart0 {
287 + pinctrl-names = "default";
288 + pinctrl-0 = <&uart0_pins>;
289 + status = "okay";
290 +};
Staging tree of Chuanhong Guo