target/linux/starfive/patches-6.1/0052-clk-starfive-Add-StarFive-JH7110-System-Top-Group-cl.patch

   1 From 9a02d66b0515d987037d0229b99367412b9eb38c Mon Sep 17 00:00:00 2001
   2 From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
   3 Date: Thu, 18 May 2023 18:12:25 +0800
   4 Subject: [PATCH 052/122] clk: starfive: Add StarFive JH7110 System-Top-Group
   5  clock driver
   6
   7 Add driver for the StarFive JH7110 System-Top-Group clock controller.
   8
   9 Co-developed-by: Xingyu Wu <xingyu.wu@starfivetech.com>
  10 Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
  11 Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
  12 ---
  13  drivers/clk/starfive/Kconfig                  |  11 ++
  14  drivers/clk/starfive/Makefile                 |   1 +
  15  .../clk/starfive/clk-starfive-jh7110-stg.c    | 173 ++++++++++++++++++
  16  3 files changed, 185 insertions(+)
  17  create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-stg.c
  18
  19 --- a/drivers/clk/starfive/Kconfig
  20 +++ b/drivers/clk/starfive/Kconfig
  21 @@ -51,3 +51,14 @@ config CLK_STARFIVE_JH7110_AON
  22         help
  23           Say yes here to support the always-on clock controller on the
  24           StarFive JH7110 SoC.
  25 +
  26 +config CLK_STARFIVE_JH7110_STG
  27 +       tristate "StarFive JH7110 System-Top-Group clock support"
  28 +       depends on CLK_STARFIVE_JH7110_SYS
  29 +       select AUXILIARY_BUS
  30 +       select CLK_STARFIVE_JH71X0
  31 +       select RESET_STARFIVE_JH7110
  32 +       default m if ARCH_STARFIVE
  33 +       help
  34 +         Say yes here to support the System-Top-Group clock controller
  35 +         on the StarFive JH7110 SoC.
  36 --- a/drivers/clk/starfive/Makefile
  37 +++ b/drivers/clk/starfive/Makefile
  38 @@ -7,3 +7,4 @@ obj-$(CONFIG_CLK_STARFIVE_JH7100_AUDIO)
  39  obj-$(CONFIG_CLK_STARFIVE_JH7110_PLL)  += clk-starfive-jh7110-pll.o
  40  obj-$(CONFIG_CLK_STARFIVE_JH7110_SYS)  += clk-starfive-jh7110-sys.o
  41  obj-$(CONFIG_CLK_STARFIVE_JH7110_AON)  += clk-starfive-jh7110-aon.o
  42 +obj-$(CONFIG_CLK_STARFIVE_JH7110_STG)  += clk-starfive-jh7110-stg.o
  43 --- /dev/null
  44 +++ b/drivers/clk/starfive/clk-starfive-jh7110-stg.c
  45 @@ -0,0 +1,173 @@
  46 +// SPDX-License-Identifier: GPL-2.0
  47 +/*
  48 + * StarFive JH7110 System-Top-Group Clock Driver
  49 + *
  50 + * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
  51 + * Copyright (C) 2022 StarFive Technology Co., Ltd.
  52 + */
  53 +
  54 +#include <linux/clk-provider.h>
  55 +#include <linux/io.h>
  56 +#include <linux/platform_device.h>
  57 +
  58 +#include <dt-bindings/clock/starfive,jh7110-crg.h>
  59 +
  60 +#include "clk-starfive-jh7110.h"
  61 +
  62 +/* external clocks */
  63 +#define JH7110_STGCLK_OSC                      (JH7110_STGCLK_END + 0)
  64 +#define JH7110_STGCLK_HIFI4_CORE               (JH7110_STGCLK_END + 1)
  65 +#define JH7110_STGCLK_STG_AXIAHB               (JH7110_STGCLK_END + 2)
  66 +#define JH7110_STGCLK_USB_125M                 (JH7110_STGCLK_END + 3)
  67 +#define JH7110_STGCLK_CPU_BUS                  (JH7110_STGCLK_END + 4)
  68 +#define JH7110_STGCLK_HIFI4_AXI                        (JH7110_STGCLK_END + 5)
  69 +#define JH7110_STGCLK_NOCSTG_BUS               (JH7110_STGCLK_END + 6)
  70 +#define JH7110_STGCLK_APB_BUS                  (JH7110_STGCLK_END + 7)
  71 +#define JH7110_STGCLK_EXT_END                  (JH7110_STGCLK_END + 8)
  72 +
  73 +static const struct jh71x0_clk_data jh7110_stgclk_data[] = {
  74 +       /* hifi4 */
  75 +       JH71X0_GATE(JH7110_STGCLK_HIFI4_CLK_CORE, "hifi4_clk_core", 0,
  76 +                   JH7110_STGCLK_HIFI4_CORE),
  77 +       /* usb */
  78 +       JH71X0_GATE(JH7110_STGCLK_USB0_APB, "usb0_apb", 0, JH7110_STGCLK_APB_BUS),
  79 +       JH71X0_GATE(JH7110_STGCLK_USB0_UTMI_APB, "usb0_utmi_apb", 0, JH7110_STGCLK_APB_BUS),
  80 +       JH71X0_GATE(JH7110_STGCLK_USB0_AXI, "usb0_axi", 0, JH7110_STGCLK_STG_AXIAHB),
  81 +       JH71X0_GDIV(JH7110_STGCLK_USB0_LPM, "usb0_lpm", 0, 2, JH7110_STGCLK_OSC),
  82 +       JH71X0_GDIV(JH7110_STGCLK_USB0_STB, "usb0_stb", 0, 4, JH7110_STGCLK_OSC),
  83 +       JH71X0_GATE(JH7110_STGCLK_USB0_APP_125, "usb0_app_125", 0, JH7110_STGCLK_USB_125M),
  84 +       JH71X0__DIV(JH7110_STGCLK_USB0_REFCLK, "usb0_refclk", 2, JH7110_STGCLK_OSC),
  85 +       /* pci-e */
  86 +       JH71X0_GATE(JH7110_STGCLK_PCIE0_AXI_MST0, "pcie0_axi_mst0", 0,
  87 +                   JH7110_STGCLK_STG_AXIAHB),
  88 +       JH71X0_GATE(JH7110_STGCLK_PCIE0_APB, "pcie0_apb", 0, JH7110_STGCLK_APB_BUS),
  89 +       JH71X0_GATE(JH7110_STGCLK_PCIE0_TL, "pcie0_tl", 0, JH7110_STGCLK_STG_AXIAHB),
  90 +       JH71X0_GATE(JH7110_STGCLK_PCIE1_AXI_MST0, "pcie1_axi_mst0", 0,
  91 +                   JH7110_STGCLK_STG_AXIAHB),
  92 +       JH71X0_GATE(JH7110_STGCLK_PCIE1_APB, "pcie1_apb", 0, JH7110_STGCLK_APB_BUS),
  93 +       JH71X0_GATE(JH7110_STGCLK_PCIE1_TL, "pcie1_tl", 0, JH7110_STGCLK_STG_AXIAHB),
  94 +       JH71X0_GATE(JH7110_STGCLK_PCIE_SLV_MAIN, "pcie_slv_main", CLK_IS_CRITICAL,
  95 +                   JH7110_STGCLK_STG_AXIAHB),
  96 +       /* security */
  97 +       JH71X0_GATE(JH7110_STGCLK_SEC_AHB, "sec_ahb", 0, JH7110_STGCLK_STG_AXIAHB),
  98 +       JH71X0_GATE(JH7110_STGCLK_SEC_MISC_AHB, "sec_misc_ahb", 0, JH7110_STGCLK_STG_AXIAHB),
  99 +       /* stg mtrx */
 100 +       JH71X0_GATE(JH7110_STGCLK_GRP0_MAIN, "mtrx_grp0_main", CLK_IS_CRITICAL,
 101 +                   JH7110_STGCLK_CPU_BUS),
 102 +       JH71X0_GATE(JH7110_STGCLK_GRP0_BUS, "mtrx_grp0_bus", CLK_IS_CRITICAL,
 103 +                   JH7110_STGCLK_NOCSTG_BUS),
 104 +       JH71X0_GATE(JH7110_STGCLK_GRP0_STG, "mtrx_grp0_stg", CLK_IS_CRITICAL,
 105 +                   JH7110_STGCLK_STG_AXIAHB),
 106 +       JH71X0_GATE(JH7110_STGCLK_GRP1_MAIN, "mtrx_grp1_main", CLK_IS_CRITICAL,
 107 +                   JH7110_STGCLK_CPU_BUS),
 108 +       JH71X0_GATE(JH7110_STGCLK_GRP1_BUS, "mtrx_grp1_bus", CLK_IS_CRITICAL,
 109 +                   JH7110_STGCLK_NOCSTG_BUS),
 110 +       JH71X0_GATE(JH7110_STGCLK_GRP1_STG, "mtrx_grp1_stg", CLK_IS_CRITICAL,
 111 +                   JH7110_STGCLK_STG_AXIAHB),
 112 +       JH71X0_GATE(JH7110_STGCLK_GRP1_HIFI, "mtrx_grp1_hifi", CLK_IS_CRITICAL,
 113 +                   JH7110_STGCLK_HIFI4_AXI),
 114 +       /* e24_rvpi */
 115 +       JH71X0_GDIV(JH7110_STGCLK_E2_RTC, "e2_rtc", 0, 24, JH7110_STGCLK_OSC),
 116 +       JH71X0_GATE(JH7110_STGCLK_E2_CORE, "e2_core", 0, JH7110_STGCLK_STG_AXIAHB),
 117 +       JH71X0_GATE(JH7110_STGCLK_E2_DBG, "e2_dbg", 0, JH7110_STGCLK_STG_AXIAHB),
 118 +       /* dw_sgdma1p */
 119 +       JH71X0_GATE(JH7110_STGCLK_DMA1P_AXI, "dma1p_axi", 0, JH7110_STGCLK_STG_AXIAHB),
 120 +       JH71X0_GATE(JH7110_STGCLK_DMA1P_AHB, "dma1p_ahb", 0, JH7110_STGCLK_STG_AXIAHB),
 121 +};
 122 +
 123 +static struct clk_hw *jh7110_stgclk_get(struct of_phandle_args *clkspec, void *data)
 124 +{
 125 +       struct jh71x0_clk_priv *priv = data;
 126 +       unsigned int idx = clkspec->args[0];
 127 +
 128 +       if (idx < JH7110_STGCLK_END)
 129 +               return &priv->reg[idx].hw;
 130 +
 131 +       return ERR_PTR(-EINVAL);
 132 +}
 133 +
 134 +static int jh7110_stgcrg_probe(struct platform_device *pdev)
 135 +{
 136 +       struct jh71x0_clk_priv *priv;
 137 +       unsigned int idx;
 138 +       int ret;
 139 +
 140 +       priv = devm_kzalloc(&pdev->dev, struct_size(priv, reg, JH7110_STGCLK_END),
 141 +                           GFP_KERNEL);
 142 +       if (!priv)
 143 +               return -ENOMEM;
 144 +
 145 +       spin_lock_init(&priv->rmw_lock);
 146 +       priv->dev = &pdev->dev;
 147 +       priv->base = devm_platform_ioremap_resource(pdev, 0);
 148 +       if (IS_ERR(priv->base))
 149 +               return PTR_ERR(priv->base);
 150 +
 151 +       for (idx = 0; idx < JH7110_STGCLK_END; idx++) {
 152 +               u32 max = jh7110_stgclk_data[idx].max;
 153 +               struct clk_parent_data parents[4] = {};
 154 +               struct clk_init_data init = {
 155 +                       .name = jh7110_stgclk_data[idx].name,
 156 +                       .ops = starfive_jh71x0_clk_ops(max),
 157 +                       .parent_data = parents,
 158 +                       .num_parents =
 159 +                               ((max & JH71X0_CLK_MUX_MASK) >> JH71X0_CLK_MUX_SHIFT) + 1,
 160 +                       .flags = jh7110_stgclk_data[idx].flags,
 161 +               };
 162 +               struct jh71x0_clk *clk = &priv->reg[idx];
 163 +               const char *fw_name[JH7110_STGCLK_EXT_END - JH7110_STGCLK_END] = {
 164 +                       "osc",
 165 +                       "hifi4_core",
 166 +                       "stg_axiahb",
 167 +                       "usb_125m",
 168 +                       "cpu_bus",
 169 +                       "hifi4_axi",
 170 +                       "nocstg_bus",
 171 +                       "apb_bus"
 172 +               };
 173 +               unsigned int i;
 174 +
 175 +               for (i = 0; i < init.num_parents; i++) {
 176 +                       unsigned int pidx = jh7110_stgclk_data[idx].parents[i];
 177 +
 178 +                       if (pidx < JH7110_STGCLK_END)
 179 +                               parents[i].hw = &priv->reg[pidx].hw;
 180 +                       else if (pidx < JH7110_STGCLK_EXT_END)
 181 +                               parents[i].fw_name = fw_name[pidx - JH7110_STGCLK_END];
 182 +               }
 183 +
 184 +               clk->hw.init = &init;
 185 +               clk->idx = idx;
 186 +               clk->max_div = max & JH71X0_CLK_DIV_MASK;
 187 +
 188 +               ret = devm_clk_hw_register(&pdev->dev, &clk->hw);
 189 +               if (ret)
 190 +                       return ret;
 191 +       }
 192 +
 193 +       ret = devm_of_clk_add_hw_provider(&pdev->dev, jh7110_stgclk_get, priv);
 194 +       if (ret)
 195 +               return ret;
 196 +
 197 +       return jh7110_reset_controller_register(priv, "rst-stg", 2);
 198 +}
 199 +
 200 +static const struct of_device_id jh7110_stgcrg_match[] = {
 201 +       { .compatible = "starfive,jh7110-stgcrg" },
 202 +       { /* sentinel */ }
 203 +};
 204 +MODULE_DEVICE_TABLE(of, jh7110_stgcrg_match);
 205 +
 206 +static struct platform_driver jh7110_stgcrg_driver = {
 207 +       .probe = jh7110_stgcrg_probe,
 208 +       .driver = {
 209 +               .name = "clk-starfive-jh7110-stg",
 210 +               .of_match_table = jh7110_stgcrg_match,
 211 +       },
 212 +};
 213 +module_platform_driver(jh7110_stgcrg_driver);
 214 +
 215 +MODULE_AUTHOR("Xingyu Wu <xingyu.wu@starfivetech.com>");
 216 +MODULE_AUTHOR("Emil Renner Berthing <kernel@esmil.dk>");
 217 +MODULE_DESCRIPTION("StarFive JH7110 System-Top-Group clock driver");
 218 +MODULE_LICENSE("GPL");