target/linux/starfive/patches-6.1/0055-dt-bindings-clock-Add-StarFive-JH7110-Video-Output-c.patch

   1 From 06fa910083f37ecbc9234c7230dcbbd4d83e2f02 Mon Sep 17 00:00:00 2001
   2 From: Xingyu Wu <xingyu.wu@starfivetech.com>
   3 Date: Thu, 18 May 2023 18:12:28 +0800
   4 Subject: [PATCH 055/122] dt-bindings: clock: Add StarFive JH7110 Video-Output
   5  clock and reset generator
   6
   7 Add bindings for the Video-Output clock and reset generator (VOUTCRG)
   8 on the JH7110 RISC-V SoC by StarFive Ltd.
   9
  10 Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
  11 Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
  12 ---
  13  .../clock/starfive,jh7110-voutcrg.yaml        | 90 +++++++++++++++++++
  14  .../dt-bindings/clock/starfive,jh7110-crg.h   | 22 +++++
  15  .../dt-bindings/reset/starfive,jh7110-crg.h   | 16 ++++
  16  3 files changed, 128 insertions(+)
  17  create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-voutcrg.yaml
  18
  19 --- /dev/null
  20 +++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-voutcrg.yaml
  21 @@ -0,0 +1,90 @@
  22 +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
  23 +%YAML 1.2
  24 +---
  25 +$id: http://devicetree.org/schemas/clock/starfive,jh7110-voutcrg.yaml#
  26 +$schema: http://devicetree.org/meta-schemas/core.yaml#
  27 +
  28 +title: StarFive JH7110 Video-Output Clock and Reset Generator
  29 +
  30 +maintainers:
  31 +  - Xingyu Wu <xingyu.wu@starfivetech.com>
  32 +
  33 +properties:
  34 +  compatible:
  35 +    const: starfive,jh7110-voutcrg
  36 +
  37 +  reg:
  38 +    maxItems: 1
  39 +
  40 +  clocks:
  41 +    items:
  42 +      - description: Vout Top core
  43 +      - description: Vout Top Ahb
  44 +      - description: Vout Top Axi
  45 +      - description: Vout Top HDMI MCLK
  46 +      - description: I2STX0 BCLK
  47 +      - description: external HDMI pixel
  48 +
  49 +  clock-names:
  50 +    items:
  51 +      - const: vout_src
  52 +      - const: vout_top_ahb
  53 +      - const: vout_top_axi
  54 +      - const: vout_top_hdmitx0_mclk
  55 +      - const: i2stx0_bclk
  56 +      - const: hdmitx0_pixelclk
  57 +
  58 +  resets:
  59 +    maxItems: 1
  60 +    description: Vout Top core
  61 +
  62 +  '#clock-cells':
  63 +    const: 1
  64 +    description:
  65 +      See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
  66 +
  67 +  '#reset-cells':
  68 +    const: 1
  69 +    description:
  70 +      See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
  71 +
  72 +  power-domains:
  73 +    maxItems: 1
  74 +    description:
  75 +      Vout domain power
  76 +
  77 +required:
  78 +  - compatible
  79 +  - reg
  80 +  - clocks
  81 +  - clock-names
  82 +  - resets
  83 +  - '#clock-cells'
  84 +  - '#reset-cells'
  85 +  - power-domains
  86 +
  87 +additionalProperties: false
  88 +
  89 +examples:
  90 +  - |
  91 +    #include <dt-bindings/clock/starfive,jh7110-crg.h>
  92 +    #include <dt-bindings/power/starfive,jh7110-pmu.h>
  93 +    #include <dt-bindings/reset/starfive,jh7110-crg.h>
  94 +
  95 +    voutcrg: clock-controller@295C0000 {
  96 +        compatible = "starfive,jh7110-voutcrg";
  97 +        reg = <0x295C0000 0x10000>;
  98 +        clocks = <&syscrg JH7110_SYSCLK_VOUT_SRC>,
  99 +                 <&syscrg JH7110_SYSCLK_VOUT_TOP_AHB>,
 100 +                 <&syscrg JH7110_SYSCLK_VOUT_TOP_AXI>,
 101 +                 <&syscrg JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK>,
 102 +                 <&syscrg JH7110_SYSCLK_I2STX0_BCLK>,
 103 +                 <&hdmitx0_pixelclk>;
 104 +        clock-names = "vout_src", "vout_top_ahb",
 105 +                      "vout_top_axi", "vout_top_hdmitx0_mclk",
 106 +                      "i2stx0_bclk", "hdmitx0_pixelclk";
 107 +        resets = <&syscrg JH7110_SYSRST_VOUT_TOP_SRC>;
 108 +        #clock-cells = <1>;
 109 +        #reset-cells = <1>;
 110 +        power-domains = <&pwrc JH7110_PD_VOUT>;
 111 +    };
 112 --- a/include/dt-bindings/clock/starfive,jh7110-crg.h
 113 +++ b/include/dt-bindings/clock/starfive,jh7110-crg.h
 114 @@ -276,4 +276,26 @@
 115
 116  #define JH7110_ISPCLK_END                      14
 117
 118 +/* VOUTCRG clocks */
 119 +#define JH7110_VOUTCLK_APB                     0
 120 +#define JH7110_VOUTCLK_DC8200_PIX              1
 121 +#define JH7110_VOUTCLK_DSI_SYS                 2
 122 +#define JH7110_VOUTCLK_TX_ESC                  3
 123 +#define JH7110_VOUTCLK_DC8200_AXI              4
 124 +#define JH7110_VOUTCLK_DC8200_CORE             5
 125 +#define JH7110_VOUTCLK_DC8200_AHB              6
 126 +#define JH7110_VOUTCLK_DC8200_PIX0             7
 127 +#define JH7110_VOUTCLK_DC8200_PIX1             8
 128 +#define JH7110_VOUTCLK_DOM_VOUT_TOP_LCD                9
 129 +#define JH7110_VOUTCLK_DSITX_APB               10
 130 +#define JH7110_VOUTCLK_DSITX_SYS               11
 131 +#define JH7110_VOUTCLK_DSITX_DPI               12
 132 +#define JH7110_VOUTCLK_DSITX_TXESC             13
 133 +#define JH7110_VOUTCLK_MIPITX_DPHY_TXESC       14
 134 +#define JH7110_VOUTCLK_HDMI_TX_MCLK            15
 135 +#define JH7110_VOUTCLK_HDMI_TX_BCLK            16
 136 +#define JH7110_VOUTCLK_HDMI_TX_SYS             17
 137 +
 138 +#define JH7110_VOUTCLK_END                     18
 139 +
 140  #endif /* __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__ */
 141 --- a/include/dt-bindings/reset/starfive,jh7110-crg.h
 142 +++ b/include/dt-bindings/reset/starfive,jh7110-crg.h
 143 @@ -195,4 +195,20 @@
 144
 145  #define JH7110_ISPRST_END                      12
 146
 147 +/* VOUTCRG resets */
 148 +#define JH7110_VOUTRST_DC8200_AXI              0
 149 +#define JH7110_VOUTRST_DC8200_AHB              1
 150 +#define JH7110_VOUTRST_DC8200_CORE             2
 151 +#define JH7110_VOUTRST_DSITX_DPI               3
 152 +#define JH7110_VOUTRST_DSITX_APB               4
 153 +#define JH7110_VOUTRST_DSITX_RXESC             5
 154 +#define JH7110_VOUTRST_DSITX_SYS               6
 155 +#define JH7110_VOUTRST_DSITX_TXBYTEHS          7
 156 +#define JH7110_VOUTRST_DSITX_TXESC             8
 157 +#define JH7110_VOUTRST_HDMI_TX_HDMI            9
 158 +#define JH7110_VOUTRST_MIPITX_DPHY_SYS         10
 159 +#define JH7110_VOUTRST_MIPITX_DPHY_TXBYTEHS    11
 160 +
 161 +#define JH7110_VOUTRST_END                     12
 162 +
 163  #endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_CRG_H__ */