starfive: add new target for StarFive JH7100/7110 SoC
[openwrt/staging/981213.git] / target / linux / starfive / patches-6.1 / 0062-dt-bindings-PWM-Add-StarFive-PWM-module.patch
1 From 99f0bf43994dada29e33fd8718fd25484634da3a Mon Sep 17 00:00:00 2001
2 From: William Qiu <william.qiu@starfivetech.com>
3 Date: Tue, 21 Mar 2023 13:52:27 +0800
4 Subject: [PATCH 062/122] dt-bindings: PWM: Add StarFive PWM module
5
6 Add documentation to describe StarFive Pulse Width Modulation
7 controller driver.
8
9 Signed-off-by: William Qiu <william.qiu@starfivetech.com>
10 Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
11 ---
12 .../bindings/pwm/starfive,jh7110-pwm.yaml | 53 +++++++++++++++++++
13 1 file changed, 53 insertions(+)
14 create mode 100644 Documentation/devicetree/bindings/pwm/starfive,jh7110-pwm.yaml
15
16 --- /dev/null
17 +++ b/Documentation/devicetree/bindings/pwm/starfive,jh7110-pwm.yaml
18 @@ -0,0 +1,53 @@
19 +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
20 +%YAML 1.2
21 +---
22 +$id: http://devicetree.org/schemas/pwm/starfive,jh7110-pwm.yaml#
23 +$schema: http://devicetree.org/meta-schemas/core.yaml#
24 +
25 +title: StarFive PWM controller
26 +
27 +maintainers:
28 + - William Qiu <william.qiu@starfivetech.com>
29 +
30 +description:
31 + StarFive SoCs contain PWM and when operating in PWM mode, the PTC core generates
32 + binary signal with user-programmable low and high periods. Clock source for the
33 + PWM can be either system clockor external clock. Each PWM timer block provides 8
34 + PWM channels.
35 +
36 +allOf:
37 + - $ref: pwm.yaml#
38 +
39 +properties:
40 + compatible:
41 + const: starfive,jh7110-pwm
42 +
43 + reg:
44 + maxItems: 1
45 +
46 + clocks:
47 + maxItems: 1
48 +
49 + resets:
50 + maxItems: 1
51 +
52 + "#pwm-cells":
53 + const: 3
54 +
55 +required:
56 + - compatible
57 + - reg
58 + - clocks
59 + - resets
60 +
61 +additionalProperties: false
62 +
63 +examples:
64 + - |
65 + pwm@120d0000 {
66 + compatible = "starfive,jh7110-pwm";
67 + reg = <0x120d0000 0x10000>;
68 + clocks = <&syscrg 121>;
69 + resets = <&syscrg 108>;
70 + #pwm-cells = <3>;
71 + };