1 From 99f0bf43994dada29e33fd8718fd25484634da3a Mon Sep 17 00:00:00 2001
2 From: William Qiu <william.qiu@starfivetech.com>
3 Date: Tue, 21 Mar 2023 13:52:27 +0800
4 Subject: [PATCH 062/122] dt-bindings: PWM: Add StarFive PWM module
6 Add documentation to describe StarFive Pulse Width Modulation
9 Signed-off-by: William Qiu <william.qiu@starfivetech.com>
10 Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
12 .../bindings/pwm/starfive,jh7110-pwm.yaml | 53 +++++++++++++++++++
13 1 file changed, 53 insertions(+)
14 create mode 100644 Documentation/devicetree/bindings/pwm/starfive,jh7110-pwm.yaml
17 +++ b/Documentation/devicetree/bindings/pwm/starfive,jh7110-pwm.yaml
19 +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
22 +$id: http://devicetree.org/schemas/pwm/starfive,jh7110-pwm.yaml#
23 +$schema: http://devicetree.org/meta-schemas/core.yaml#
25 +title: StarFive PWM controller
28 + - William Qiu <william.qiu@starfivetech.com>
31 + StarFive SoCs contain PWM and when operating in PWM mode, the PTC core generates
32 + binary signal with user-programmable low and high periods. Clock source for the
33 + PWM can be either system clockor external clock. Each PWM timer block provides 8
41 + const: starfive,jh7110-pwm
61 +additionalProperties: false
66 + compatible = "starfive,jh7110-pwm";
67 + reg = <0x120d0000 0x10000>;
68 + clocks = <&syscrg 121>;
69 + resets = <&syscrg 108>;