1 From 60817a4e755c6e98092fdceec35fcda94d35e4b1 Mon Sep 17 00:00:00 2001
2 From: Jack Zhu <jack.zhu@starfivetech.com>
3 Date: Tue, 23 May 2023 16:56:23 +0800
4 Subject: [PATCH 077/122] media: dt-bindings: cadence-csi2rx: Add resets
7 Add resets property for Cadence MIPI-CSI2 RX controller
9 Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
10 Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
11 Signed-off-by: Jack Zhu <jack.zhu@starfivetech.com>
13 .../bindings/media/cdns,csi2rx.yaml | 24 +++++++++++++++++++
14 1 file changed, 24 insertions(+)
16 --- a/Documentation/devicetree/bindings/media/cdns,csi2rx.yaml
17 +++ b/Documentation/devicetree/bindings/media/cdns,csi2rx.yaml
18 @@ -41,6 +41,24 @@ properties:
19 - const: pixel_if2_clk
20 - const: pixel_if3_clk
24 + - description: CSI2Rx system reset
25 + - description: Gated Register bank reset for APB interface
26 + - description: pixel reset for Stream interface 0
27 + - description: pixel reset for Stream interface 1
28 + - description: pixel reset for Stream interface 2
29 + - description: pixel reset for Stream interface 3
42 description: MIPI D-PHY
43 @@ -123,6 +141,12 @@ examples:
44 clock-names = "sys_clk", "p_clk",
45 "pixel_if0_clk", "pixel_if1_clk",
46 "pixel_if2_clk", "pixel_if3_clk";
47 + resets = <&bytereset 9>, <&bytereset 4>,
48 + <&corereset 5>, <&corereset 6>,
49 + <&corereset 7>, <&corereset 8>;
50 + reset-names = "sys", "reg_bank",
51 + "pixel_if0", "pixel_if1",
52 + "pixel_if2", "pixel_if3";