1 From 2fbf4d367b25de4fa2f2d9cec57c88766c37d9de Mon Sep 17 00:00:00 2001
2 From: Jack Zhu <jack.zhu@starfivetech.com>
3 Date: Tue, 23 May 2023 16:56:24 +0800
4 Subject: [PATCH 078/122] media: cadence: Add operation on reset
6 Add operation on reset for Cadence MIPI-CSI2 RX Controller.
8 Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
9 Signed-off-by: Jack Zhu <jack.zhu@starfivetech.com>
11 drivers/media/platform/cadence/cdns-csi2rx.c | 40 +++++++++++++++++---
12 1 file changed, 35 insertions(+), 5 deletions(-)
14 --- a/drivers/media/platform/cadence/cdns-csi2rx.c
15 +++ b/drivers/media/platform/cadence/cdns-csi2rx.c
17 #include <linux/of_graph.h>
18 #include <linux/phy/phy.h>
19 #include <linux/platform_device.h>
20 +#include <linux/reset.h>
21 #include <linux/slab.h>
23 #include <media/v4l2-ctrls.h>
24 @@ -68,6 +69,9 @@ struct csi2rx_priv {
27 struct clk *pixel_clk[CSI2RX_STREAMS_MAX];
28 + struct reset_control *sys_rst;
29 + struct reset_control *p_rst;
30 + struct reset_control *pixel_rst[CSI2RX_STREAMS_MAX];
33 u8 lanes[CSI2RX_LANES_MAX];
34 @@ -112,6 +116,7 @@ static int csi2rx_start(struct csi2rx_pr
38 + reset_control_deassert(csi2rx->p_rst);
41 reg = csi2rx->num_lanes << 8;
42 @@ -154,6 +159,8 @@ static int csi2rx_start(struct csi2rx_pr
44 goto err_disable_pixclk;
46 + reset_control_deassert(csi2rx->pixel_rst[i]);
48 writel(CSI2RX_STREAM_CFG_FIFO_MODE_LARGE_BUF,
49 csi2rx->base + CSI2RX_STREAM_CFG_REG(i));
51 @@ -169,13 +176,16 @@ static int csi2rx_start(struct csi2rx_pr
53 goto err_disable_pixclk;
55 + reset_control_deassert(csi2rx->sys_rst);
56 clk_disable_unprepare(csi2rx->p_clk);
62 + for (; i > 0; i--) {
63 + reset_control_assert(csi2rx->pixel_rst[i - 1]);
64 clk_disable_unprepare(csi2rx->pixel_clk[i - 1]);
68 clk_disable_unprepare(csi2rx->p_clk);
69 @@ -188,14 +198,17 @@ static void csi2rx_stop(struct csi2rx_pr
72 clk_prepare_enable(csi2rx->p_clk);
73 + reset_control_assert(csi2rx->sys_rst);
74 clk_disable_unprepare(csi2rx->sys_clk);
76 for (i = 0; i < csi2rx->max_streams; i++) {
77 writel(0, csi2rx->base + CSI2RX_STREAM_CTRL_REG(i));
79 + reset_control_assert(csi2rx->pixel_rst[i]);
80 clk_disable_unprepare(csi2rx->pixel_clk[i]);
83 + reset_control_assert(csi2rx->p_rst);
84 clk_disable_unprepare(csi2rx->p_clk);
86 if (v4l2_subdev_call(csi2rx->source_subdev, video, s_stream, false))
87 @@ -299,6 +312,16 @@ static int csi2rx_get_resources(struct c
88 return PTR_ERR(csi2rx->p_clk);
91 + csi2rx->sys_rst = devm_reset_control_get_optional_exclusive(&pdev->dev,
93 + if (IS_ERR(csi2rx->sys_rst))
94 + return PTR_ERR(csi2rx->sys_rst);
96 + csi2rx->p_rst = devm_reset_control_get_optional_exclusive(&pdev->dev,
98 + if (IS_ERR(csi2rx->p_rst))
99 + return PTR_ERR(csi2rx->p_rst);
101 csi2rx->dphy = devm_phy_optional_get(&pdev->dev, "dphy");
102 if (IS_ERR(csi2rx->dphy)) {
103 dev_err(&pdev->dev, "Couldn't get external D-PHY\n");
104 @@ -349,14 +372,21 @@ static int csi2rx_get_resources(struct c
107 for (i = 0; i < csi2rx->max_streams; i++) {
111 - snprintf(clk_name, sizeof(clk_name), "pixel_if%u_clk", i);
112 - csi2rx->pixel_clk[i] = devm_clk_get(&pdev->dev, clk_name);
113 + snprintf(name, sizeof(name), "pixel_if%u_clk", i);
114 + csi2rx->pixel_clk[i] = devm_clk_get(&pdev->dev, name);
115 if (IS_ERR(csi2rx->pixel_clk[i])) {
116 - dev_err(&pdev->dev, "Couldn't get clock %s\n", clk_name);
117 + dev_err(&pdev->dev, "Couldn't get clock %s\n", name);
118 return PTR_ERR(csi2rx->pixel_clk[i]);
121 + snprintf(name, sizeof(name), "pixel_if%u", i);
122 + csi2rx->pixel_rst[i] =
123 + devm_reset_control_get_optional_exclusive(&pdev->dev,
125 + if (IS_ERR(csi2rx->pixel_rst[i]))
126 + return PTR_ERR(csi2rx->pixel_rst[i]);