1 From 0b99a4626c7e148df128c6a8cb686d500431189b Mon Sep 17 00:00:00 2001
2 From: Jia Jie Ho <jiajie.ho@starfivetech.com>
3 Date: Tue, 17 Jan 2023 09:54:43 +0800
4 Subject: [PATCH 101/122] dt-bindings: rng: Add StarFive TRNG module
6 Add documentation to describe Starfive true random number generator
9 Co-developed-by: Jenny Zhang <jenny.zhang@starfivetech.com>
10 Signed-off-by: Jenny Zhang <jenny.zhang@starfivetech.com>
11 Signed-off-by: Jia Jie Ho <jiajie.ho@starfivetech.com>
12 Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
13 Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
15 .../bindings/rng/starfive,jh7110-trng.yaml | 55 +++++++++++++++++++
16 1 file changed, 55 insertions(+)
17 create mode 100644 Documentation/devicetree/bindings/rng/starfive,jh7110-trng.yaml
20 +++ b/Documentation/devicetree/bindings/rng/starfive,jh7110-trng.yaml
22 +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
25 +$id: http://devicetree.org/schemas/rng/starfive,jh7110-trng.yaml#
26 +$schema: http://devicetree.org/meta-schemas/core.yaml#
28 +title: StarFive SoC TRNG Module
31 + - Jia Jie Ho <jiajie.ho@starfivetech.com>
35 + const: starfive,jh7110-trng
42 + - description: Hardware reference clock
43 + - description: AHB reference clock
64 +additionalProperties: false
69 + compatible = "starfive,jh7110-trng";
70 + reg = <0x1600C000 0x4000>;
71 + clocks = <&clk 15>, <&clk 16>;
72 + clock-names = "hclk", "ahb";
73 + resets = <&reset 3>;