1 From e835861823130ae47665db5e8039a7097ede14e4 Mon Sep 17 00:00:00 2001
2 From: Xingyu Wu <xingyu.wu@starfivetech.com>
3 Date: Tue, 14 Mar 2023 21:24:36 +0800
4 Subject: [PATCH 105/122] drivers: watchdog: Add StarFive Watchdog driver
6 Add watchdog driver for the StarFive JH7100 and JH7110 SoC.
8 Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
9 Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
10 Reviewed-by: Guenter Roeck <linux@roeck-us.net>
13 drivers/watchdog/Kconfig | 11 +
14 drivers/watchdog/Makefile | 3 +
15 drivers/watchdog/starfive-wdt.c | 606 ++++++++++++++++++++++++++++++++
16 4 files changed, 627 insertions(+)
17 create mode 100644 drivers/watchdog/starfive-wdt.c
21 @@ -19715,6 +19715,13 @@ S: Supported
22 F: Documentation/devicetree/bindings/rng/starfive*
23 F: drivers/char/hw_random/starfive-trng.c
25 +STARFIVE WATCHDOG DRIVER
26 +M: Xingyu Wu <xingyu.wu@starfivetech.com>
27 +M: Samin Guo <samin.guo@starfivetech.com>
29 +F: Documentation/devicetree/bindings/watchdog/starfive*
30 +F: drivers/watchdog/starfive-wdt.c
33 M: Peter Zijlstra <peterz@infradead.org>
34 M: Josh Poimboeuf <jpoimboe@kernel.org>
35 --- a/drivers/watchdog/Kconfig
36 +++ b/drivers/watchdog/Kconfig
37 @@ -1991,6 +1991,17 @@ config WATCHDOG_RTAS
38 To compile this driver as a module, choose M here. The module
39 will be called wdrtas.
41 +# RISC-V Architecture
43 +config STARFIVE_WATCHDOG
44 + tristate "StarFive Watchdog support"
45 + depends on ARCH_STARFIVE || COMPILE_TEST
46 + select WATCHDOG_CORE
47 + default ARCH_STARFIVE
49 + Say Y here to support the watchdog of StarFive JH7100 and JH7110
50 + SoC. This driver can also be built as a module if choose M.
54 config DIAG288_WATCHDOG
55 --- a/drivers/watchdog/Makefile
56 +++ b/drivers/watchdog/Makefile
57 @@ -191,6 +191,9 @@ obj-$(CONFIG_MEN_A21_WDT) += mena21_wdt.
58 obj-$(CONFIG_PSERIES_WDT) += pseries-wdt.o
59 obj-$(CONFIG_WATCHDOG_RTAS) += wdrtas.o
61 +# RISC-V Architecture
62 +obj-$(CONFIG_STARFIVE_WATCHDOG) += starfive-wdt.o
65 obj-$(CONFIG_DIAG288_WATCHDOG) += diag288_wdt.o
68 +++ b/drivers/watchdog/starfive-wdt.c
70 +// SPDX-License-Identifier: GPL-2.0
72 + * Starfive Watchdog driver
74 + * Copyright (C) 2022 StarFive Technology Co., Ltd.
77 +#include <linux/clk.h>
78 +#include <linux/iopoll.h>
79 +#include <linux/module.h>
80 +#include <linux/of_device.h>
81 +#include <linux/pm_runtime.h>
82 +#include <linux/reset.h>
83 +#include <linux/watchdog.h>
85 +/* JH7100 Watchdog register define */
86 +#define STARFIVE_WDT_JH7100_INTSTAUS 0x000
87 +#define STARFIVE_WDT_JH7100_CONTROL 0x104
88 +#define STARFIVE_WDT_JH7100_LOAD 0x108
89 +#define STARFIVE_WDT_JH7100_EN 0x110
90 +#define STARFIVE_WDT_JH7100_RELOAD 0x114 /* Write 0 or 1 to reload preset value */
91 +#define STARFIVE_WDT_JH7100_VALUE 0x118
92 +#define STARFIVE_WDT_JH7100_INTCLR 0x120 /*
93 + * [0]: Write 1 to clear interrupt
94 + * [1]: 1 mean clearing and 0 mean complete
97 +#define STARFIVE_WDT_JH7100_LOCK 0x13c /* write 0x378f0765 to unlock */
99 +/* JH7110 Watchdog register define */
100 +#define STARFIVE_WDT_JH7110_LOAD 0x000
101 +#define STARFIVE_WDT_JH7110_VALUE 0x004
102 +#define STARFIVE_WDT_JH7110_CONTROL 0x008 /*
103 + * [0]: reset enable;
104 + * [1]: interrupt enable && watchdog enable
105 + * [31:2]: reserved.
107 +#define STARFIVE_WDT_JH7110_INTCLR 0x00c /* clear intterupt and reload the counter */
108 +#define STARFIVE_WDT_JH7110_IMS 0x014
109 +#define STARFIVE_WDT_JH7110_LOCK 0xc00 /* write 0x1ACCE551 to unlock */
112 +#define STARFIVE_WDT_ENABLE 0x1
113 +#define STARFIVE_WDT_EN_SHIFT 0
114 +#define STARFIVE_WDT_RESET_EN 0x1
115 +#define STARFIVE_WDT_JH7100_RST_EN_SHIFT 0
116 +#define STARFIVE_WDT_JH7110_RST_EN_SHIFT 1
119 +#define STARFIVE_WDT_JH7100_UNLOCK_KEY 0x378f0765
120 +#define STARFIVE_WDT_JH7110_UNLOCK_KEY 0x1acce551
123 +#define STARFIVE_WDT_INTCLR 0x1
124 +#define STARFIVE_WDT_JH7100_INTCLR_AVA_SHIFT 1 /* Watchdog can clear interrupt when 0 */
126 +#define STARFIVE_WDT_MAXCNT 0xffffffff
127 +#define STARFIVE_WDT_DEFAULT_TIME (15)
128 +#define STARFIVE_WDT_DELAY_US 0
129 +#define STARFIVE_WDT_TIMEOUT_US 10000
131 +/* module parameter */
132 +#define STARFIVE_WDT_EARLY_ENA 0
134 +static bool nowayout = WATCHDOG_NOWAYOUT;
135 +static int heartbeat;
136 +static bool early_enable = STARFIVE_WDT_EARLY_ENA;
138 +module_param(heartbeat, int, 0);
139 +module_param(early_enable, bool, 0);
140 +module_param(nowayout, bool, 0);
142 +MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (default="
143 + __MODULE_STRING(STARFIVE_WDT_DEFAULT_TIME) ")");
144 +MODULE_PARM_DESC(early_enable,
145 + "Watchdog is started at boot time if set to 1, default="
146 + __MODULE_STRING(STARFIVE_WDT_EARLY_ENA));
147 +MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
148 + __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
150 +struct starfive_wdt_variant {
151 + unsigned int control; /* Watchdog Control Resgister for reset enable */
152 + unsigned int load; /* Watchdog Load register */
153 + unsigned int reload; /* Watchdog Reload Control register */
154 + unsigned int enable; /* Watchdog Enable Register */
155 + unsigned int value; /* Watchdog Counter Value Register */
156 + unsigned int int_clr; /* Watchdog Interrupt Clear Register */
157 + unsigned int unlock; /* Watchdog Lock Register */
158 + unsigned int int_status; /* Watchdog Interrupt Status Register */
163 + bool intclr_check; /* whether need to check it before clearing interrupt */
164 + char intclr_ava_shift;
165 + bool double_timeout; /* The watchdog need twice timeout to reboot */
168 +struct starfive_wdt {
169 + struct watchdog_device wdd;
170 + spinlock_t lock; /* spinlock for register handling */
171 + void __iomem *base;
172 + struct clk *core_clk;
173 + struct clk *apb_clk;
174 + const struct starfive_wdt_variant *variant;
175 + unsigned long freq;
176 + u32 count; /* count of timeout */
177 + u32 reload; /* restore the count */
180 +/* Register layout and configuration for the JH7100 */
181 +static const struct starfive_wdt_variant starfive_wdt_jh7100_variant = {
182 + .control = STARFIVE_WDT_JH7100_CONTROL,
183 + .load = STARFIVE_WDT_JH7100_LOAD,
184 + .reload = STARFIVE_WDT_JH7100_RELOAD,
185 + .enable = STARFIVE_WDT_JH7100_EN,
186 + .value = STARFIVE_WDT_JH7100_VALUE,
187 + .int_clr = STARFIVE_WDT_JH7100_INTCLR,
188 + .unlock = STARFIVE_WDT_JH7100_LOCK,
189 + .unlock_key = STARFIVE_WDT_JH7100_UNLOCK_KEY,
190 + .int_status = STARFIVE_WDT_JH7100_INTSTAUS,
191 + .enrst_shift = STARFIVE_WDT_JH7100_RST_EN_SHIFT,
192 + .en_shift = STARFIVE_WDT_EN_SHIFT,
193 + .intclr_check = true,
194 + .intclr_ava_shift = STARFIVE_WDT_JH7100_INTCLR_AVA_SHIFT,
195 + .double_timeout = false,
198 +/* Register layout and configuration for the JH7110 */
199 +static const struct starfive_wdt_variant starfive_wdt_jh7110_variant = {
200 + .control = STARFIVE_WDT_JH7110_CONTROL,
201 + .load = STARFIVE_WDT_JH7110_LOAD,
202 + .enable = STARFIVE_WDT_JH7110_CONTROL,
203 + .value = STARFIVE_WDT_JH7110_VALUE,
204 + .int_clr = STARFIVE_WDT_JH7110_INTCLR,
205 + .unlock = STARFIVE_WDT_JH7110_LOCK,
206 + .unlock_key = STARFIVE_WDT_JH7110_UNLOCK_KEY,
207 + .int_status = STARFIVE_WDT_JH7110_IMS,
208 + .enrst_shift = STARFIVE_WDT_JH7110_RST_EN_SHIFT,
209 + .en_shift = STARFIVE_WDT_EN_SHIFT,
210 + .intclr_check = false,
211 + .double_timeout = true,
214 +static int starfive_wdt_enable_clock(struct starfive_wdt *wdt)
218 + ret = clk_prepare_enable(wdt->apb_clk);
220 + return dev_err_probe(wdt->wdd.parent, ret, "failed to enable apb clock\n");
222 + ret = clk_prepare_enable(wdt->core_clk);
224 + return dev_err_probe(wdt->wdd.parent, ret, "failed to enable core clock\n");
229 +static void starfive_wdt_disable_clock(struct starfive_wdt *wdt)
231 + clk_disable_unprepare(wdt->core_clk);
232 + clk_disable_unprepare(wdt->apb_clk);
235 +static inline int starfive_wdt_get_clock(struct starfive_wdt *wdt)
237 + struct device *dev = wdt->wdd.parent;
239 + wdt->apb_clk = devm_clk_get(dev, "apb");
240 + if (IS_ERR(wdt->apb_clk))
241 + return dev_err_probe(dev, PTR_ERR(wdt->apb_clk), "failed to get apb clock\n");
243 + wdt->core_clk = devm_clk_get(dev, "core");
244 + if (IS_ERR(wdt->core_clk))
245 + return dev_err_probe(dev, PTR_ERR(wdt->core_clk), "failed to get core clock\n");
250 +static inline int starfive_wdt_reset_init(struct device *dev)
252 + struct reset_control *rsts;
255 + rsts = devm_reset_control_array_get_exclusive(dev);
257 + return dev_err_probe(dev, PTR_ERR(rsts), "failed to get resets\n");
259 + ret = reset_control_deassert(rsts);
261 + return dev_err_probe(dev, ret, "failed to deassert resets\n");
266 +static u32 starfive_wdt_ticks_to_sec(struct starfive_wdt *wdt, u32 ticks)
268 + return DIV_ROUND_CLOSEST(ticks, wdt->freq);
271 +/* Write unlock-key to unlock. Write other value to lock. */
272 +static void starfive_wdt_unlock(struct starfive_wdt *wdt)
274 + spin_lock(&wdt->lock);
275 + writel(wdt->variant->unlock_key, wdt->base + wdt->variant->unlock);
278 +static void starfive_wdt_lock(struct starfive_wdt *wdt)
280 + writel(~wdt->variant->unlock_key, wdt->base + wdt->variant->unlock);
281 + spin_unlock(&wdt->lock);
284 +/* enable watchdog interrupt to reset/reboot */
285 +static void starfive_wdt_enable_reset(struct starfive_wdt *wdt)
289 + val = readl(wdt->base + wdt->variant->control);
290 + val |= STARFIVE_WDT_RESET_EN << wdt->variant->enrst_shift;
291 + writel(val, wdt->base + wdt->variant->control);
294 +/* interrupt status whether has been raised from the counter */
295 +static bool starfive_wdt_raise_irq_status(struct starfive_wdt *wdt)
297 + return !!readl(wdt->base + wdt->variant->int_status);
300 +/* waiting interrupt can be free to clear */
301 +static int starfive_wdt_wait_int_free(struct starfive_wdt *wdt)
305 + return readl_poll_timeout_atomic(wdt->base + wdt->variant->int_clr, value,
306 + !(value & BIT(wdt->variant->intclr_ava_shift)),
307 + STARFIVE_WDT_DELAY_US, STARFIVE_WDT_TIMEOUT_US);
310 +/* clear interrupt signal before initialization or reload */
311 +static int starfive_wdt_int_clr(struct starfive_wdt *wdt)
315 + if (wdt->variant->intclr_check) {
316 + ret = starfive_wdt_wait_int_free(wdt);
318 + return dev_err_probe(wdt->wdd.parent, ret,
319 + "watchdog is not ready to clear interrupt.\n");
321 + writel(STARFIVE_WDT_INTCLR, wdt->base + wdt->variant->int_clr);
326 +static inline void starfive_wdt_set_count(struct starfive_wdt *wdt, u32 val)
328 + writel(val, wdt->base + wdt->variant->load);
331 +static inline u32 starfive_wdt_get_count(struct starfive_wdt *wdt)
333 + return readl(wdt->base + wdt->variant->value);
336 +/* enable watchdog */
337 +static inline void starfive_wdt_enable(struct starfive_wdt *wdt)
341 + val = readl(wdt->base + wdt->variant->enable);
342 + val |= STARFIVE_WDT_ENABLE << wdt->variant->en_shift;
343 + writel(val, wdt->base + wdt->variant->enable);
346 +/* disable watchdog */
347 +static inline void starfive_wdt_disable(struct starfive_wdt *wdt)
351 + val = readl(wdt->base + wdt->variant->enable);
352 + val &= ~(STARFIVE_WDT_ENABLE << wdt->variant->en_shift);
353 + writel(val, wdt->base + wdt->variant->enable);
356 +static inline void starfive_wdt_set_reload_count(struct starfive_wdt *wdt, u32 count)
358 + starfive_wdt_set_count(wdt, count);
360 + /* 7100 need set any value to reload register and could reload value to counter */
361 + if (wdt->variant->reload)
362 + writel(0x1, wdt->base + wdt->variant->reload);
365 +static unsigned int starfive_wdt_max_timeout(struct starfive_wdt *wdt)
367 + if (wdt->variant->double_timeout)
368 + return DIV_ROUND_UP(STARFIVE_WDT_MAXCNT, (wdt->freq / 2)) - 1;
370 + return DIV_ROUND_UP(STARFIVE_WDT_MAXCNT, wdt->freq) - 1;
373 +static unsigned int starfive_wdt_get_timeleft(struct watchdog_device *wdd)
375 + struct starfive_wdt *wdt = watchdog_get_drvdata(wdd);
379 + * If the watchdog takes twice timeout and set half count value,
380 + * timeleft value should add the count value before first timeout.
382 + count = starfive_wdt_get_count(wdt);
383 + if (wdt->variant->double_timeout && !starfive_wdt_raise_irq_status(wdt))
384 + count += wdt->count;
386 + return starfive_wdt_ticks_to_sec(wdt, count);
389 +static int starfive_wdt_keepalive(struct watchdog_device *wdd)
391 + struct starfive_wdt *wdt = watchdog_get_drvdata(wdd);
394 + starfive_wdt_unlock(wdt);
395 + ret = starfive_wdt_int_clr(wdt);
399 + starfive_wdt_set_reload_count(wdt, wdt->count);
402 + /* exit with releasing spinlock and locking registers */
403 + starfive_wdt_lock(wdt);
407 +static int starfive_wdt_start(struct starfive_wdt *wdt)
411 + starfive_wdt_unlock(wdt);
412 + /* disable watchdog, to be safe */
413 + starfive_wdt_disable(wdt);
415 + starfive_wdt_enable_reset(wdt);
416 + ret = starfive_wdt_int_clr(wdt);
420 + starfive_wdt_set_count(wdt, wdt->count);
421 + starfive_wdt_enable(wdt);
424 + starfive_wdt_lock(wdt);
428 +static void starfive_wdt_stop(struct starfive_wdt *wdt)
430 + starfive_wdt_unlock(wdt);
431 + starfive_wdt_disable(wdt);
432 + starfive_wdt_lock(wdt);
435 +static int starfive_wdt_pm_start(struct watchdog_device *wdd)
437 + struct starfive_wdt *wdt = watchdog_get_drvdata(wdd);
438 + int ret = pm_runtime_get_sync(wdd->parent);
443 + return starfive_wdt_start(wdt);
446 +static int starfive_wdt_pm_stop(struct watchdog_device *wdd)
448 + struct starfive_wdt *wdt = watchdog_get_drvdata(wdd);
450 + starfive_wdt_stop(wdt);
451 + return pm_runtime_put_sync(wdd->parent);
454 +static int starfive_wdt_set_timeout(struct watchdog_device *wdd,
455 + unsigned int timeout)
457 + struct starfive_wdt *wdt = watchdog_get_drvdata(wdd);
458 + unsigned long count = timeout * wdt->freq;
460 + /* some watchdogs take two timeouts to reset */
461 + if (wdt->variant->double_timeout)
464 + wdt->count = count;
465 + wdd->timeout = timeout;
467 + starfive_wdt_unlock(wdt);
468 + starfive_wdt_disable(wdt);
469 + starfive_wdt_set_reload_count(wdt, wdt->count);
470 + starfive_wdt_enable(wdt);
471 + starfive_wdt_lock(wdt);
476 +#define STARFIVE_WDT_OPTIONS (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE)
478 +static const struct watchdog_info starfive_wdt_info = {
479 + .options = STARFIVE_WDT_OPTIONS,
480 + .identity = "StarFive Watchdog",
483 +static const struct watchdog_ops starfive_wdt_ops = {
484 + .owner = THIS_MODULE,
485 + .start = starfive_wdt_pm_start,
486 + .stop = starfive_wdt_pm_stop,
487 + .ping = starfive_wdt_keepalive,
488 + .set_timeout = starfive_wdt_set_timeout,
489 + .get_timeleft = starfive_wdt_get_timeleft,
492 +static int starfive_wdt_probe(struct platform_device *pdev)
494 + struct starfive_wdt *wdt;
497 + wdt = devm_kzalloc(&pdev->dev, sizeof(*wdt), GFP_KERNEL);
501 + wdt->base = devm_platform_ioremap_resource(pdev, 0);
502 + if (IS_ERR(wdt->base))
503 + return dev_err_probe(&pdev->dev, PTR_ERR(wdt->base), "error mapping registers\n");
505 + wdt->wdd.parent = &pdev->dev;
506 + ret = starfive_wdt_get_clock(wdt);
510 + platform_set_drvdata(pdev, wdt);
511 + pm_runtime_enable(&pdev->dev);
512 + if (pm_runtime_enabled(&pdev->dev)) {
513 + ret = pm_runtime_get_sync(&pdev->dev);
517 + /* runtime PM is disabled but clocks need to be enabled */
518 + ret = starfive_wdt_enable_clock(wdt);
523 + ret = starfive_wdt_reset_init(&pdev->dev);
527 + watchdog_set_drvdata(&wdt->wdd, wdt);
528 + wdt->wdd.info = &starfive_wdt_info;
529 + wdt->wdd.ops = &starfive_wdt_ops;
530 + wdt->variant = of_device_get_match_data(&pdev->dev);
531 + spin_lock_init(&wdt->lock);
533 + wdt->freq = clk_get_rate(wdt->core_clk);
535 + dev_err(&pdev->dev, "get clock rate failed.\n");
540 + wdt->wdd.min_timeout = 1;
541 + wdt->wdd.max_timeout = starfive_wdt_max_timeout(wdt);
542 + wdt->wdd.timeout = STARFIVE_WDT_DEFAULT_TIME;
543 + watchdog_init_timeout(&wdt->wdd, heartbeat, &pdev->dev);
544 + starfive_wdt_set_timeout(&wdt->wdd, wdt->wdd.timeout);
546 + watchdog_set_nowayout(&wdt->wdd, nowayout);
547 + watchdog_stop_on_reboot(&wdt->wdd);
548 + watchdog_stop_on_unregister(&wdt->wdd);
550 + if (early_enable) {
551 + ret = starfive_wdt_start(wdt);
554 + set_bit(WDOG_HW_RUNNING, &wdt->wdd.status);
556 + starfive_wdt_stop(wdt);
559 + ret = watchdog_register_device(&wdt->wdd);
564 + return pm_runtime_put_sync(&pdev->dev);
569 + starfive_wdt_disable_clock(wdt);
570 + pm_runtime_disable(&pdev->dev);
575 +static int starfive_wdt_remove(struct platform_device *pdev)
577 + struct starfive_wdt *wdt = platform_get_drvdata(pdev);
579 + starfive_wdt_stop(wdt);
580 + watchdog_unregister_device(&wdt->wdd);
582 + if (pm_runtime_enabled(&pdev->dev))
583 + pm_runtime_disable(&pdev->dev);
585 + /* disable clock without PM */
586 + starfive_wdt_disable_clock(wdt);
591 +static void starfive_wdt_shutdown(struct platform_device *pdev)
593 + struct starfive_wdt *wdt = platform_get_drvdata(pdev);
595 + starfive_wdt_pm_stop(&wdt->wdd);
598 +#ifdef CONFIG_PM_SLEEP
599 +static int starfive_wdt_suspend(struct device *dev)
601 + struct starfive_wdt *wdt = dev_get_drvdata(dev);
603 + /* Save watchdog state, and turn it off. */
604 + wdt->reload = starfive_wdt_get_count(wdt);
606 + /* Note that WTCNT doesn't need to be saved. */
607 + starfive_wdt_stop(wdt);
609 + return pm_runtime_force_suspend(dev);
612 +static int starfive_wdt_resume(struct device *dev)
614 + struct starfive_wdt *wdt = dev_get_drvdata(dev);
617 + ret = pm_runtime_force_resume(dev);
621 + starfive_wdt_unlock(wdt);
622 + /* Restore watchdog state. */
623 + starfive_wdt_set_reload_count(wdt, wdt->reload);
624 + starfive_wdt_lock(wdt);
626 + return starfive_wdt_start(wdt);
628 +#endif /* CONFIG_PM_SLEEP */
631 +static int starfive_wdt_runtime_suspend(struct device *dev)
633 + struct starfive_wdt *wdt = dev_get_drvdata(dev);
635 + starfive_wdt_disable_clock(wdt);
640 +static int starfive_wdt_runtime_resume(struct device *dev)
642 + struct starfive_wdt *wdt = dev_get_drvdata(dev);
644 + return starfive_wdt_enable_clock(wdt);
646 +#endif /* CONFIG_PM */
648 +static const struct dev_pm_ops starfive_wdt_pm_ops = {
649 + SET_RUNTIME_PM_OPS(starfive_wdt_runtime_suspend, starfive_wdt_runtime_resume, NULL)
650 + SET_SYSTEM_SLEEP_PM_OPS(starfive_wdt_suspend, starfive_wdt_resume)
653 +static const struct of_device_id starfive_wdt_match[] = {
654 + { .compatible = "starfive,jh7100-wdt", .data = &starfive_wdt_jh7100_variant },
655 + { .compatible = "starfive,jh7110-wdt", .data = &starfive_wdt_jh7110_variant },
658 +MODULE_DEVICE_TABLE(of, starfive_wdt_match);
660 +static struct platform_driver starfive_wdt_driver = {
661 + .probe = starfive_wdt_probe,
662 + .remove = starfive_wdt_remove,
663 + .shutdown = starfive_wdt_shutdown,
665 + .name = "starfive-wdt",
666 + .pm = &starfive_wdt_pm_ops,
667 + .of_match_table = of_match_ptr(starfive_wdt_match),
670 +module_platform_driver(starfive_wdt_driver);
672 +MODULE_AUTHOR("Xingyu Wu <xingyu.wu@starfivetech.com>");
673 +MODULE_AUTHOR("Samin Guo <samin.guo@starfivetech.com>");
674 +MODULE_DESCRIPTION("StarFive Watchdog Device Driver");
675 +MODULE_LICENSE("GPL");