target/linux/starfive/patches-6.1/1017-dt-bindings-riscv-sifive-ccache-Add-uncached-offset-.patch

   1 From 3b83b32e16fa431c76a5da1ac59c268ca2fecbb5 Mon Sep 17 00:00:00 2001
   2 From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
   3 Date: Sat, 11 Feb 2023 05:18:11 +0200
   4 Subject: [PATCH 1017/1024] dt-bindings: riscv: sifive-ccache: Add
   5  'uncached-offset' property
   6
   7 Add the 'uncached-offset' property to be used for specifying the
   8 uncached memory offset required for handling non-coherent DMA
   9 transactions.
  10
  11 Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
  12 Link: https://lore.kernel.org/r/20230211031821.976408-3-cristian.ciocaltea@collabora.com
  13 ---
  14  Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml | 5 +++++
  15  1 file changed, 5 insertions(+)
  16
  17 --- a/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml
  18 +++ b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml
  19 @@ -70,6 +70,11 @@ properties:
  20
  21    next-level-cache: true
  22
  23 +  uncached-offset:
  24 +    $ref: /schemas/types.yaml#/definitions/uint64
  25 +    description: |
  26 +      Uncached memory offset for handling non-coherent DMA transactions.
  27 +
  28    memory-region:
  29      maxItems: 1
  30      description: |