target/linux/sunxi/files/drivers/mmc/host/sunxi-mci.h

   1 /*
   2  * Driver for sunxi SD/MMC host controllers
   3  * (C) Copyright 2007-2011 Reuuimlla Technology Co., Ltd.
   4  * (C) Copyright 2007-2011 Aaron Maoye <leafy.myeh@reuuimllatech.com>
   5  * (C) Copyright 2013-2013 O2S GmbH <www.o2s.ch>
   6  * (C) Copyright 2013-2013 David Lanzendörfer <david.lanzendoerfer@o2s.ch>
   7  * (C) Copyright 2013-2013 Hans de Goede <hdegoede@redhat.com>
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  */
  14
  15 #ifndef __SUNXI_MCI_H__
  16 #define __SUNXI_MCI_H__
  17
  18 /* register offset define */
  19 #define SDXC_REG_GCTRL  (0x00) /* SMC Global Control Register */
  20 #define SDXC_REG_CLKCR  (0x04) /* SMC Clock Control Register */
  21 #define SDXC_REG_TMOUT  (0x08) /* SMC Time Out Register */
  22 #define SDXC_REG_WIDTH  (0x0C) /* SMC Bus Width Register */
  23 #define SDXC_REG_BLKSZ  (0x10) /* SMC Block Size Register */
  24 #define SDXC_REG_BCNTR  (0x14) /* SMC Byte Count Register */
  25 #define SDXC_REG_CMDR   (0x18) /* SMC Command Register */
  26 #define SDXC_REG_CARG   (0x1C) /* SMC Argument Register */
  27 #define SDXC_REG_RESP0  (0x20) /* SMC Response Register 0 */
  28 #define SDXC_REG_RESP1  (0x24) /* SMC Response Register 1 */
  29 #define SDXC_REG_RESP2  (0x28) /* SMC Response Register 2 */
  30 #define SDXC_REG_RESP3  (0x2C) /* SMC Response Register 3 */
  31 #define SDXC_REG_IMASK  (0x30) /* SMC Interrupt Mask Register */
  32 #define SDXC_REG_MISTA  (0x34) /* SMC Masked Interrupt Status Register */
  33 #define SDXC_REG_RINTR  (0x38) /* SMC Raw Interrupt Status Register */
  34 #define SDXC_REG_STAS   (0x3C) /* SMC Status Register */
  35 #define SDXC_REG_FTRGL  (0x40) /* SMC FIFO Threshold Watermark Registe */
  36 #define SDXC_REG_FUNS   (0x44) /* SMC Function Select Register */
  37 #define SDXC_REG_CBCR   (0x48) /* SMC CIU Byte Count Register */
  38 #define SDXC_REG_BBCR   (0x4C) /* SMC BIU Byte Count Register */
  39 #define SDXC_REG_DBGC   (0x50) /* SMC Debug Enable Register */
  40 #define SDXC_REG_HWRST  (0x78) /* SMC Card Hardware Reset for Register */
  41 #define SDXC_REG_DMAC   (0x80) /* SMC IDMAC Control Register */
  42 #define SDXC_REG_DLBA   (0x84) /* SMC IDMAC Descriptor List Base Addre */
  43 #define SDXC_REG_IDST   (0x88) /* SMC IDMAC Status Register */
  44 #define SDXC_REG_IDIE   (0x8C) /* SMC IDMAC Interrupt Enable Register */
  45 #define SDXC_REG_CHDA   (0x90)
  46 #define SDXC_REG_CBDA   (0x94)
  47
  48 #define mci_readl(host, reg) \
  49         __raw_readl((host)->reg_base + SDXC_##reg)
  50 #define mci_writel(host, reg, value) \
  51         __raw_writel((value), (host)->reg_base + SDXC_##reg)
  52
  53 /* global control register bits */
  54 #define SDXC_SoftReset          BIT(0)
  55 #define SDXC_FIFOReset          BIT(1)
  56 #define SDXC_DMAReset           BIT(2)
  57 #define SDXC_HWReset            (SDXC_SoftReset|SDXC_FIFOReset|SDXC_DMAReset)
  58 #define SDXC_INTEnb             BIT(4)
  59 #define SDXC_DMAEnb             BIT(5)
  60 #define SDXC_DebounceEnb        BIT(8)
  61 #define SDXC_PosedgeLatchData   BIT(9)
  62 #define SDXC_DDR_MODE           BIT(10)
  63 #define SDXC_MemAccessDone      BIT(29)
  64 #define SDXC_AccessDoneDirect   BIT(30)
  65 #define SDXC_ACCESS_BY_AHB      BIT(31)
  66 #define SDXC_ACCESS_BY_DMA      (0U << 31)
  67 /* clock control bits */
  68 #define SDXC_CardClkOn          BIT(16)
  69 #define SDXC_LowPowerOn         BIT(17)
  70 /* bus width */
  71 #define SDXC_WIDTH1             (0)
  72 #define SDXC_WIDTH4             (1)
  73 #define SDXC_WIDTH8             (2)
  74 /* smc command bits */
  75 #define SDXC_RspExp             BIT(6)
  76 #define SDXC_LongRsp            BIT(7)
  77 #define SDXC_CheckRspCRC        BIT(8)
  78 #define SDXC_DataExp            BIT(9)
  79 #define SDXC_Write              BIT(10)
  80 #define SDXC_Seqmod             BIT(11)
  81 #define SDXC_SendAutoStop       BIT(12)
  82 #define SDXC_WaitPreOver        BIT(13)
  83 #define SDXC_StopAbortCMD       BIT(14)
  84 #define SDXC_SendInitSeq        BIT(15)
  85 #define SDXC_UPCLKOnly          BIT(21)
  86 #define SDXC_RdCEATADev         BIT(22)
  87 #define SDXC_CCSExp             BIT(23)
  88 #define SDXC_EnbBoot            BIT(24)
  89 #define SDXC_AltBootOpt         BIT(25)
  90 #define SDXC_BootACKExp         BIT(26)
  91 #define SDXC_BootAbort          BIT(27)
  92 #define SDXC_VolSwitch          BIT(28)
  93 #define SDXC_UseHoldReg         BIT(29)
  94 #define SDXC_Start              BIT(31)
  95 /* interrupt bits */
  96 #define SDXC_RespErr            BIT(1)
  97 #define SDXC_CmdDone            BIT(2)
  98 #define SDXC_DataOver           BIT(3)
  99 #define SDXC_TxDataReq          BIT(4)
 100 #define SDXC_RxDataReq          BIT(5)
 101 #define SDXC_RespCRCErr         BIT(6)
 102 #define SDXC_DataCRCErr         BIT(7)
 103 #define SDXC_RespTimeout        BIT(8)
 104 #define SDXC_DataTimeout        BIT(9)
 105 #define SDXC_VolChgDone         BIT(10)
 106 #define SDXC_FIFORunErr         BIT(11)
 107 #define SDXC_HardWLocked        BIT(12)
 108 #define SDXC_StartBitErr        BIT(13)
 109 #define SDXC_AutoCMDDone        BIT(14)
 110 #define SDXC_EndBitErr          BIT(15)
 111 #define SDXC_SDIOInt            BIT(16)
 112 #define SDXC_CardInsert         BIT(30)
 113 #define SDXC_CardRemove         BIT(31)
 114 #define SDXC_IntErrBit          (SDXC_RespErr | SDXC_RespCRCErr | \
 115                                  SDXC_DataCRCErr | SDXC_RespTimeout | \
 116                                  SDXC_DataTimeout | SDXC_FIFORunErr | \
 117                                  SDXC_HardWLocked | SDXC_StartBitErr | \
 118                                  SDXC_EndBitErr) /* 0xbbc2 */
 119 #define SDXC_IntDoneBit         (SDXC_AutoCMDDone | SDXC_DataOver | \
 120                                  SDXC_CmdDone | SDXC_VolChgDone)
 121 /* status */
 122 #define SDXC_RXWLFlag           BIT(0)
 123 #define SDXC_TXWLFlag           BIT(1)
 124 #define SDXC_FIFOEmpty          BIT(2)
 125 #define SDXC_FIFOFull           BIT(3)
 126 #define SDXC_CardPresent        BIT(8)
 127 #define SDXC_CardDataBusy       BIT(9)
 128 #define SDXC_DataFSMBusy        BIT(10)
 129 #define SDXC_DMAReq             BIT(31)
 130 #define SDXC_FIFO_SIZE          (16)
 131 /* Function select */
 132 #define SDXC_CEATAOn            (0xceaaU << 16)
 133 #define SDXC_SendIrqRsp         BIT(0)
 134 #define SDXC_SDIORdWait         BIT(1)
 135 #define SDXC_AbtRdData          BIT(2)
 136 #define SDXC_SendCCSD           BIT(8)
 137 #define SDXC_SendAutoStopCCSD   BIT(9)
 138 #define SDXC_CEATADevIntEnb     BIT(10)
 139 /* IDMA controller bus mod bit field */
 140 #define SDXC_IDMACSoftRST       BIT(0)
 141 #define SDXC_IDMACFixBurst      BIT(1)
 142 #define SDXC_IDMACIDMAOn        BIT(7)
 143 #define SDXC_IDMACRefetchDES    BIT(31)
 144 /* IDMA status bit field */
 145 #define SDXC_IDMACTransmitInt   BIT(0)
 146 #define SDXC_IDMACReceiveInt    BIT(1)
 147 #define SDXC_IDMACFatalBusErr   BIT(2)
 148 #define SDXC_IDMACDesInvalid    BIT(4)
 149 #define SDXC_IDMACCardErrSum    BIT(5)
 150 #define SDXC_IDMACNormalIntSum  BIT(8)
 151 #define SDXC_IDMACAbnormalIntSum BIT(9)
 152 #define SDXC_IDMACHostAbtInTx   BIT(10)
 153 #define SDXC_IDMACHostAbtInRx   BIT(10)
 154 #define SDXC_IDMACIdle          (0U << 13)
 155 #define SDXC_IDMACSuspend       (1U << 13)
 156 #define SDXC_IDMACDESCRd        (2U << 13)
 157 #define SDXC_IDMACDESCCheck     (3U << 13)
 158 #define SDXC_IDMACRdReqWait     (4U << 13)
 159 #define SDXC_IDMACWrReqWait     (5U << 13)
 160 #define SDXC_IDMACRd            (6U << 13)
 161 #define SDXC_IDMACWr            (7U << 13)
 162 #define SDXC_IDMACDESCClose     (8U << 13)
 163
 164 struct sunxi_idma_des {
 165         u32     config;
 166 #define SDXC_IDMAC_DES0_DIC     BIT(1)  /* disable interrupt on completion */
 167 #define SDXC_IDMAC_DES0_LD      BIT(2)  /* last descriptor */
 168 #define SDXC_IDMAC_DES0_FD      BIT(3)  /* first descriptor */
 169 #define SDXC_IDMAC_DES0_CH      BIT(4)  /* chain mode */
 170 #define SDXC_IDMAC_DES0_ER      BIT(5)  /* end of ring */
 171 #define SDXC_IDMAC_DES0_CES     BIT(30) /* card error summary */
 172 #define SDXC_IDMAC_DES0_OWN     BIT(31) /* 1-idma owns it, 0-host owns it */
 173
 174         /*
 175          * If the idma-des-size-bits of property is ie 13, bufsize bits are:
 176          *  Bits  0-12: buf1 size
 177          *  Bits 13-25: buf2 size
 178          *  Bits 26-31: not used
 179          * Since we only ever set buf1 size, we can simply store it directly.
 180          */
 181         u32     buf_size;
 182         u32     buf_addr_ptr1;
 183         u32     buf_addr_ptr2;
 184 };
 185
 186 struct sunxi_mmc_host {
 187         struct mmc_host *mmc;
 188         struct regulator *vmmc;
 189
 190         /* IO mapping base */
 191         void __iomem *reg_base;
 192
 193         spinlock_t lock;
 194         struct tasklet_struct tasklet;
 195
 196         /* clock management */
 197         struct clk *clk_ahb;
 198         struct clk *clk_mod;
 199
 200         /* indicator pins */
 201         int wp_pin;
 202         int cd_pin;
 203         int cd_mode;
 204 #define CARD_DETECT_BY_GPIO_POLL (1)    /* mmc detected by gpio check */
 205 #define CARD_ALWAYS_PRESENT      (2)    /* mmc always present */
 206
 207         /* ios information */
 208         u32             clk_mod_rate;
 209         u32             bus_width;
 210         u32             idma_des_size_bits;
 211         u32             ddr;
 212         u32             voltage_switching;
 213
 214         /* irq */
 215         int             irq;
 216         u32             int_sum;
 217         u32             sdio_imask;
 218
 219         /* flags */
 220         u32             power_on:1;
 221         u32             io_flag:1;
 222         u32             wait_dma:1;
 223
 224         dma_addr_t      sg_dma;
 225         void            *sg_cpu;
 226
 227         struct mmc_request *mrq;
 228         u32             ferror;
 229 };
 230
 231 #define MMC_CLK_400K            0
 232 #define MMC_CLK_25M             1
 233 #define MMC_CLK_50M             2
 234 #define MMC_CLK_50MDDR          3
 235 #define MMC_CLK_50MDDR_8BIT     4
 236 #define MMC_CLK_100M            5
 237 #define MMC_CLK_200M            6
 238 #define MMC_CLK_MOD_NUM         7
 239
 240 struct sunxi_mmc_clk_dly {
 241         u32 mode;
 242         u32 oclk_dly;
 243         u32 sclk_dly;
 244 };
 245
 246 #endif