1 From 2a906d06b21968803ce504348864908ad1ed66ac Mon Sep 17 00:00:00 2001
2 From: Maxime Ripard <maxime.ripard@free-electrons.com>
3 Date: Tue, 24 Sep 2013 11:10:41 +0300
4 Subject: [PATCH] ARM: sun6i: Add the reset controller to the DTSI
6 The A31 has a reset controller IP that maintains a few other IPs in
7 reset, among which we can find the UARTs, high speed timers or the I2C.
8 Now that we have support for them, add the reset controllers to the DTSI.
10 Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
12 arch/arm/boot/dts/sun6i-a31.dtsi | 24 ++++++++++++++++++++++++
13 1 file changed, 24 insertions(+)
15 diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
16 index c1751a6..c7e0658 100644
17 --- a/arch/arm/boot/dts/sun6i-a31.dtsi
18 +++ b/arch/arm/boot/dts/sun6i-a31.dtsi
23 + ahb1_rst: reset@01c202c0 {
25 + compatible = "allwinner,sun6i-a31-ahb1-reset";
26 + reg = <0x01c202c0 0xc>;
29 + apb1_rst: reset@01c202d0 {
31 + compatible = "allwinner,sun4i-clock-reset";
32 + reg = <0x01c202d0 0x4>;
35 + apb2_rst: reset@01c202d8 {
37 + compatible = "allwinner,sun4i-clock-reset";
38 + reg = <0x01c202d8 0x4>;
42 compatible = "allwinner,sun4i-timer";
43 reg = <0x01c20c00 0xa0>;
47 clocks = <&apb2_gates 16>;
48 + resets = <&apb2_rst 16>;
55 clocks = <&apb2_gates 17>;
56 + resets = <&apb2_rst 17>;
63 clocks = <&apb2_gates 18>;
64 + resets = <&apb2_rst 18>;
71 clocks = <&apb2_gates 19>;
72 + resets = <&apb2_rst 19>;
79 clocks = <&apb2_gates 20>;
80 + resets = <&apb2_rst 20>;
87 clocks = <&apb2_gates 21>;
88 + resets = <&apb2_rst 21>;