1 From 3e52e08e7f8f9cb1137f232e3bfa00f89ed27475 Mon Sep 17 00:00:00 2001
2 From: Maxime Ripard <maxime.ripard@free-electrons.com>
3 Date: Sat, 7 Dec 2013 12:38:32 +0100
4 Subject: [PATCH] ARM: sun7i: dt: Fix interrupt trigger types
6 The Allwinner A20 uses the ARM GIC as its internal interrupts controller. The
7 GIC can work on several interrupt triggers, and the A20 was actually setting it
8 up to use a rising edge as a trigger, while it was actually a level high
9 trigger, leading to some interrupts that would be completely ignored if the
12 Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
13 Reported-by: Hans de Goede <hdegoede@redhat.com>
14 Signed-off-by: Hans de Goede <hdegoede@redhat.com>
16 arch/arm/boot/dts/sun7i-a20.dtsi | 42 ++++++++++++++++++++--------------------
17 1 file changed, 21 insertions(+), 21 deletions(-)
19 diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
20 index f1a6b24..0b7fcc1 100644
21 --- a/arch/arm/boot/dts/sun7i-a20.dtsi
22 +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
24 emac: ethernet@01c0b000 {
25 compatible = "allwinner,sun4i-emac";
26 reg = <0x01c0b000 0x1000>;
27 - interrupts = <0 55 1>;
28 + interrupts = <0 55 4>;
29 clocks = <&ahb_gates 17>;
33 pio: pinctrl@01c20800 {
34 compatible = "allwinner,sun7i-a20-pinctrl";
35 reg = <0x01c20800 0x400>;
36 - interrupts = <0 28 1>;
37 + interrupts = <0 28 4>;
38 clocks = <&apb0_gates 5>;
43 compatible = "allwinner,sun4i-timer";
44 reg = <0x01c20c00 0x90>;
45 - interrupts = <0 22 1>,
51 + interrupts = <0 22 4>,
61 uart0: serial@01c28000 {
62 compatible = "snps,dw-apb-uart";
63 reg = <0x01c28000 0x400>;
64 - interrupts = <0 1 1>;
65 + interrupts = <0 1 4>;
68 clocks = <&apb1_gates 16>;
70 uart1: serial@01c28400 {
71 compatible = "snps,dw-apb-uart";
72 reg = <0x01c28400 0x400>;
73 - interrupts = <0 2 1>;
74 + interrupts = <0 2 4>;
77 clocks = <&apb1_gates 17>;
79 uart2: serial@01c28800 {
80 compatible = "snps,dw-apb-uart";
81 reg = <0x01c28800 0x400>;
82 - interrupts = <0 3 1>;
83 + interrupts = <0 3 4>;
86 clocks = <&apb1_gates 18>;
88 uart3: serial@01c28c00 {
89 compatible = "snps,dw-apb-uart";
90 reg = <0x01c28c00 0x400>;
91 - interrupts = <0 4 1>;
92 + interrupts = <0 4 4>;
95 clocks = <&apb1_gates 19>;
97 uart4: serial@01c29000 {
98 compatible = "snps,dw-apb-uart";
99 reg = <0x01c29000 0x400>;
100 - interrupts = <0 17 1>;
101 + interrupts = <0 17 4>;
104 clocks = <&apb1_gates 20>;
106 uart5: serial@01c29400 {
107 compatible = "snps,dw-apb-uart";
108 reg = <0x01c29400 0x400>;
109 - interrupts = <0 18 1>;
110 + interrupts = <0 18 4>;
113 clocks = <&apb1_gates 21>;
115 uart6: serial@01c29800 {
116 compatible = "snps,dw-apb-uart";
117 reg = <0x01c29800 0x400>;
118 - interrupts = <0 19 1>;
119 + interrupts = <0 19 4>;
122 clocks = <&apb1_gates 22>;
124 uart7: serial@01c29c00 {
125 compatible = "snps,dw-apb-uart";
126 reg = <0x01c29c00 0x400>;
127 - interrupts = <0 20 1>;
128 + interrupts = <0 20 4>;
131 clocks = <&apb1_gates 23>;
134 compatible = "allwinner,sun4i-i2c";
135 reg = <0x01c2ac00 0x400>;
136 - interrupts = <0 7 1>;
137 + interrupts = <0 7 4>;
138 clocks = <&apb1_gates 0>;
139 clock-frequency = <100000>;
143 compatible = "allwinner,sun4i-i2c";
144 reg = <0x01c2b000 0x400>;
145 - interrupts = <0 8 1>;
146 + interrupts = <0 8 4>;
147 clocks = <&apb1_gates 1>;
148 clock-frequency = <100000>;
152 compatible = "allwinner,sun4i-i2c";
153 reg = <0x01c2b400 0x400>;
154 - interrupts = <0 9 1>;
155 + interrupts = <0 9 4>;
156 clocks = <&apb1_gates 2>;
157 clock-frequency = <100000>;
161 compatible = "allwinner,sun4i-i2c";
162 reg = <0x01c2b800 0x400>;
163 - interrupts = <0 88 1>;
164 + interrupts = <0 88 4>;
165 clocks = <&apb1_gates 3>;
166 clock-frequency = <100000>;
170 compatible = "allwinner,sun4i-i2c";
171 reg = <0x01c2bc00 0x400>;
172 - interrupts = <0 89 1>;
173 + interrupts = <0 89 4>;
174 clocks = <&apb1_gates 15>;
175 clock-frequency = <100000>;