target/linux/sunxi/patches-3.13/108-sun6i-add-smp-support.patch

   1 From 6f5002c91f35f6b171bc608b87b3f2b55451f32b Mon Sep 17 00:00:00 2001
   2 From: Maxime Ripard <maxime.ripard@free-electrons.com>
   3 Date: Sun, 3 Nov 2013 10:30:13 +0100
   4 Subject: [PATCH] ARM: sun6i: Add SMP support for the Allwinner A31
   5
   6 The A31 is a quad Cortex-A7. Add the logic to use the IPs used to
   7 control the CPU configuration and the CPU power so that we can bring up
   8 secondary CPUs at boot.
   9
  10 Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
  11 ---
  12  arch/arm/mach-sunxi/Makefile  |   1 +
  13  arch/arm/mach-sunxi/common.h  |  19 +++++++
  14  arch/arm/mach-sunxi/headsmp.S |   9 +++
  15  arch/arm/mach-sunxi/platsmp.c | 124 ++++++++++++++++++++++++++++++++++++++++++
  16  arch/arm/mach-sunxi/sunxi.c   |   3 +
  17  5 files changed, 156 insertions(+)
  18  create mode 100644 arch/arm/mach-sunxi/common.h
  19  create mode 100644 arch/arm/mach-sunxi/headsmp.S
  20  create mode 100644 arch/arm/mach-sunxi/platsmp.c
  21
  22 diff --git a/arch/arm/mach-sunxi/Makefile b/arch/arm/mach-sunxi/Makefile
  23 index 93bebfc..d939720 100644
  24 --- a/arch/arm/mach-sunxi/Makefile
  25 +++ b/arch/arm/mach-sunxi/Makefile
  26 @@ -1 +1,2 @@
  27  obj-$(CONFIG_ARCH_SUNXI) += sunxi.o
  28 +obj-$(CONFIG_SMP) += platsmp.o headsmp.o
  29 diff --git a/arch/arm/mach-sunxi/common.h b/arch/arm/mach-sunxi/common.h
  30 new file mode 100644
  31 index 0000000..9e5ac47
  32 --- /dev/null
  33 +++ b/arch/arm/mach-sunxi/common.h
  34 @@ -0,0 +1,19 @@
  35 +/*
  36 + * Core functions for Allwinner SoCs
  37 + *
  38 + * Copyright (C) 2013 Maxime Ripard
  39 + *
  40 + * Maxime Ripard <maxime.ripard@free-electrons.com>
  41 + *
  42 + * This file is licensed under the terms of the GNU General Public
  43 + * License version 2.  This program is licensed "as is" without any
  44 + * warranty of any kind, whether express or implied.
  45 + */
  46 +
  47 +#ifndef __ARCH_SUNXI_COMMON_H_
  48 +#define __ARCH_SUNXI_COMMON_H_
  49 +
  50 +void sun6i_secondary_startup(void);
  51 +extern struct smp_operations sun6i_smp_ops;
  52 +
  53 +#endif /* __ARCH_SUNXI_COMMON_H_ */
  54 diff --git a/arch/arm/mach-sunxi/headsmp.S b/arch/arm/mach-sunxi/headsmp.S
  55 new file mode 100644
  56 index 0000000..a10d494
  57 --- /dev/null
  58 +++ b/arch/arm/mach-sunxi/headsmp.S
  59 @@ -0,0 +1,9 @@
  60 +#include <linux/linkage.h>
  61 +#include <linux/init.h>
  62 +
  63 +        .section ".text.head", "ax"
  64 +
  65 +ENTRY(sun6i_secondary_startup)
  66 +       msr     cpsr_fsxc, #0xd3
  67 +       b       secondary_startup
  68 +ENDPROC(sun6i_secondary_startup)
  69 diff --git a/arch/arm/mach-sunxi/platsmp.c b/arch/arm/mach-sunxi/platsmp.c
  70 new file mode 100644
  71 index 0000000..7b141d8
  72 --- /dev/null
  73 +++ b/arch/arm/mach-sunxi/platsmp.c
  74 @@ -0,0 +1,124 @@
  75 +/*
  76 + * SMP support for Allwinner SoCs
  77 + *
  78 + * Copyright (C) 2013 Maxime Ripard
  79 + *
  80 + * Maxime Ripard <maxime.ripard@free-electrons.com>
  81 + *
  82 + * Based on code
  83 + *  Copyright (C) 2012-2013 Allwinner Ltd.
  84 + *
  85 + * This file is licensed under the terms of the GNU General Public
  86 + * License version 2.  This program is licensed "as is" without any
  87 + * warranty of any kind, whether express or implied.
  88 + */
  89 +
  90 +#include <linux/delay.h>
  91 +#include <linux/init.h>
  92 +#include <linux/io.h>
  93 +#include <linux/memory.h>
  94 +#include <linux/of.h>
  95 +#include <linux/of_address.h>
  96 +#include <linux/smp.h>
  97 +
  98 +#include "common.h"
  99 +
 100 +#define CPUCFG_CPU_PWR_CLAMP_STATUS_REG(cpu)   ((cpu) * 0x40 + 0x64)
 101 +#define CPUCFG_CPU_RST_CTRL_REG(cpu)           (((cpu) + 1) * 0x40)
 102 +#define CPUCFG_CPU_CTRL_REG(cpu)               (((cpu) + 1) * 0x40 + 0x04)
 103 +#define CPUCFG_CPU_STATUS_REG(cpu)             (((cpu) + 1) * 0x40 + 0x08)
 104 +#define CPUCFG_GEN_CTRL_REG                    0x184
 105 +#define CPUCFG_PRIVATE0_REG                    0x1a4
 106 +#define CPUCFG_PRIVATE1_REG                    0x1a8
 107 +#define CPUCFG_DBG_CTL0_REG                    0x1e0
 108 +#define CPUCFG_DBG_CTL1_REG                    0x1e4
 109 +
 110 +#define PRCM_CPU_PWROFF_REG                    0x100
 111 +#define PRCM_CPU_PWR_CLAMP_REG(cpu)            (((cpu) * 4) + 0x140)
 112 +
 113 +static void __iomem *cpucfg_membase;
 114 +static void __iomem *prcm_membase;
 115 +
 116 +static DEFINE_SPINLOCK(cpu_lock);
 117 +
 118 +static void __init sun6i_smp_prepare_cpus(unsigned int max_cpus)
 119 +{
 120 +       struct device_node *node;
 121 +
 122 +       node = of_find_compatible_node(NULL, NULL, "allwinner,sun6i-a31-prcm");
 123 +       if (!node) {
 124 +               pr_err("Missing A31 PRCM node in the device tree\n");
 125 +               return;
 126 +       }
 127 +
 128 +       prcm_membase = of_iomap(node, 0);
 129 +       if (!prcm_membase) {
 130 +               pr_err("Couldn't map A31 PRCM registers\n");
 131 +               return;
 132 +       }
 133 +
 134 +       node = of_find_compatible_node(NULL, NULL,
 135 +                                      "allwinner,sun6i-a31-cpuconfig");
 136 +       if (!node) {
 137 +               pr_err("Missing A31 CPU config node in the device tree\n");
 138 +               return;
 139 +       }
 140 +
 141 +       cpucfg_membase = of_iomap(node, 0);
 142 +       if (!cpucfg_membase)
 143 +               pr_err("Couldn't map A31 CPU config registers\n");
 144 +
 145 +}
 146 +
 147 +static int sun6i_smp_boot_secondary(unsigned int cpu,
 148 +                                   struct task_struct *idle)
 149 +{
 150 +       u32 reg;
 151 +       int i;
 152 +
 153 +       if (!(prcm_membase && cpucfg_membase))
 154 +               return -EFAULT;
 155 +
 156 +       spin_lock(&cpu_lock);
 157 +
 158 +       /* Set CPU boot address */
 159 +       writel(virt_to_phys(sun6i_secondary_startup),
 160 +              cpucfg_membase + CPUCFG_PRIVATE0_REG);
 161 +
 162 +       /* Assert the CPU core in reset */
 163 +       writel(0, cpucfg_membase + CPUCFG_CPU_RST_CTRL_REG(cpu));
 164 +
 165 +       /* Assert the L1 cache in reset */
 166 +       reg = readl(cpucfg_membase + CPUCFG_GEN_CTRL_REG);
 167 +       writel(reg & ~BIT(cpu), cpucfg_membase + CPUCFG_GEN_CTRL_REG);
 168 +
 169 +       /* Disable external debug access */
 170 +       reg = readl(cpucfg_membase + CPUCFG_DBG_CTL1_REG);
 171 +       writel(reg & ~BIT(cpu), cpucfg_membase + CPUCFG_DBG_CTL1_REG);
 172 +
 173 +       /* Power up the CPU */
 174 +       for (i = 0; i <= 8; i++)
 175 +               writel(0xff >> i, prcm_membase + PRCM_CPU_PWR_CLAMP_REG(cpu));
 176 +       mdelay(10);
 177 +
 178 +       /* Clear CPU power-off gating */
 179 +       reg = readl(prcm_membase + PRCM_CPU_PWROFF_REG);
 180 +       writel(reg & ~BIT(cpu), prcm_membase + PRCM_CPU_PWROFF_REG);
 181 +       mdelay(1);
 182 +
 183 +       /* Deassert the CPU core reset */
 184 +       writel(3, cpucfg_membase + CPUCFG_CPU_RST_CTRL_REG(cpu));
 185 +
 186 +       /* Enable back the external debug accesses */
 187 +       reg = readl(cpucfg_membase + CPUCFG_DBG_CTL1_REG);
 188 +       writel(reg | BIT(cpu), cpucfg_membase + CPUCFG_DBG_CTL1_REG);
 189 +
 190 +       spin_unlock(&cpu_lock);
 191 +
 192 +       return 0;
 193 +}
 194 +
 195 +struct smp_operations sun6i_smp_ops __initdata = {
 196 +       .smp_prepare_cpus       = sun6i_smp_prepare_cpus,
 197 +       .smp_boot_secondary     = sun6i_smp_boot_secondary,
 198 +};
 199 diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
 200 index 594ac48..aeea6ce 100644
 201 --- a/arch/arm/mach-sunxi/sunxi.c
 202 +++ b/arch/arm/mach-sunxi/sunxi.c
 203 @@ -25,6 +25,8 @@
 204  #include <asm/mach/map.h>
 205  #include <asm/system_misc.h>
 206
 207 +#include "common.h"
 208 +
 209  #define SUN4I_WATCHDOG_CTRL_REG                0x00
 210  #define SUN4I_WATCHDOG_CTRL_RESTART            BIT(0)
 211  #define SUN4I_WATCHDOG_MODE_REG                0x04
 212 @@ -147,6 +149,7 @@ static void __init sun6i_timer_init(void)
 213         .init_time      = sun6i_timer_init,
 214         .dt_compat      = sun6i_board_dt_compat,
 215         .restart        = sun6i_restart,
 216 +       .smp            = smp_ops(sun6i_smp_ops),
 217  MACHINE_END
 218
 219  static const char * const sun7i_board_dt_compat[] = {
 220 --
 221 1.8.5.1
 222