1 From 46b2ee17d7321149b4d48dd86ee2e346624aa141 Mon Sep 17 00:00:00 2001
2 From: Maxime Ripard <maxime.ripard@free-electrons.com>
3 Date: Thu, 6 Feb 2014 09:55:58 +0100
4 Subject: [PATCH] ARM: sunxi: dt: Convert to the new clock compatibles
6 Switch the device tree to the new compatibles introduced in the clock drivers
7 to have a common pattern accross all Allwinner SoCs.
9 Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
11 arch/arm/boot/dts/sun4i-a10.dtsi | 60 +++++++++++++++++++--------------------
12 arch/arm/boot/dts/sun5i-a10s.dtsi | 48 +++++++++++++++----------------
13 arch/arm/boot/dts/sun5i-a13.dtsi | 48 +++++++++++++++----------------
14 arch/arm/boot/dts/sun6i-a31.dtsi | 10 +++----
15 arch/arm/boot/dts/sun7i-a20.dtsi | 54 +++++++++++++++++------------------
16 5 files changed, 110 insertions(+), 110 deletions(-)
18 --- a/arch/arm/boot/dts/sun4i-a10.dtsi
19 +++ b/arch/arm/boot/dts/sun4i-a10.dtsi
22 osc24M: clk@01c20050 {
24 - compatible = "allwinner,sun4i-osc-clk";
25 + compatible = "allwinner,sun4i-a10-osc-clk";
26 reg = <0x01c20050 0x4>;
27 clock-frequency = <24000000>;
28 clock-output-names = "osc24M";
33 - compatible = "allwinner,sun4i-pll1-clk";
34 + compatible = "allwinner,sun4i-a10-pll1-clk";
35 reg = <0x01c20000 0x4>;
37 clock-output-names = "pll1";
42 - compatible = "allwinner,sun4i-pll1-clk";
43 + compatible = "allwinner,sun4i-a10-pll1-clk";
44 reg = <0x01c20018 0x4>;
46 clock-output-names = "pll4";
51 - compatible = "allwinner,sun4i-pll5-clk";
52 + compatible = "allwinner,sun4i-a10-pll5-clk";
53 reg = <0x01c20020 0x4>;
55 clock-output-names = "pll5_ddr", "pll5_other";
60 - compatible = "allwinner,sun4i-pll6-clk";
61 + compatible = "allwinner,sun4i-a10-pll6-clk";
62 reg = <0x01c20028 0x4>;
64 clock-output-names = "pll6_sata", "pll6_other", "pll6";
69 - compatible = "allwinner,sun4i-cpu-clk";
70 + compatible = "allwinner,sun4i-a10-cpu-clk";
71 reg = <0x01c20054 0x4>;
72 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
73 clock-output-names = "cpu";
78 - compatible = "allwinner,sun4i-axi-clk";
79 + compatible = "allwinner,sun4i-a10-axi-clk";
80 reg = <0x01c20054 0x4>;
82 clock-output-names = "axi";
85 axi_gates: clk@01c2005c {
87 - compatible = "allwinner,sun4i-axi-gates-clk";
88 + compatible = "allwinner,sun4i-a10-axi-gates-clk";
89 reg = <0x01c2005c 0x4>;
91 clock-output-names = "axi_dram";
96 - compatible = "allwinner,sun4i-ahb-clk";
97 + compatible = "allwinner,sun4i-a10-ahb-clk";
98 reg = <0x01c20054 0x4>;
100 clock-output-names = "ahb";
103 ahb_gates: clk@01c20060 {
105 - compatible = "allwinner,sun4i-ahb-gates-clk";
106 + compatible = "allwinner,sun4i-a10-ahb-gates-clk";
107 reg = <0x01c20060 0x8>;
109 clock-output-names = "ahb_usb0", "ahb_ehci0",
112 apb0: apb0@01c20054 {
114 - compatible = "allwinner,sun4i-apb0-clk";
115 + compatible = "allwinner,sun4i-a10-apb0-clk";
116 reg = <0x01c20054 0x4>;
118 clock-output-names = "apb0";
121 apb0_gates: clk@01c20068 {
123 - compatible = "allwinner,sun4i-apb0-gates-clk";
124 + compatible = "allwinner,sun4i-a10-apb0-gates-clk";
125 reg = <0x01c20068 0x4>;
127 clock-output-names = "apb0_codec", "apb0_spdif",
130 apb1_mux: apb1_mux@01c20058 {
132 - compatible = "allwinner,sun4i-apb1-mux-clk";
133 + compatible = "allwinner,sun4i-a10-apb1-mux-clk";
134 reg = <0x01c20058 0x4>;
135 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
136 clock-output-names = "apb1_mux";
139 apb1: apb1@01c20058 {
141 - compatible = "allwinner,sun4i-apb1-clk";
142 + compatible = "allwinner,sun4i-a10-apb1-clk";
143 reg = <0x01c20058 0x4>;
144 clocks = <&apb1_mux>;
145 clock-output-names = "apb1";
148 apb1_gates: clk@01c2006c {
150 - compatible = "allwinner,sun4i-apb1-gates-clk";
151 + compatible = "allwinner,sun4i-a10-apb1-gates-clk";
152 reg = <0x01c2006c 0x4>;
154 clock-output-names = "apb1_i2c0", "apb1_i2c1",
157 nand_clk: clk@01c20080 {
159 - compatible = "allwinner,sun4i-mod0-clk";
160 + compatible = "allwinner,sun4i-a10-mod0-clk";
161 reg = <0x01c20080 0x4>;
162 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
163 clock-output-names = "nand";
166 ms_clk: clk@01c20084 {
168 - compatible = "allwinner,sun4i-mod0-clk";
169 + compatible = "allwinner,sun4i-a10-mod0-clk";
170 reg = <0x01c20084 0x4>;
171 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
172 clock-output-names = "ms";
175 mmc0_clk: clk@01c20088 {
177 - compatible = "allwinner,sun4i-mod0-clk";
178 + compatible = "allwinner,sun4i-a10-mod0-clk";
179 reg = <0x01c20088 0x4>;
180 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
181 clock-output-names = "mmc0";
184 mmc1_clk: clk@01c2008c {
186 - compatible = "allwinner,sun4i-mod0-clk";
187 + compatible = "allwinner,sun4i-a10-mod0-clk";
188 reg = <0x01c2008c 0x4>;
189 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
190 clock-output-names = "mmc1";
193 mmc2_clk: clk@01c20090 {
195 - compatible = "allwinner,sun4i-mod0-clk";
196 + compatible = "allwinner,sun4i-a10-mod0-clk";
197 reg = <0x01c20090 0x4>;
198 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
199 clock-output-names = "mmc2";
202 mmc3_clk: clk@01c20094 {
204 - compatible = "allwinner,sun4i-mod0-clk";
205 + compatible = "allwinner,sun4i-a10-mod0-clk";
206 reg = <0x01c20094 0x4>;
207 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
208 clock-output-names = "mmc3";
211 ts_clk: clk@01c20098 {
213 - compatible = "allwinner,sun4i-mod0-clk";
214 + compatible = "allwinner,sun4i-a10-mod0-clk";
215 reg = <0x01c20098 0x4>;
216 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
217 clock-output-names = "ts";
220 ss_clk: clk@01c2009c {
222 - compatible = "allwinner,sun4i-mod0-clk";
223 + compatible = "allwinner,sun4i-a10-mod0-clk";
224 reg = <0x01c2009c 0x4>;
225 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
226 clock-output-names = "ss";
229 spi0_clk: clk@01c200a0 {
231 - compatible = "allwinner,sun4i-mod0-clk";
232 + compatible = "allwinner,sun4i-a10-mod0-clk";
233 reg = <0x01c200a0 0x4>;
234 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
235 clock-output-names = "spi0";
238 spi1_clk: clk@01c200a4 {
240 - compatible = "allwinner,sun4i-mod0-clk";
241 + compatible = "allwinner,sun4i-a10-mod0-clk";
242 reg = <0x01c200a4 0x4>;
243 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
244 clock-output-names = "spi1";
247 spi2_clk: clk@01c200a8 {
249 - compatible = "allwinner,sun4i-mod0-clk";
250 + compatible = "allwinner,sun4i-a10-mod0-clk";
251 reg = <0x01c200a8 0x4>;
252 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
253 clock-output-names = "spi2";
256 pata_clk: clk@01c200ac {
258 - compatible = "allwinner,sun4i-mod0-clk";
259 + compatible = "allwinner,sun4i-a10-mod0-clk";
260 reg = <0x01c200ac 0x4>;
261 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
262 clock-output-names = "pata";
265 ir0_clk: clk@01c200b0 {
267 - compatible = "allwinner,sun4i-mod0-clk";
268 + compatible = "allwinner,sun4i-a10-mod0-clk";
269 reg = <0x01c200b0 0x4>;
270 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
271 clock-output-names = "ir0";
274 ir1_clk: clk@01c200b4 {
276 - compatible = "allwinner,sun4i-mod0-clk";
277 + compatible = "allwinner,sun4i-a10-mod0-clk";
278 reg = <0x01c200b4 0x4>;
279 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
280 clock-output-names = "ir1";
283 spi3_clk: clk@01c200d4 {
285 - compatible = "allwinner,sun4i-mod0-clk";
286 + compatible = "allwinner,sun4i-a10-mod0-clk";
287 reg = <0x01c200d4 0x4>;
288 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
289 clock-output-names = "spi3";
290 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi
291 +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
294 osc24M: clk@01c20050 {
296 - compatible = "allwinner,sun4i-osc-clk";
297 + compatible = "allwinner,sun4i-a10-osc-clk";
298 reg = <0x01c20050 0x4>;
299 clock-frequency = <24000000>;
300 clock-output-names = "osc24M";
305 - compatible = "allwinner,sun4i-pll1-clk";
306 + compatible = "allwinner,sun4i-a10-pll1-clk";
307 reg = <0x01c20000 0x4>;
309 clock-output-names = "pll1";
314 - compatible = "allwinner,sun4i-pll1-clk";
315 + compatible = "allwinner,sun4i-a10-pll1-clk";
316 reg = <0x01c20018 0x4>;
318 clock-output-names = "pll4";
323 - compatible = "allwinner,sun4i-pll5-clk";
324 + compatible = "allwinner,sun4i-a10-pll5-clk";
325 reg = <0x01c20020 0x4>;
327 clock-output-names = "pll5_ddr", "pll5_other";
332 - compatible = "allwinner,sun4i-pll6-clk";
333 + compatible = "allwinner,sun4i-a10-pll6-clk";
334 reg = <0x01c20028 0x4>;
336 clock-output-names = "pll6_sata", "pll6_other", "pll6";
341 - compatible = "allwinner,sun4i-cpu-clk";
342 + compatible = "allwinner,sun4i-a10-cpu-clk";
343 reg = <0x01c20054 0x4>;
344 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
345 clock-output-names = "cpu";
350 - compatible = "allwinner,sun4i-axi-clk";
351 + compatible = "allwinner,sun4i-a10-axi-clk";
352 reg = <0x01c20054 0x4>;
354 clock-output-names = "axi";
357 axi_gates: clk@01c2005c {
359 - compatible = "allwinner,sun4i-axi-gates-clk";
360 + compatible = "allwinner,sun4i-a10-axi-gates-clk";
361 reg = <0x01c2005c 0x4>;
363 clock-output-names = "axi_dram";
368 - compatible = "allwinner,sun4i-ahb-clk";
369 + compatible = "allwinner,sun4i-a10-ahb-clk";
370 reg = <0x01c20054 0x4>;
372 clock-output-names = "ahb";
375 apb0: apb0@01c20054 {
377 - compatible = "allwinner,sun4i-apb0-clk";
378 + compatible = "allwinner,sun4i-a10-apb0-clk";
379 reg = <0x01c20054 0x4>;
381 clock-output-names = "apb0";
384 apb1_mux: apb1_mux@01c20058 {
386 - compatible = "allwinner,sun4i-apb1-mux-clk";
387 + compatible = "allwinner,sun4i-a10-apb1-mux-clk";
388 reg = <0x01c20058 0x4>;
389 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
390 clock-output-names = "apb1_mux";
393 apb1: apb1@01c20058 {
395 - compatible = "allwinner,sun4i-apb1-clk";
396 + compatible = "allwinner,sun4i-a10-apb1-clk";
397 reg = <0x01c20058 0x4>;
398 clocks = <&apb1_mux>;
399 clock-output-names = "apb1";
402 nand_clk: clk@01c20080 {
404 - compatible = "allwinner,sun4i-mod0-clk";
405 + compatible = "allwinner,sun4i-a10-mod0-clk";
406 reg = <0x01c20080 0x4>;
407 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
408 clock-output-names = "nand";
411 ms_clk: clk@01c20084 {
413 - compatible = "allwinner,sun4i-mod0-clk";
414 + compatible = "allwinner,sun4i-a10-mod0-clk";
415 reg = <0x01c20084 0x4>;
416 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
417 clock-output-names = "ms";
420 mmc0_clk: clk@01c20088 {
422 - compatible = "allwinner,sun4i-mod0-clk";
423 + compatible = "allwinner,sun4i-a10-mod0-clk";
424 reg = <0x01c20088 0x4>;
425 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
426 clock-output-names = "mmc0";
429 mmc1_clk: clk@01c2008c {
431 - compatible = "allwinner,sun4i-mod0-clk";
432 + compatible = "allwinner,sun4i-a10-mod0-clk";
433 reg = <0x01c2008c 0x4>;
434 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
435 clock-output-names = "mmc1";
438 mmc2_clk: clk@01c20090 {
440 - compatible = "allwinner,sun4i-mod0-clk";
441 + compatible = "allwinner,sun4i-a10-mod0-clk";
442 reg = <0x01c20090 0x4>;
443 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
444 clock-output-names = "mmc2";
447 ts_clk: clk@01c20098 {
449 - compatible = "allwinner,sun4i-mod0-clk";
450 + compatible = "allwinner,sun4i-a10-mod0-clk";
451 reg = <0x01c20098 0x4>;
452 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
453 clock-output-names = "ts";
456 ss_clk: clk@01c2009c {
458 - compatible = "allwinner,sun4i-mod0-clk";
459 + compatible = "allwinner,sun4i-a10-mod0-clk";
460 reg = <0x01c2009c 0x4>;
461 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
462 clock-output-names = "ss";
465 spi0_clk: clk@01c200a0 {
467 - compatible = "allwinner,sun4i-mod0-clk";
468 + compatible = "allwinner,sun4i-a10-mod0-clk";
469 reg = <0x01c200a0 0x4>;
470 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
471 clock-output-names = "spi0";
474 spi1_clk: clk@01c200a4 {
476 - compatible = "allwinner,sun4i-mod0-clk";
477 + compatible = "allwinner,sun4i-a10-mod0-clk";
478 reg = <0x01c200a4 0x4>;
479 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
480 clock-output-names = "spi1";
483 spi2_clk: clk@01c200a8 {
485 - compatible = "allwinner,sun4i-mod0-clk";
486 + compatible = "allwinner,sun4i-a10-mod0-clk";
487 reg = <0x01c200a8 0x4>;
488 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
489 clock-output-names = "spi2";
492 ir0_clk: clk@01c200b0 {
494 - compatible = "allwinner,sun4i-mod0-clk";
495 + compatible = "allwinner,sun4i-a10-mod0-clk";
496 reg = <0x01c200b0 0x4>;
497 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
498 clock-output-names = "ir0";
501 mbus_clk: clk@01c2015c {
503 - compatible = "allwinner,sun4i-mod0-clk";
504 + compatible = "allwinner,sun4i-a10-mod0-clk";
505 reg = <0x01c2015c 0x4>;
506 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
507 clock-output-names = "mbus";
508 --- a/arch/arm/boot/dts/sun5i-a13.dtsi
509 +++ b/arch/arm/boot/dts/sun5i-a13.dtsi
512 osc24M: clk@01c20050 {
514 - compatible = "allwinner,sun4i-osc-clk";
515 + compatible = "allwinner,sun4i-a10-osc-clk";
516 reg = <0x01c20050 0x4>;
517 clock-frequency = <24000000>;
518 clock-output-names = "osc24M";
523 - compatible = "allwinner,sun4i-pll1-clk";
524 + compatible = "allwinner,sun4i-a10-pll1-clk";
525 reg = <0x01c20000 0x4>;
527 clock-output-names = "pll1";
532 - compatible = "allwinner,sun4i-pll1-clk";
533 + compatible = "allwinner,sun4i-a10-pll1-clk";
534 reg = <0x01c20018 0x4>;
536 clock-output-names = "pll4";
541 - compatible = "allwinner,sun4i-pll5-clk";
542 + compatible = "allwinner,sun4i-a10-pll5-clk";
543 reg = <0x01c20020 0x4>;
545 clock-output-names = "pll5_ddr", "pll5_other";
550 - compatible = "allwinner,sun4i-pll6-clk";
551 + compatible = "allwinner,sun4i-a10-pll6-clk";
552 reg = <0x01c20028 0x4>;
554 clock-output-names = "pll6_sata", "pll6_other", "pll6";
559 - compatible = "allwinner,sun4i-cpu-clk";
560 + compatible = "allwinner,sun4i-a10-cpu-clk";
561 reg = <0x01c20054 0x4>;
562 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
563 clock-output-names = "cpu";
568 - compatible = "allwinner,sun4i-axi-clk";
569 + compatible = "allwinner,sun4i-a10-axi-clk";
570 reg = <0x01c20054 0x4>;
572 clock-output-names = "axi";
575 axi_gates: clk@01c2005c {
577 - compatible = "allwinner,sun4i-axi-gates-clk";
578 + compatible = "allwinner,sun4i-a10-axi-gates-clk";
579 reg = <0x01c2005c 0x4>;
581 clock-output-names = "axi_dram";
586 - compatible = "allwinner,sun4i-ahb-clk";
587 + compatible = "allwinner,sun4i-a10-ahb-clk";
588 reg = <0x01c20054 0x4>;
590 clock-output-names = "ahb";
593 apb0: apb0@01c20054 {
595 - compatible = "allwinner,sun4i-apb0-clk";
596 + compatible = "allwinner,sun4i-a10-apb0-clk";
597 reg = <0x01c20054 0x4>;
599 clock-output-names = "apb0";
602 apb1_mux: apb1_mux@01c20058 {
604 - compatible = "allwinner,sun4i-apb1-mux-clk";
605 + compatible = "allwinner,sun4i-a10-apb1-mux-clk";
606 reg = <0x01c20058 0x4>;
607 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
608 clock-output-names = "apb1_mux";
611 apb1: apb1@01c20058 {
613 - compatible = "allwinner,sun4i-apb1-clk";
614 + compatible = "allwinner,sun4i-a10-apb1-clk";
615 reg = <0x01c20058 0x4>;
616 clocks = <&apb1_mux>;
617 clock-output-names = "apb1";
620 nand_clk: clk@01c20080 {
622 - compatible = "allwinner,sun4i-mod0-clk";
623 + compatible = "allwinner,sun4i-a10-mod0-clk";
624 reg = <0x01c20080 0x4>;
625 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
626 clock-output-names = "nand";
629 ms_clk: clk@01c20084 {
631 - compatible = "allwinner,sun4i-mod0-clk";
632 + compatible = "allwinner,sun4i-a10-mod0-clk";
633 reg = <0x01c20084 0x4>;
634 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
635 clock-output-names = "ms";
638 mmc0_clk: clk@01c20088 {
640 - compatible = "allwinner,sun4i-mod0-clk";
641 + compatible = "allwinner,sun4i-a10-mod0-clk";
642 reg = <0x01c20088 0x4>;
643 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
644 clock-output-names = "mmc0";
647 mmc1_clk: clk@01c2008c {
649 - compatible = "allwinner,sun4i-mod0-clk";
650 + compatible = "allwinner,sun4i-a10-mod0-clk";
651 reg = <0x01c2008c 0x4>;
652 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
653 clock-output-names = "mmc1";
656 mmc2_clk: clk@01c20090 {
658 - compatible = "allwinner,sun4i-mod0-clk";
659 + compatible = "allwinner,sun4i-a10-mod0-clk";
660 reg = <0x01c20090 0x4>;
661 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
662 clock-output-names = "mmc2";
665 ts_clk: clk@01c20098 {
667 - compatible = "allwinner,sun4i-mod0-clk";
668 + compatible = "allwinner,sun4i-a10-mod0-clk";
669 reg = <0x01c20098 0x4>;
670 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
671 clock-output-names = "ts";
674 ss_clk: clk@01c2009c {
676 - compatible = "allwinner,sun4i-mod0-clk";
677 + compatible = "allwinner,sun4i-a10-mod0-clk";
678 reg = <0x01c2009c 0x4>;
679 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
680 clock-output-names = "ss";
683 spi0_clk: clk@01c200a0 {
685 - compatible = "allwinner,sun4i-mod0-clk";
686 + compatible = "allwinner,sun4i-a10-mod0-clk";
687 reg = <0x01c200a0 0x4>;
688 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
689 clock-output-names = "spi0";
692 spi1_clk: clk@01c200a4 {
694 - compatible = "allwinner,sun4i-mod0-clk";
695 + compatible = "allwinner,sun4i-a10-mod0-clk";
696 reg = <0x01c200a4 0x4>;
697 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
698 clock-output-names = "spi1";
701 spi2_clk: clk@01c200a8 {
703 - compatible = "allwinner,sun4i-mod0-clk";
704 + compatible = "allwinner,sun4i-a10-mod0-clk";
705 reg = <0x01c200a8 0x4>;
706 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
707 clock-output-names = "spi2";
710 ir0_clk: clk@01c200b0 {
712 - compatible = "allwinner,sun4i-mod0-clk";
713 + compatible = "allwinner,sun4i-a10-mod0-clk";
714 reg = <0x01c200b0 0x4>;
715 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
716 clock-output-names = "ir0";
719 mbus_clk: clk@01c2015c {
721 - compatible = "allwinner,sun4i-mod0-clk";
722 + compatible = "allwinner,sun4i-a10-mod0-clk";
723 reg = <0x01c2015c 0x4>;
724 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
725 clock-output-names = "mbus";
726 --- a/arch/arm/boot/dts/sun6i-a31.dtsi
727 +++ b/arch/arm/boot/dts/sun6i-a31.dtsi
732 - compatible = "allwinner,sun4i-cpu-clk";
733 + compatible = "allwinner,sun4i-a10-cpu-clk";
734 reg = <0x01c20050 0x4>;
741 - compatible = "allwinner,sun4i-axi-clk";
742 + compatible = "allwinner,sun4i-a10-axi-clk";
743 reg = <0x01c20050 0x4>;
745 clock-output-names = "axi";
748 ahb1: ahb1@01c20054 {
750 - compatible = "allwinner,sun4i-ahb-clk";
751 + compatible = "allwinner,sun4i-a10-ahb-clk";
752 reg = <0x01c20054 0x4>;
753 clocks = <&ahb1_mux>;
754 clock-output-names = "ahb1";
757 apb1: apb1@01c20054 {
759 - compatible = "allwinner,sun4i-apb0-clk";
760 + compatible = "allwinner,sun4i-a10-apb0-clk";
761 reg = <0x01c20054 0x4>;
763 clock-output-names = "apb1";
766 apb2_mux: apb2_mux@01c20058 {
768 - compatible = "allwinner,sun4i-apb1-mux-clk";
769 + compatible = "allwinner,sun4i-a10-apb1-mux-clk";
770 reg = <0x01c20058 0x4>;
771 clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
772 clock-output-names = "apb2_mux";
773 --- a/arch/arm/boot/dts/sun7i-a20.dtsi
774 +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
777 osc24M: clk@01c20050 {
779 - compatible = "allwinner,sun4i-osc-clk";
780 + compatible = "allwinner,sun4i-a10-osc-clk";
781 reg = <0x01c20050 0x4>;
782 clock-frequency = <24000000>;
783 clock-output-names = "osc24M";
788 - compatible = "allwinner,sun4i-pll1-clk";
789 + compatible = "allwinner,sun4i-a10-pll1-clk";
790 reg = <0x01c20000 0x4>;
792 clock-output-names = "pll1";
797 - compatible = "allwinner,sun4i-pll1-clk";
798 + compatible = "allwinner,sun4i-a10-pll1-clk";
799 reg = <0x01c20018 0x4>;
801 clock-output-names = "pll4";
806 - compatible = "allwinner,sun4i-pll5-clk";
807 + compatible = "allwinner,sun4i-a10-pll5-clk";
808 reg = <0x01c20020 0x4>;
810 clock-output-names = "pll5_ddr", "pll5_other";
815 - compatible = "allwinner,sun4i-pll6-clk";
816 + compatible = "allwinner,sun4i-a10-pll6-clk";
817 reg = <0x01c20028 0x4>;
819 clock-output-names = "pll6_sata", "pll6_other", "pll6";
824 - compatible = "allwinner,sun4i-cpu-clk";
825 + compatible = "allwinner,sun4i-a10-cpu-clk";
826 reg = <0x01c20054 0x4>;
827 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
828 clock-output-names = "cpu";
833 - compatible = "allwinner,sun4i-axi-clk";
834 + compatible = "allwinner,sun4i-a10-axi-clk";
835 reg = <0x01c20054 0x4>;
837 clock-output-names = "axi";
842 - compatible = "allwinner,sun4i-ahb-clk";
843 + compatible = "allwinner,sun4i-a10-ahb-clk";
844 reg = <0x01c20054 0x4>;
846 clock-output-names = "ahb";
849 apb0: apb0@01c20054 {
851 - compatible = "allwinner,sun4i-apb0-clk";
852 + compatible = "allwinner,sun4i-a10-apb0-clk";
853 reg = <0x01c20054 0x4>;
855 clock-output-names = "apb0";
858 apb1_mux: apb1_mux@01c20058 {
860 - compatible = "allwinner,sun4i-apb1-mux-clk";
861 + compatible = "allwinner,sun4i-a10-apb1-mux-clk";
862 reg = <0x01c20058 0x4>;
863 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
864 clock-output-names = "apb1_mux";
867 apb1: apb1@01c20058 {
869 - compatible = "allwinner,sun4i-apb1-clk";
870 + compatible = "allwinner,sun4i-a10-apb1-clk";
871 reg = <0x01c20058 0x4>;
872 clocks = <&apb1_mux>;
873 clock-output-names = "apb1";
876 nand_clk: clk@01c20080 {
878 - compatible = "allwinner,sun4i-mod0-clk";
879 + compatible = "allwinner,sun4i-a10-mod0-clk";
880 reg = <0x01c20080 0x4>;
881 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
882 clock-output-names = "nand";
885 ms_clk: clk@01c20084 {
887 - compatible = "allwinner,sun4i-mod0-clk";
888 + compatible = "allwinner,sun4i-a10-mod0-clk";
889 reg = <0x01c20084 0x4>;
890 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
891 clock-output-names = "ms";
894 mmc0_clk: clk@01c20088 {
896 - compatible = "allwinner,sun4i-mod0-clk";
897 + compatible = "allwinner,sun4i-a10-mod0-clk";
898 reg = <0x01c20088 0x4>;
899 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
900 clock-output-names = "mmc0";
903 mmc1_clk: clk@01c2008c {
905 - compatible = "allwinner,sun4i-mod0-clk";
906 + compatible = "allwinner,sun4i-a10-mod0-clk";
907 reg = <0x01c2008c 0x4>;
908 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
909 clock-output-names = "mmc1";
912 mmc2_clk: clk@01c20090 {
914 - compatible = "allwinner,sun4i-mod0-clk";
915 + compatible = "allwinner,sun4i-a10-mod0-clk";
916 reg = <0x01c20090 0x4>;
917 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
918 clock-output-names = "mmc2";
921 mmc3_clk: clk@01c20094 {
923 - compatible = "allwinner,sun4i-mod0-clk";
924 + compatible = "allwinner,sun4i-a10-mod0-clk";
925 reg = <0x01c20094 0x4>;
926 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
927 clock-output-names = "mmc3";
930 ts_clk: clk@01c20098 {
932 - compatible = "allwinner,sun4i-mod0-clk";
933 + compatible = "allwinner,sun4i-a10-mod0-clk";
934 reg = <0x01c20098 0x4>;
935 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
936 clock-output-names = "ts";
939 ss_clk: clk@01c2009c {
941 - compatible = "allwinner,sun4i-mod0-clk";
942 + compatible = "allwinner,sun4i-a10-mod0-clk";
943 reg = <0x01c2009c 0x4>;
944 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
945 clock-output-names = "ss";
948 spi0_clk: clk@01c200a0 {
950 - compatible = "allwinner,sun4i-mod0-clk";
951 + compatible = "allwinner,sun4i-a10-mod0-clk";
952 reg = <0x01c200a0 0x4>;
953 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
954 clock-output-names = "spi0";
957 spi1_clk: clk@01c200a4 {
959 - compatible = "allwinner,sun4i-mod0-clk";
960 + compatible = "allwinner,sun4i-a10-mod0-clk";
961 reg = <0x01c200a4 0x4>;
962 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
963 clock-output-names = "spi1";
966 spi2_clk: clk@01c200a8 {
968 - compatible = "allwinner,sun4i-mod0-clk";
969 + compatible = "allwinner,sun4i-a10-mod0-clk";
970 reg = <0x01c200a8 0x4>;
971 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
972 clock-output-names = "spi2";
975 pata_clk: clk@01c200ac {
977 - compatible = "allwinner,sun4i-mod0-clk";
978 + compatible = "allwinner,sun4i-a10-mod0-clk";
979 reg = <0x01c200ac 0x4>;
980 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
981 clock-output-names = "pata";
984 ir0_clk: clk@01c200b0 {
986 - compatible = "allwinner,sun4i-mod0-clk";
987 + compatible = "allwinner,sun4i-a10-mod0-clk";
988 reg = <0x01c200b0 0x4>;
989 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
990 clock-output-names = "ir0";
993 ir1_clk: clk@01c200b4 {
995 - compatible = "allwinner,sun4i-mod0-clk";
996 + compatible = "allwinner,sun4i-a10-mod0-clk";
997 reg = <0x01c200b4 0x4>;
998 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
999 clock-output-names = "ir1";
1002 spi3_clk: clk@01c200d4 {
1004 - compatible = "allwinner,sun4i-mod0-clk";
1005 + compatible = "allwinner,sun4i-a10-mod0-clk";
1006 reg = <0x01c200d4 0x4>;
1007 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
1008 clock-output-names = "spi3";
1011 mbus_clk: clk@01c2015c {
1013 - compatible = "allwinner,sun4i-mod0-clk";
1014 + compatible = "allwinner,sun4i-a10-mod0-clk";
1015 reg = <0x01c2015c 0x4>;
1016 clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
1017 clock-output-names = "mbus";