1 From 46b2ee17d7321149b4d48dd86ee2e346624aa141 Mon Sep 17 00:00:00 2001
2 From: Maxime Ripard <maxime.ripard@free-electrons.com>
3 Date: Thu, 6 Feb 2014 09:55:58 +0100
4 Subject: [PATCH] ARM: sunxi: dt: Convert to the new clock compatibles
6 Switch the device tree to the new compatibles introduced in the clock drivers
7 to have a common pattern accross all Allwinner SoCs.
9 Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
11 arch/arm/boot/dts/sun4i-a10.dtsi | 60 +++++++++++++++++++--------------------
12 arch/arm/boot/dts/sun5i-a10s.dtsi | 48 +++++++++++++++----------------
13 arch/arm/boot/dts/sun5i-a13.dtsi | 48 +++++++++++++++----------------
14 arch/arm/boot/dts/sun6i-a31.dtsi | 10 +++----
15 arch/arm/boot/dts/sun7i-a20.dtsi | 54 +++++++++++++++++------------------
16 5 files changed, 110 insertions(+), 110 deletions(-)
18 diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
19 index 2d623d0..f6f41d6 100644
20 --- a/arch/arm/boot/dts/sun4i-a10.dtsi
21 +++ b/arch/arm/boot/dts/sun4i-a10.dtsi
24 osc24M: clk@01c20050 {
26 - compatible = "allwinner,sun4i-osc-clk";
27 + compatible = "allwinner,sun4i-a10-osc-clk";
28 reg = <0x01c20050 0x4>;
29 clock-frequency = <24000000>;
30 clock-output-names = "osc24M";
35 - compatible = "allwinner,sun4i-pll1-clk";
36 + compatible = "allwinner,sun4i-a10-pll1-clk";
37 reg = <0x01c20000 0x4>;
39 clock-output-names = "pll1";
44 - compatible = "allwinner,sun4i-pll1-clk";
45 + compatible = "allwinner,sun4i-a10-pll1-clk";
46 reg = <0x01c20018 0x4>;
48 clock-output-names = "pll4";
53 - compatible = "allwinner,sun4i-pll5-clk";
54 + compatible = "allwinner,sun4i-a10-pll5-clk";
55 reg = <0x01c20020 0x4>;
57 clock-output-names = "pll5_ddr", "pll5_other";
62 - compatible = "allwinner,sun4i-pll6-clk";
63 + compatible = "allwinner,sun4i-a10-pll6-clk";
64 reg = <0x01c20028 0x4>;
66 clock-output-names = "pll6_sata", "pll6_other", "pll6";
71 - compatible = "allwinner,sun4i-cpu-clk";
72 + compatible = "allwinner,sun4i-a10-cpu-clk";
73 reg = <0x01c20054 0x4>;
74 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
75 clock-output-names = "cpu";
80 - compatible = "allwinner,sun4i-axi-clk";
81 + compatible = "allwinner,sun4i-a10-axi-clk";
82 reg = <0x01c20054 0x4>;
84 clock-output-names = "axi";
87 axi_gates: clk@01c2005c {
89 - compatible = "allwinner,sun4i-axi-gates-clk";
90 + compatible = "allwinner,sun4i-a10-axi-gates-clk";
91 reg = <0x01c2005c 0x4>;
93 clock-output-names = "axi_dram";
98 - compatible = "allwinner,sun4i-ahb-clk";
99 + compatible = "allwinner,sun4i-a10-ahb-clk";
100 reg = <0x01c20054 0x4>;
102 clock-output-names = "ahb";
105 ahb_gates: clk@01c20060 {
107 - compatible = "allwinner,sun4i-ahb-gates-clk";
108 + compatible = "allwinner,sun4i-a10-ahb-gates-clk";
109 reg = <0x01c20060 0x8>;
111 clock-output-names = "ahb_usb0", "ahb_ehci0",
114 apb0: apb0@01c20054 {
116 - compatible = "allwinner,sun4i-apb0-clk";
117 + compatible = "allwinner,sun4i-a10-apb0-clk";
118 reg = <0x01c20054 0x4>;
120 clock-output-names = "apb0";
123 apb0_gates: clk@01c20068 {
125 - compatible = "allwinner,sun4i-apb0-gates-clk";
126 + compatible = "allwinner,sun4i-a10-apb0-gates-clk";
127 reg = <0x01c20068 0x4>;
129 clock-output-names = "apb0_codec", "apb0_spdif",
132 apb1_mux: apb1_mux@01c20058 {
134 - compatible = "allwinner,sun4i-apb1-mux-clk";
135 + compatible = "allwinner,sun4i-a10-apb1-mux-clk";
136 reg = <0x01c20058 0x4>;
137 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
138 clock-output-names = "apb1_mux";
141 apb1: apb1@01c20058 {
143 - compatible = "allwinner,sun4i-apb1-clk";
144 + compatible = "allwinner,sun4i-a10-apb1-clk";
145 reg = <0x01c20058 0x4>;
146 clocks = <&apb1_mux>;
147 clock-output-names = "apb1";
150 apb1_gates: clk@01c2006c {
152 - compatible = "allwinner,sun4i-apb1-gates-clk";
153 + compatible = "allwinner,sun4i-a10-apb1-gates-clk";
154 reg = <0x01c2006c 0x4>;
156 clock-output-names = "apb1_i2c0", "apb1_i2c1",
159 nand_clk: clk@01c20080 {
161 - compatible = "allwinner,sun4i-mod0-clk";
162 + compatible = "allwinner,sun4i-a10-mod0-clk";
163 reg = <0x01c20080 0x4>;
164 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
165 clock-output-names = "nand";
168 ms_clk: clk@01c20084 {
170 - compatible = "allwinner,sun4i-mod0-clk";
171 + compatible = "allwinner,sun4i-a10-mod0-clk";
172 reg = <0x01c20084 0x4>;
173 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
174 clock-output-names = "ms";
177 mmc0_clk: clk@01c20088 {
179 - compatible = "allwinner,sun4i-mod0-clk";
180 + compatible = "allwinner,sun4i-a10-mod0-clk";
181 reg = <0x01c20088 0x4>;
182 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
183 clock-output-names = "mmc0";
186 mmc1_clk: clk@01c2008c {
188 - compatible = "allwinner,sun4i-mod0-clk";
189 + compatible = "allwinner,sun4i-a10-mod0-clk";
190 reg = <0x01c2008c 0x4>;
191 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
192 clock-output-names = "mmc1";
195 mmc2_clk: clk@01c20090 {
197 - compatible = "allwinner,sun4i-mod0-clk";
198 + compatible = "allwinner,sun4i-a10-mod0-clk";
199 reg = <0x01c20090 0x4>;
200 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
201 clock-output-names = "mmc2";
204 mmc3_clk: clk@01c20094 {
206 - compatible = "allwinner,sun4i-mod0-clk";
207 + compatible = "allwinner,sun4i-a10-mod0-clk";
208 reg = <0x01c20094 0x4>;
209 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
210 clock-output-names = "mmc3";
213 ts_clk: clk@01c20098 {
215 - compatible = "allwinner,sun4i-mod0-clk";
216 + compatible = "allwinner,sun4i-a10-mod0-clk";
217 reg = <0x01c20098 0x4>;
218 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
219 clock-output-names = "ts";
222 ss_clk: clk@01c2009c {
224 - compatible = "allwinner,sun4i-mod0-clk";
225 + compatible = "allwinner,sun4i-a10-mod0-clk";
226 reg = <0x01c2009c 0x4>;
227 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
228 clock-output-names = "ss";
231 spi0_clk: clk@01c200a0 {
233 - compatible = "allwinner,sun4i-mod0-clk";
234 + compatible = "allwinner,sun4i-a10-mod0-clk";
235 reg = <0x01c200a0 0x4>;
236 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
237 clock-output-names = "spi0";
240 spi1_clk: clk@01c200a4 {
242 - compatible = "allwinner,sun4i-mod0-clk";
243 + compatible = "allwinner,sun4i-a10-mod0-clk";
244 reg = <0x01c200a4 0x4>;
245 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
246 clock-output-names = "spi1";
249 spi2_clk: clk@01c200a8 {
251 - compatible = "allwinner,sun4i-mod0-clk";
252 + compatible = "allwinner,sun4i-a10-mod0-clk";
253 reg = <0x01c200a8 0x4>;
254 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
255 clock-output-names = "spi2";
258 pata_clk: clk@01c200ac {
260 - compatible = "allwinner,sun4i-mod0-clk";
261 + compatible = "allwinner,sun4i-a10-mod0-clk";
262 reg = <0x01c200ac 0x4>;
263 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
264 clock-output-names = "pata";
267 ir0_clk: clk@01c200b0 {
269 - compatible = "allwinner,sun4i-mod0-clk";
270 + compatible = "allwinner,sun4i-a10-mod0-clk";
271 reg = <0x01c200b0 0x4>;
272 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
273 clock-output-names = "ir0";
276 ir1_clk: clk@01c200b4 {
278 - compatible = "allwinner,sun4i-mod0-clk";
279 + compatible = "allwinner,sun4i-a10-mod0-clk";
280 reg = <0x01c200b4 0x4>;
281 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
282 clock-output-names = "ir1";
285 spi3_clk: clk@01c200d4 {
287 - compatible = "allwinner,sun4i-mod0-clk";
288 + compatible = "allwinner,sun4i-a10-mod0-clk";
289 reg = <0x01c200d4 0x4>;
290 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
291 clock-output-names = "spi3";
292 diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
293 index 905317e..df90a29 100644
294 --- a/arch/arm/boot/dts/sun5i-a10s.dtsi
295 +++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
298 osc24M: clk@01c20050 {
300 - compatible = "allwinner,sun4i-osc-clk";
301 + compatible = "allwinner,sun4i-a10-osc-clk";
302 reg = <0x01c20050 0x4>;
303 clock-frequency = <24000000>;
304 clock-output-names = "osc24M";
309 - compatible = "allwinner,sun4i-pll1-clk";
310 + compatible = "allwinner,sun4i-a10-pll1-clk";
311 reg = <0x01c20000 0x4>;
313 clock-output-names = "pll1";
318 - compatible = "allwinner,sun4i-pll1-clk";
319 + compatible = "allwinner,sun4i-a10-pll1-clk";
320 reg = <0x01c20018 0x4>;
322 clock-output-names = "pll4";
327 - compatible = "allwinner,sun4i-pll5-clk";
328 + compatible = "allwinner,sun4i-a10-pll5-clk";
329 reg = <0x01c20020 0x4>;
331 clock-output-names = "pll5_ddr", "pll5_other";
336 - compatible = "allwinner,sun4i-pll6-clk";
337 + compatible = "allwinner,sun4i-a10-pll6-clk";
338 reg = <0x01c20028 0x4>;
340 clock-output-names = "pll6_sata", "pll6_other", "pll6";
345 - compatible = "allwinner,sun4i-cpu-clk";
346 + compatible = "allwinner,sun4i-a10-cpu-clk";
347 reg = <0x01c20054 0x4>;
348 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
349 clock-output-names = "cpu";
354 - compatible = "allwinner,sun4i-axi-clk";
355 + compatible = "allwinner,sun4i-a10-axi-clk";
356 reg = <0x01c20054 0x4>;
358 clock-output-names = "axi";
361 axi_gates: clk@01c2005c {
363 - compatible = "allwinner,sun4i-axi-gates-clk";
364 + compatible = "allwinner,sun4i-a10-axi-gates-clk";
365 reg = <0x01c2005c 0x4>;
367 clock-output-names = "axi_dram";
372 - compatible = "allwinner,sun4i-ahb-clk";
373 + compatible = "allwinner,sun4i-a10-ahb-clk";
374 reg = <0x01c20054 0x4>;
376 clock-output-names = "ahb";
379 apb0: apb0@01c20054 {
381 - compatible = "allwinner,sun4i-apb0-clk";
382 + compatible = "allwinner,sun4i-a10-apb0-clk";
383 reg = <0x01c20054 0x4>;
385 clock-output-names = "apb0";
388 apb1_mux: apb1_mux@01c20058 {
390 - compatible = "allwinner,sun4i-apb1-mux-clk";
391 + compatible = "allwinner,sun4i-a10-apb1-mux-clk";
392 reg = <0x01c20058 0x4>;
393 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
394 clock-output-names = "apb1_mux";
397 apb1: apb1@01c20058 {
399 - compatible = "allwinner,sun4i-apb1-clk";
400 + compatible = "allwinner,sun4i-a10-apb1-clk";
401 reg = <0x01c20058 0x4>;
402 clocks = <&apb1_mux>;
403 clock-output-names = "apb1";
406 nand_clk: clk@01c20080 {
408 - compatible = "allwinner,sun4i-mod0-clk";
409 + compatible = "allwinner,sun4i-a10-mod0-clk";
410 reg = <0x01c20080 0x4>;
411 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
412 clock-output-names = "nand";
415 ms_clk: clk@01c20084 {
417 - compatible = "allwinner,sun4i-mod0-clk";
418 + compatible = "allwinner,sun4i-a10-mod0-clk";
419 reg = <0x01c20084 0x4>;
420 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
421 clock-output-names = "ms";
424 mmc0_clk: clk@01c20088 {
426 - compatible = "allwinner,sun4i-mod0-clk";
427 + compatible = "allwinner,sun4i-a10-mod0-clk";
428 reg = <0x01c20088 0x4>;
429 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
430 clock-output-names = "mmc0";
433 mmc1_clk: clk@01c2008c {
435 - compatible = "allwinner,sun4i-mod0-clk";
436 + compatible = "allwinner,sun4i-a10-mod0-clk";
437 reg = <0x01c2008c 0x4>;
438 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
439 clock-output-names = "mmc1";
442 mmc2_clk: clk@01c20090 {
444 - compatible = "allwinner,sun4i-mod0-clk";
445 + compatible = "allwinner,sun4i-a10-mod0-clk";
446 reg = <0x01c20090 0x4>;
447 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
448 clock-output-names = "mmc2";
451 ts_clk: clk@01c20098 {
453 - compatible = "allwinner,sun4i-mod0-clk";
454 + compatible = "allwinner,sun4i-a10-mod0-clk";
455 reg = <0x01c20098 0x4>;
456 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
457 clock-output-names = "ts";
460 ss_clk: clk@01c2009c {
462 - compatible = "allwinner,sun4i-mod0-clk";
463 + compatible = "allwinner,sun4i-a10-mod0-clk";
464 reg = <0x01c2009c 0x4>;
465 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
466 clock-output-names = "ss";
469 spi0_clk: clk@01c200a0 {
471 - compatible = "allwinner,sun4i-mod0-clk";
472 + compatible = "allwinner,sun4i-a10-mod0-clk";
473 reg = <0x01c200a0 0x4>;
474 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
475 clock-output-names = "spi0";
478 spi1_clk: clk@01c200a4 {
480 - compatible = "allwinner,sun4i-mod0-clk";
481 + compatible = "allwinner,sun4i-a10-mod0-clk";
482 reg = <0x01c200a4 0x4>;
483 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
484 clock-output-names = "spi1";
487 spi2_clk: clk@01c200a8 {
489 - compatible = "allwinner,sun4i-mod0-clk";
490 + compatible = "allwinner,sun4i-a10-mod0-clk";
491 reg = <0x01c200a8 0x4>;
492 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
493 clock-output-names = "spi2";
496 ir0_clk: clk@01c200b0 {
498 - compatible = "allwinner,sun4i-mod0-clk";
499 + compatible = "allwinner,sun4i-a10-mod0-clk";
500 reg = <0x01c200b0 0x4>;
501 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
502 clock-output-names = "ir0";
505 mbus_clk: clk@01c2015c {
507 - compatible = "allwinner,sun4i-mod0-clk";
508 + compatible = "allwinner,sun4i-a10-mod0-clk";
509 reg = <0x01c2015c 0x4>;
510 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
511 clock-output-names = "mbus";
512 diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
513 index d196ebc6..24cd86cb 100644
514 --- a/arch/arm/boot/dts/sun5i-a13.dtsi
515 +++ b/arch/arm/boot/dts/sun5i-a13.dtsi
518 osc24M: clk@01c20050 {
520 - compatible = "allwinner,sun4i-osc-clk";
521 + compatible = "allwinner,sun4i-a10-osc-clk";
522 reg = <0x01c20050 0x4>;
523 clock-frequency = <24000000>;
524 clock-output-names = "osc24M";
529 - compatible = "allwinner,sun4i-pll1-clk";
530 + compatible = "allwinner,sun4i-a10-pll1-clk";
531 reg = <0x01c20000 0x4>;
533 clock-output-names = "pll1";
538 - compatible = "allwinner,sun4i-pll1-clk";
539 + compatible = "allwinner,sun4i-a10-pll1-clk";
540 reg = <0x01c20018 0x4>;
542 clock-output-names = "pll4";
547 - compatible = "allwinner,sun4i-pll5-clk";
548 + compatible = "allwinner,sun4i-a10-pll5-clk";
549 reg = <0x01c20020 0x4>;
551 clock-output-names = "pll5_ddr", "pll5_other";
556 - compatible = "allwinner,sun4i-pll6-clk";
557 + compatible = "allwinner,sun4i-a10-pll6-clk";
558 reg = <0x01c20028 0x4>;
560 clock-output-names = "pll6_sata", "pll6_other", "pll6";
565 - compatible = "allwinner,sun4i-cpu-clk";
566 + compatible = "allwinner,sun4i-a10-cpu-clk";
567 reg = <0x01c20054 0x4>;
568 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
569 clock-output-names = "cpu";
574 - compatible = "allwinner,sun4i-axi-clk";
575 + compatible = "allwinner,sun4i-a10-axi-clk";
576 reg = <0x01c20054 0x4>;
578 clock-output-names = "axi";
581 axi_gates: clk@01c2005c {
583 - compatible = "allwinner,sun4i-axi-gates-clk";
584 + compatible = "allwinner,sun4i-a10-axi-gates-clk";
585 reg = <0x01c2005c 0x4>;
587 clock-output-names = "axi_dram";
592 - compatible = "allwinner,sun4i-ahb-clk";
593 + compatible = "allwinner,sun4i-a10-ahb-clk";
594 reg = <0x01c20054 0x4>;
596 clock-output-names = "ahb";
599 apb0: apb0@01c20054 {
601 - compatible = "allwinner,sun4i-apb0-clk";
602 + compatible = "allwinner,sun4i-a10-apb0-clk";
603 reg = <0x01c20054 0x4>;
605 clock-output-names = "apb0";
608 apb1_mux: apb1_mux@01c20058 {
610 - compatible = "allwinner,sun4i-apb1-mux-clk";
611 + compatible = "allwinner,sun4i-a10-apb1-mux-clk";
612 reg = <0x01c20058 0x4>;
613 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
614 clock-output-names = "apb1_mux";
617 apb1: apb1@01c20058 {
619 - compatible = "allwinner,sun4i-apb1-clk";
620 + compatible = "allwinner,sun4i-a10-apb1-clk";
621 reg = <0x01c20058 0x4>;
622 clocks = <&apb1_mux>;
623 clock-output-names = "apb1";
626 nand_clk: clk@01c20080 {
628 - compatible = "allwinner,sun4i-mod0-clk";
629 + compatible = "allwinner,sun4i-a10-mod0-clk";
630 reg = <0x01c20080 0x4>;
631 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
632 clock-output-names = "nand";
635 ms_clk: clk@01c20084 {
637 - compatible = "allwinner,sun4i-mod0-clk";
638 + compatible = "allwinner,sun4i-a10-mod0-clk";
639 reg = <0x01c20084 0x4>;
640 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
641 clock-output-names = "ms";
644 mmc0_clk: clk@01c20088 {
646 - compatible = "allwinner,sun4i-mod0-clk";
647 + compatible = "allwinner,sun4i-a10-mod0-clk";
648 reg = <0x01c20088 0x4>;
649 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
650 clock-output-names = "mmc0";
653 mmc1_clk: clk@01c2008c {
655 - compatible = "allwinner,sun4i-mod0-clk";
656 + compatible = "allwinner,sun4i-a10-mod0-clk";
657 reg = <0x01c2008c 0x4>;
658 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
659 clock-output-names = "mmc1";
662 mmc2_clk: clk@01c20090 {
664 - compatible = "allwinner,sun4i-mod0-clk";
665 + compatible = "allwinner,sun4i-a10-mod0-clk";
666 reg = <0x01c20090 0x4>;
667 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
668 clock-output-names = "mmc2";
671 ts_clk: clk@01c20098 {
673 - compatible = "allwinner,sun4i-mod0-clk";
674 + compatible = "allwinner,sun4i-a10-mod0-clk";
675 reg = <0x01c20098 0x4>;
676 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
677 clock-output-names = "ts";
680 ss_clk: clk@01c2009c {
682 - compatible = "allwinner,sun4i-mod0-clk";
683 + compatible = "allwinner,sun4i-a10-mod0-clk";
684 reg = <0x01c2009c 0x4>;
685 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
686 clock-output-names = "ss";
689 spi0_clk: clk@01c200a0 {
691 - compatible = "allwinner,sun4i-mod0-clk";
692 + compatible = "allwinner,sun4i-a10-mod0-clk";
693 reg = <0x01c200a0 0x4>;
694 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
695 clock-output-names = "spi0";
698 spi1_clk: clk@01c200a4 {
700 - compatible = "allwinner,sun4i-mod0-clk";
701 + compatible = "allwinner,sun4i-a10-mod0-clk";
702 reg = <0x01c200a4 0x4>;
703 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
704 clock-output-names = "spi1";
707 spi2_clk: clk@01c200a8 {
709 - compatible = "allwinner,sun4i-mod0-clk";
710 + compatible = "allwinner,sun4i-a10-mod0-clk";
711 reg = <0x01c200a8 0x4>;
712 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
713 clock-output-names = "spi2";
716 ir0_clk: clk@01c200b0 {
718 - compatible = "allwinner,sun4i-mod0-clk";
719 + compatible = "allwinner,sun4i-a10-mod0-clk";
720 reg = <0x01c200b0 0x4>;
721 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
722 clock-output-names = "ir0";
725 mbus_clk: clk@01c2015c {
727 - compatible = "allwinner,sun4i-mod0-clk";
728 + compatible = "allwinner,sun4i-a10-mod0-clk";
729 reg = <0x01c2015c 0x4>;
730 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
731 clock-output-names = "mbus";
732 diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
733 index d3f1995..af6f87c 100644
734 --- a/arch/arm/boot/dts/sun6i-a31.dtsi
735 +++ b/arch/arm/boot/dts/sun6i-a31.dtsi
740 - compatible = "allwinner,sun4i-cpu-clk";
741 + compatible = "allwinner,sun4i-a10-cpu-clk";
742 reg = <0x01c20050 0x4>;
749 - compatible = "allwinner,sun4i-axi-clk";
750 + compatible = "allwinner,sun4i-a10-axi-clk";
751 reg = <0x01c20050 0x4>;
753 clock-output-names = "axi";
756 ahb1: ahb1@01c20054 {
758 - compatible = "allwinner,sun4i-ahb-clk";
759 + compatible = "allwinner,sun4i-a10-ahb-clk";
760 reg = <0x01c20054 0x4>;
761 clocks = <&ahb1_mux>;
762 clock-output-names = "ahb1";
765 apb1: apb1@01c20054 {
767 - compatible = "allwinner,sun4i-apb0-clk";
768 + compatible = "allwinner,sun4i-a10-apb0-clk";
769 reg = <0x01c20054 0x4>;
771 clock-output-names = "apb1";
774 apb2_mux: apb2_mux@01c20058 {
776 - compatible = "allwinner,sun4i-apb1-mux-clk";
777 + compatible = "allwinner,sun4i-a10-apb1-mux-clk";
778 reg = <0x01c20058 0x4>;
779 clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
780 clock-output-names = "apb2_mux";
781 diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
782 index 911d4e4..d00fbf8 100644
783 --- a/arch/arm/boot/dts/sun7i-a20.dtsi
784 +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
787 osc24M: clk@01c20050 {
789 - compatible = "allwinner,sun4i-osc-clk";
790 + compatible = "allwinner,sun4i-a10-osc-clk";
791 reg = <0x01c20050 0x4>;
792 clock-frequency = <24000000>;
793 clock-output-names = "osc24M";
798 - compatible = "allwinner,sun4i-pll1-clk";
799 + compatible = "allwinner,sun4i-a10-pll1-clk";
800 reg = <0x01c20000 0x4>;
802 clock-output-names = "pll1";
807 - compatible = "allwinner,sun4i-pll1-clk";
808 + compatible = "allwinner,sun4i-a10-pll1-clk";
809 reg = <0x01c20018 0x4>;
811 clock-output-names = "pll4";
816 - compatible = "allwinner,sun4i-pll5-clk";
817 + compatible = "allwinner,sun4i-a10-pll5-clk";
818 reg = <0x01c20020 0x4>;
820 clock-output-names = "pll5_ddr", "pll5_other";
825 - compatible = "allwinner,sun4i-pll6-clk";
826 + compatible = "allwinner,sun4i-a10-pll6-clk";
827 reg = <0x01c20028 0x4>;
829 clock-output-names = "pll6_sata", "pll6_other", "pll6";
834 - compatible = "allwinner,sun4i-cpu-clk";
835 + compatible = "allwinner,sun4i-a10-cpu-clk";
836 reg = <0x01c20054 0x4>;
837 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
838 clock-output-names = "cpu";
843 - compatible = "allwinner,sun4i-axi-clk";
844 + compatible = "allwinner,sun4i-a10-axi-clk";
845 reg = <0x01c20054 0x4>;
847 clock-output-names = "axi";
852 - compatible = "allwinner,sun4i-ahb-clk";
853 + compatible = "allwinner,sun4i-a10-ahb-clk";
854 reg = <0x01c20054 0x4>;
856 clock-output-names = "ahb";
859 apb0: apb0@01c20054 {
861 - compatible = "allwinner,sun4i-apb0-clk";
862 + compatible = "allwinner,sun4i-a10-apb0-clk";
863 reg = <0x01c20054 0x4>;
865 clock-output-names = "apb0";
868 apb1_mux: apb1_mux@01c20058 {
870 - compatible = "allwinner,sun4i-apb1-mux-clk";
871 + compatible = "allwinner,sun4i-a10-apb1-mux-clk";
872 reg = <0x01c20058 0x4>;
873 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
874 clock-output-names = "apb1_mux";
877 apb1: apb1@01c20058 {
879 - compatible = "allwinner,sun4i-apb1-clk";
880 + compatible = "allwinner,sun4i-a10-apb1-clk";
881 reg = <0x01c20058 0x4>;
882 clocks = <&apb1_mux>;
883 clock-output-names = "apb1";
886 nand_clk: clk@01c20080 {
888 - compatible = "allwinner,sun4i-mod0-clk";
889 + compatible = "allwinner,sun4i-a10-mod0-clk";
890 reg = <0x01c20080 0x4>;
891 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
892 clock-output-names = "nand";
895 ms_clk: clk@01c20084 {
897 - compatible = "allwinner,sun4i-mod0-clk";
898 + compatible = "allwinner,sun4i-a10-mod0-clk";
899 reg = <0x01c20084 0x4>;
900 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
901 clock-output-names = "ms";
904 mmc0_clk: clk@01c20088 {
906 - compatible = "allwinner,sun4i-mod0-clk";
907 + compatible = "allwinner,sun4i-a10-mod0-clk";
908 reg = <0x01c20088 0x4>;
909 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
910 clock-output-names = "mmc0";
913 mmc1_clk: clk@01c2008c {
915 - compatible = "allwinner,sun4i-mod0-clk";
916 + compatible = "allwinner,sun4i-a10-mod0-clk";
917 reg = <0x01c2008c 0x4>;
918 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
919 clock-output-names = "mmc1";
922 mmc2_clk: clk@01c20090 {
924 - compatible = "allwinner,sun4i-mod0-clk";
925 + compatible = "allwinner,sun4i-a10-mod0-clk";
926 reg = <0x01c20090 0x4>;
927 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
928 clock-output-names = "mmc2";
931 mmc3_clk: clk@01c20094 {
933 - compatible = "allwinner,sun4i-mod0-clk";
934 + compatible = "allwinner,sun4i-a10-mod0-clk";
935 reg = <0x01c20094 0x4>;
936 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
937 clock-output-names = "mmc3";
940 ts_clk: clk@01c20098 {
942 - compatible = "allwinner,sun4i-mod0-clk";
943 + compatible = "allwinner,sun4i-a10-mod0-clk";
944 reg = <0x01c20098 0x4>;
945 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
946 clock-output-names = "ts";
949 ss_clk: clk@01c2009c {
951 - compatible = "allwinner,sun4i-mod0-clk";
952 + compatible = "allwinner,sun4i-a10-mod0-clk";
953 reg = <0x01c2009c 0x4>;
954 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
955 clock-output-names = "ss";
958 spi0_clk: clk@01c200a0 {
960 - compatible = "allwinner,sun4i-mod0-clk";
961 + compatible = "allwinner,sun4i-a10-mod0-clk";
962 reg = <0x01c200a0 0x4>;
963 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
964 clock-output-names = "spi0";
967 spi1_clk: clk@01c200a4 {
969 - compatible = "allwinner,sun4i-mod0-clk";
970 + compatible = "allwinner,sun4i-a10-mod0-clk";
971 reg = <0x01c200a4 0x4>;
972 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
973 clock-output-names = "spi1";
976 spi2_clk: clk@01c200a8 {
978 - compatible = "allwinner,sun4i-mod0-clk";
979 + compatible = "allwinner,sun4i-a10-mod0-clk";
980 reg = <0x01c200a8 0x4>;
981 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
982 clock-output-names = "spi2";
985 pata_clk: clk@01c200ac {
987 - compatible = "allwinner,sun4i-mod0-clk";
988 + compatible = "allwinner,sun4i-a10-mod0-clk";
989 reg = <0x01c200ac 0x4>;
990 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
991 clock-output-names = "pata";
994 ir0_clk: clk@01c200b0 {
996 - compatible = "allwinner,sun4i-mod0-clk";
997 + compatible = "allwinner,sun4i-a10-mod0-clk";
998 reg = <0x01c200b0 0x4>;
999 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
1000 clock-output-names = "ir0";
1003 ir1_clk: clk@01c200b4 {
1005 - compatible = "allwinner,sun4i-mod0-clk";
1006 + compatible = "allwinner,sun4i-a10-mod0-clk";
1007 reg = <0x01c200b4 0x4>;
1008 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
1009 clock-output-names = "ir1";
1012 spi3_clk: clk@01c200d4 {
1014 - compatible = "allwinner,sun4i-mod0-clk";
1015 + compatible = "allwinner,sun4i-a10-mod0-clk";
1016 reg = <0x01c200d4 0x4>;
1017 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
1018 clock-output-names = "spi3";
1021 mbus_clk: clk@01c2015c {
1023 - compatible = "allwinner,sun4i-mod0-clk";
1024 + compatible = "allwinner,sun4i-a10-mod0-clk";
1025 reg = <0x01c2015c 0x4>;
1026 clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
1027 clock-output-names = "mbus";