1 From aeb3b73fc416e14afd25f25e69f8713488edcc1b Mon Sep 17 00:00:00 2001
2 From: Maxime Ripard <maxime.ripard@free-electrons.com>
3 Date: Sat, 22 Feb 2014 22:35:57 +0100
4 Subject: [PATCH] ARM: dt: sun5i: Add A13 SPI controller nodes
6 The A13 has 3 SPI controllers compatible with the one found in the A10. Add
9 Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
11 arch/arm/boot/dts/sun5i-a13.dtsi | 33 +++++++++++++++++++++++++++++++++
12 1 file changed, 33 insertions(+)
14 --- a/arch/arm/boot/dts/sun5i-a13.dtsi
15 +++ b/arch/arm/boot/dts/sun5i-a13.dtsi
20 + spi0: spi@01c05000 {
21 + compatible = "allwinner,sun4i-a10-spi";
22 + reg = <0x01c05000 0x1000>;
24 + clocks = <&ahb_gates 20>, <&spi0_clk>;
25 + clock-names = "ahb", "mod";
26 + status = "disabled";
27 + #address-cells = <1>;
31 + spi1: spi@01c06000 {
32 + compatible = "allwinner,sun4i-a10-spi";
33 + reg = <0x01c06000 0x1000>;
35 + clocks = <&ahb_gates 21>, <&spi1_clk>;
36 + clock-names = "ahb", "mod";
37 + status = "disabled";
38 + #address-cells = <1>;
42 + spi2: spi@01c17000 {
43 + compatible = "allwinner,sun4i-a10-spi";
44 + reg = <0x01c17000 0x1000>;
46 + clocks = <&ahb_gates 22>, <&spi2_clk>;
47 + clock-names = "ahb", "mod";
48 + status = "disabled";
49 + #address-cells = <1>;
53 intc: interrupt-controller@01c20400 {
54 compatible = "allwinner,sun4i-ic";
55 reg = <0x01c20400 0x400>;