1 From eebb592523672ee7288b9327bd222165db638d1a Mon Sep 17 00:00:00 2001
2 From: Carlo Caione <carlo@caione.org>
3 Date: Thu, 27 Feb 2014 20:34:21 +0100
4 Subject: [PATCH] ARM: sun7i/sun6i: dts: Add NMI irqchip support
6 This patch adds DTS entries for NMI controller as child of GIC.
8 Signed-off-by: Carlo Caione <carlo@caione.org>
10 arch/arm/boot/dts/sun6i-a31.dtsi | 8 ++++++++
11 arch/arm/boot/dts/sun7i-a20.dtsi | 8 ++++++++
12 2 files changed, 16 insertions(+)
14 --- a/arch/arm/boot/dts/sun6i-a31.dtsi
15 +++ b/arch/arm/boot/dts/sun6i-a31.dtsi
17 interrupts = <1 9 0xf04>;
20 + nmi_intc: interrupt-controller@01f00c0c {
21 + compatible = "allwinner,sun6i-a31-sc-nmi";
22 + interrupt-controller;
23 + #interrupt-cells = <2>;
24 + reg = <0x01f00c0c 0x38>;
25 + interrupts = <0 32 4>;
29 compatible = "allwinner,sun6i-a31-cpuconfig";
30 reg = <0x01f01c00 0x300>;
31 --- a/arch/arm/boot/dts/sun7i-a20.dtsi
32 +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
37 + nmi_intc: interrupt-controller@01c00030 {
38 + compatible = "allwinner,sun7i-a20-sc-nmi";
39 + interrupt-controller;
40 + #interrupt-cells = <2>;
41 + reg = <0x01c00030 0x0c>;
42 + interrupts = <0 0 4>;
46 compatible = "allwinner,sun4i-a10-spi";
47 reg = <0x01c05000 0x1000>;