1 From 4904337fe34fa7fc529d6f4d9ee8b96fe7db310a Mon Sep 17 00:00:00 2001
2 From: Corentin Labbe <clabbe.montjoie@gmail.com>
3 Date: Tue, 31 Oct 2017 09:19:12 +0100
4 Subject: [PATCH] ARM: dts: sunxi: Restore EMAC changes (boards)
6 The original dwmac-sun8i DT bindings have some issue on how to handle
7 integrated PHY and was reverted in last RC of 4.13.
8 But now we have a solution so we need to get back that was reverted.
10 This patch restore all boards DT about dwmac-sun8i
11 This reverts partially commit fe45174b72ae ("arm: dts: sunxi: Revert EMAC changes")
13 Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
14 Acked-by: Florian Fainelli <f.fainelli@gmail.com>
15 Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
17 arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts | 9 +++++++
18 arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts | 19 +++++++++++++++
19 arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts | 29 +++++++++++++++++++++++
20 arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts | 7 ++++++
21 arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 8 +++++++
22 arch/arm/boot/dts/sun8i-h3-orangepi-one.dts | 8 +++++++
23 arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts | 5 ++++
24 arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 8 +++++++
25 arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 22 +++++++++++++++++
26 arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts | 16 +++++++++++++
27 10 files changed, 131 insertions(+)
29 --- a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
30 +++ b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
35 + /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
45 + phy-handle = <&int_mii_phy>;
47 + allwinner,leds-active-low;
52 pinctrl-names = "default";
53 pinctrl-0 = <&mmc0_pins_a>;
54 --- a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
55 +++ b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts
57 compatible = "sinovoip,bpi-m2-plus", "allwinner,sun8i-h3";
69 + pinctrl-names = "default";
70 + pinctrl-0 = <&emac_rgmii_pins>;
71 + phy-supply = <®_gmac_3v3>;
72 + phy-handle = <&ext_rgmii_phy>;
75 + allwinner,leds-active-low;
80 + ext_rgmii_phy: ethernet-phy@1 {
81 + compatible = "ethernet-phy-ieee802.3-c22";
87 pinctrl-names = "default";
88 pinctrl-0 = <&ir_pins_a>;
89 --- a/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
90 +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-m1-plus.dts
93 model = "FriendlyArm NanoPi M1 Plus";
94 compatible = "friendlyarm,nanopi-m1-plus", "allwinner,sun8i-h3";
96 + reg_gmac_3v3: gmac-3v3 {
97 + compatible = "regulator-fixed";
98 + regulator-name = "gmac-3v3";
99 + regulator-min-microvolt = <3300000>;
100 + regulator-max-microvolt = <3300000>;
101 + startup-delay-us = <100000>;
102 + enable-active-high;
103 + gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
113 + pinctrl-names = "default";
114 + pinctrl-0 = <&emac_rgmii_pins>;
115 + phy-supply = <®_gmac_3v3>;
116 + phy-handle = <&ext_rgmii_phy>;
117 + phy-mode = "rgmii";
119 + allwinner,leds-active-low;
125 + ext_rgmii_phy: ethernet-phy@1 {
126 + compatible = "ethernet-phy-ieee802.3-c22";
134 --- a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
135 +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
137 model = "FriendlyARM NanoPi NEO";
138 compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3";
142 + phy-handle = <&int_mii_phy>;
144 + allwinner,leds-active-low;
147 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
148 +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts
152 /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
154 ethernet1 = &rtl8189;
162 + phy-handle = <&int_mii_phy>;
164 + allwinner,leds-active-low;
169 pinctrl-names = "default";
170 pinctrl-0 = <&ir_pins_a>;
171 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
172 +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts
174 compatible = "xunlong,orangepi-one", "allwinner,sun8i-h3";
186 + phy-handle = <&int_mii_phy>;
188 + allwinner,leds-active-low;
193 pinctrl-names = "default";
194 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
195 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts
196 +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc-plus.dts
202 + /* LEDs changed to active high on the plus */
203 + /delete-property/ allwinner,leds-active-low;
207 pinctrl-names = "default";
208 pinctrl-0 = <&mmc1_pins_a>;
209 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
210 +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
212 compatible = "xunlong,orangepi-pc", "allwinner,sun8i-h3";
224 + phy-handle = <&int_mii_phy>;
226 + allwinner,leds-active-low;
231 pinctrl-names = "default";
232 pinctrl-0 = <&ir_pins_a>;
233 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
234 +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts
236 model = "Xunlong Orange Pi Plus / Plus 2";
237 compatible = "xunlong,orangepi-plus", "allwinner,sun8i-h3";
243 reg_gmac_3v3: gmac-3v3 {
244 compatible = "regulator-fixed";
245 regulator-name = "gmac-3v3";
251 + pinctrl-names = "default";
252 + pinctrl-0 = <&emac_rgmii_pins>;
253 + phy-supply = <®_gmac_3v3>;
254 + phy-handle = <&ext_rgmii_phy>;
255 + phy-mode = "rgmii";
257 + allwinner,leds-active-low;
262 + ext_rgmii_phy: ethernet-phy@1 {
263 + compatible = "ethernet-phy-ieee802.3-c22";
269 pinctrl-names = "default";
270 pinctrl-0 = <&mmc2_8bit_pins>;
271 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts
272 +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus2e.dts
274 gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */
279 + pinctrl-names = "default";
280 + pinctrl-0 = <&emac_rgmii_pins>;
281 + phy-supply = <®_gmac_3v3>;
282 + phy-handle = <&ext_rgmii_phy>;
283 + phy-mode = "rgmii";
288 + ext_rgmii_phy: ethernet-phy@1 {
289 + compatible = "ethernet-phy-ieee802.3-c22";