target/linux/sunxi/patches-4.4/102-dt-sun7i-add-dram-gates.patch

   1 From 0b4bf5a5200b9ac5ddf545665f171feb5594677d Mon Sep 17 00:00:00 2001
   2 From: Chen-Yu Tsai <wens@csie.org>
   3 Date: Sat, 5 Dec 2015 21:16:46 +0800
   4 Subject: [PATCH] ARM: dts: sun7i: Add DRAM gates
   5
   6 The DRAM gates controls direct memory access for some peripherals.
   7 These peripherals include the display pipeline, so add the required
   8 gates to the simplefb nodes as well.
   9
  10 Signed-off-by: Chen-Yu Tsai <wens@csie.org>
  11 Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
  12 ---
  13  arch/arm/boot/dts/sun7i-a20.dtsi | 32 +++++++++++++++++++++++++++++---
  14  1 file changed, 29 insertions(+), 3 deletions(-)
  15
  16 diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
  17 index e02eb72..21169c0 100644
  18 --- a/arch/arm/boot/dts/sun7i-a20.dtsi
  19 +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
  20 @@ -68,7 +68,7 @@
  21                                      "simple-framebuffer";
  22                         allwinner,pipeline = "de_be0-lcd0-hdmi";
  23                         clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
  24 -                                <&ahb_gates 44>;
  25 +                                <&ahb_gates 44>, <&dram_gates 26>;
  26                         status = "disabled";
  27                 };
  28
  29 @@ -76,7 +76,8 @@
  30                         compatible = "allwinner,simple-framebuffer",
  31                                      "simple-framebuffer";
  32                         allwinner,pipeline = "de_be0-lcd0";
  33 -                       clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>;
  34 +                       clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>,
  35 +                                <&dram_gates 26>;
  36                         status = "disabled";
  37                 };
  38
  39 @@ -85,7 +86,7 @@
  40                                      "simple-framebuffer";
  41                         allwinner,pipeline = "de_be0-lcd0-tve0";
  42                         clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>,
  43 -                                <&ahb_gates 44>;
  44 +                                <&ahb_gates 44>, <&dram_gates 26>;
  45                         status = "disabled";
  46                 };
  47         };
  48 @@ -501,6 +502,31 @@
  49                         clock-output-names = "spi3";
  50                 };
  51
  52 +               dram_gates: clk@01c20100 {
  53 +                       #clock-cells = <1>;
  54 +                       compatible = "allwinner,sun4i-a10-dram-gates-clk";
  55 +                       reg = <0x01c20100 0x4>;
  56 +                       clocks = <&pll5 0>;
  57 +                       clock-indices = <0>,
  58 +                                       <1>, <2>,
  59 +                                       <3>,
  60 +                                       <4>,
  61 +                                       <5>, <6>,
  62 +                                       <15>,
  63 +                                       <24>, <25>,
  64 +                                       <26>, <27>,
  65 +                                       <28>, <29>;
  66 +                       clock-output-names = "dram_ve",
  67 +                                            "dram_csi0", "dram_csi1",
  68 +                                            "dram_ts",
  69 +                                            "dram_tvd",
  70 +                                            "dram_tve0", "dram_tve1",
  71 +                                            "dram_output",
  72 +                                            "dram_de_fe1", "dram_de_fe0",
  73 +                                            "dram_de_be0", "dram_de_be1",
  74 +                                            "dram_de_mp", "dram_ace";
  75 +               };
  76 +
  77                 codec_clk: clk@01c20140 {
  78                         #clock-cells = <0>;
  79                         compatible = "allwinner,sun4i-a10-codec-clk";