1 From 318d93bc41823e86967c8251eef0444a72e4d687 Mon Sep 17 00:00:00 2001
2 From: Jens Kuske <jenskuske@gmail.com>
3 Date: Fri, 4 Dec 2015 22:24:42 +0100
4 Subject: [PATCH] ARM: dts: sunxi: Add Allwinner H3 DTSI
6 The Allwinner H3 is a home entertainment system oriented SoC with
7 four Cortex-A7 cores and a Mali-400MP2 GPU.
9 Signed-off-by: Jens Kuske <jenskuske@gmail.com>
10 Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
12 arch/arm/boot/dts/sun8i-h3.dtsi | 497 ++++++++++++++++++++++++++++++++++++++++
13 1 file changed, 497 insertions(+)
14 create mode 100644 arch/arm/boot/dts/sun8i-h3.dtsi
17 +++ b/arch/arm/boot/dts/sun8i-h3.dtsi
20 + * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
22 + * This file is dual-licensed: you can use it either under the terms
23 + * of the GPL or the X11 license, at your option. Note that this dual
24 + * licensing only applies to this file, and not this project as a
27 + * a) This file is free software; you can redistribute it and/or
28 + * modify it under the terms of the GNU General Public License as
29 + * published by the Free Software Foundation; either version 2 of the
30 + * License, or (at your option) any later version.
32 + * This file is distributed in the hope that it will be useful,
33 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
34 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
35 + * GNU General Public License for more details.
37 + * Or, alternatively,
39 + * b) Permission is hereby granted, free of charge, to any person
40 + * obtaining a copy of this software and associated documentation
41 + * files (the "Software"), to deal in the Software without
42 + * restriction, including without limitation the rights to use,
43 + * copy, modify, merge, publish, distribute, sublicense, and/or
44 + * sell copies of the Software, and to permit persons to whom the
45 + * Software is furnished to do so, subject to the following
48 + * The above copyright notice and this permission notice shall be
49 + * included in all copies or substantial portions of the Software.
51 + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
52 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
53 + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
54 + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
55 + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
56 + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
57 + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
58 + * OTHER DEALINGS IN THE SOFTWARE.
61 +#include "skeleton.dtsi"
63 +#include <dt-bindings/interrupt-controller/arm-gic.h>
64 +#include <dt-bindings/pinctrl/sun4i-a10.h>
67 + interrupt-parent = <&gic>;
70 + #address-cells = <1>;
74 + compatible = "arm,cortex-a7";
75 + device_type = "cpu";
80 + compatible = "arm,cortex-a7";
81 + device_type = "cpu";
86 + compatible = "arm,cortex-a7";
87 + device_type = "cpu";
92 + compatible = "arm,cortex-a7";
93 + device_type = "cpu";
99 + compatible = "arm,armv7-timer";
100 + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
101 + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
102 + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
103 + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
107 + #address-cells = <1>;
111 + osc24M: osc24M_clk {
112 + #clock-cells = <0>;
113 + compatible = "fixed-clock";
114 + clock-frequency = <24000000>;
115 + clock-output-names = "osc24M";
118 + osc32k: osc32k_clk {
119 + #clock-cells = <0>;
120 + compatible = "fixed-clock";
121 + clock-frequency = <32768>;
122 + clock-output-names = "osc32k";
125 + pll1: clk@01c20000 {
126 + #clock-cells = <0>;
127 + compatible = "allwinner,sun8i-a23-pll1-clk";
128 + reg = <0x01c20000 0x4>;
129 + clocks = <&osc24M>;
130 + clock-output-names = "pll1";
133 + /* dummy clock until actually implemented */
135 + #clock-cells = <0>;
136 + compatible = "fixed-clock";
137 + clock-frequency = <0>;
138 + clock-output-names = "pll5";
141 + pll6: clk@01c20028 {
142 + #clock-cells = <1>;
143 + compatible = "allwinner,sun6i-a31-pll6-clk";
144 + reg = <0x01c20028 0x4>;
145 + clocks = <&osc24M>;
146 + clock-output-names = "pll6", "pll6x2";
149 + pll6d2: pll6d2_clk {
150 + #clock-cells = <0>;
151 + compatible = "fixed-factor-clock";
154 + clocks = <&pll6 0>;
155 + clock-output-names = "pll6d2";
158 + /* dummy clock until pll6 can be reused */
160 + #clock-cells = <0>;
161 + compatible = "fixed-clock";
162 + clock-frequency = <1>;
163 + clock-output-names = "pll8";
166 + cpu: cpu_clk@01c20050 {
167 + #clock-cells = <0>;
168 + compatible = "allwinner,sun4i-a10-cpu-clk";
169 + reg = <0x01c20050 0x4>;
170 + clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
171 + clock-output-names = "cpu";
174 + axi: axi_clk@01c20050 {
175 + #clock-cells = <0>;
176 + compatible = "allwinner,sun4i-a10-axi-clk";
177 + reg = <0x01c20050 0x4>;
179 + clock-output-names = "axi";
182 + ahb1: ahb1_clk@01c20054 {
183 + #clock-cells = <0>;
184 + compatible = "allwinner,sun6i-a31-ahb1-clk";
185 + reg = <0x01c20054 0x4>;
186 + clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
187 + clock-output-names = "ahb1";
190 + ahb2: ahb2_clk@01c2005c {
191 + #clock-cells = <0>;
192 + compatible = "allwinner,sun8i-h3-ahb2-clk";
193 + reg = <0x01c2005c 0x4>;
194 + clocks = <&ahb1>, <&pll6d2>;
195 + clock-output-names = "ahb2";
198 + apb1: apb1_clk@01c20054 {
199 + #clock-cells = <0>;
200 + compatible = "allwinner,sun4i-a10-apb0-clk";
201 + reg = <0x01c20054 0x4>;
203 + clock-output-names = "apb1";
206 + apb2: apb2_clk@01c20058 {
207 + #clock-cells = <0>;
208 + compatible = "allwinner,sun4i-a10-apb1-clk";
209 + reg = <0x01c20058 0x4>;
210 + clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
211 + clock-output-names = "apb2";
214 + bus_gates: clk@01c20060 {
215 + #clock-cells = <1>;
216 + compatible = "allwinner,sun8i-h3-bus-gates-clk";
217 + reg = <0x01c20060 0x14>;
218 + clocks = <&ahb1>, <&ahb2>, <&apb1>, <&apb2>;
219 + clock-names = "ahb1", "ahb2", "apb1", "apb2";
220 + clock-indices = <5>, <6>, <8>,
238 + <116>, <128>, <135>;
239 + clock-output-names = "bus_ce", "bus_dma", "bus_mmc0",
240 + "bus_mmc1", "bus_mmc2", "bus_nand",
241 + "bus_sdram", "bus_gmac", "bus_ts",
242 + "bus_hstimer", "bus_spi0",
243 + "bus_spi1", "bus_otg",
244 + "bus_otg_ehci0", "bus_ehci1",
245 + "bus_ehci2", "bus_ehci3",
246 + "bus_otg_ohci0", "bus_ohci1",
247 + "bus_ohci2", "bus_ohci3", "bus_ve",
248 + "bus_lcd0", "bus_lcd1", "bus_deint",
249 + "bus_csi", "bus_tve", "bus_hdmi",
250 + "bus_de", "bus_gpu", "bus_msgbox",
251 + "bus_spinlock", "bus_codec",
252 + "bus_spdif", "bus_pio", "bus_ths",
253 + "bus_i2s0", "bus_i2s1", "bus_i2s2",
254 + "bus_i2c0", "bus_i2c1", "bus_i2c2",
255 + "bus_uart0", "bus_uart1",
256 + "bus_uart2", "bus_uart3",
257 + "bus_scr", "bus_ephy", "bus_dbg";
260 + mmc0_clk: clk@01c20088 {
261 + #clock-cells = <1>;
262 + compatible = "allwinner,sun4i-a10-mmc-clk";
263 + reg = <0x01c20088 0x4>;
264 + clocks = <&osc24M>, <&pll6 0>, <&pll8>;
265 + clock-output-names = "mmc0",
270 + mmc1_clk: clk@01c2008c {
271 + #clock-cells = <1>;
272 + compatible = "allwinner,sun4i-a10-mmc-clk";
273 + reg = <0x01c2008c 0x4>;
274 + clocks = <&osc24M>, <&pll6 0>, <&pll8>;
275 + clock-output-names = "mmc1",
280 + mmc2_clk: clk@01c20090 {
281 + #clock-cells = <1>;
282 + compatible = "allwinner,sun4i-a10-mmc-clk";
283 + reg = <0x01c20090 0x4>;
284 + clocks = <&osc24M>, <&pll6 0>, <&pll8>;
285 + clock-output-names = "mmc2",
290 + mbus_clk: clk@01c2015c {
291 + #clock-cells = <0>;
292 + compatible = "allwinner,sun8i-a23-mbus-clk";
293 + reg = <0x01c2015c 0x4>;
294 + clocks = <&osc24M>, <&pll6 1>, <&pll5>;
295 + clock-output-names = "mbus";
300 + compatible = "simple-bus";
301 + #address-cells = <1>;
305 + dma: dma-controller@01c02000 {
306 + compatible = "allwinner,sun8i-h3-dma";
307 + reg = <0x01c02000 0x1000>;
308 + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
309 + clocks = <&bus_gates 6>;
310 + resets = <&ahb_rst 6>;
314 + mmc0: mmc@01c0f000 {
315 + compatible = "allwinner,sun5i-a13-mmc";
316 + reg = <0x01c0f000 0x1000>;
317 + clocks = <&bus_gates 8>,
321 + clock-names = "ahb",
325 + resets = <&ahb_rst 8>;
326 + reset-names = "ahb";
327 + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
328 + status = "disabled";
329 + #address-cells = <1>;
333 + mmc1: mmc@01c10000 {
334 + compatible = "allwinner,sun5i-a13-mmc";
335 + reg = <0x01c10000 0x1000>;
336 + clocks = <&bus_gates 9>,
340 + clock-names = "ahb",
344 + resets = <&ahb_rst 9>;
345 + reset-names = "ahb";
346 + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
347 + status = "disabled";
348 + #address-cells = <1>;
352 + mmc2: mmc@01c11000 {
353 + compatible = "allwinner,sun5i-a13-mmc";
354 + reg = <0x01c11000 0x1000>;
355 + clocks = <&bus_gates 10>,
359 + clock-names = "ahb",
363 + resets = <&ahb_rst 10>;
364 + reset-names = "ahb";
365 + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
366 + status = "disabled";
367 + #address-cells = <1>;
371 + pio: pinctrl@01c20800 {
372 + compatible = "allwinner,sun8i-h3-pinctrl";
373 + reg = <0x01c20800 0x400>;
374 + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
375 + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
376 + clocks = <&bus_gates 69>;
379 + interrupt-controller;
380 + #interrupt-cells = <2>;
382 + uart0_pins_a: uart0@0 {
383 + allwinner,pins = "PA4", "PA5";
384 + allwinner,function = "uart0";
385 + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
386 + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
389 + mmc0_pins_a: mmc0@0 {
390 + allwinner,pins = "PF0", "PF1", "PF2", "PF3",
392 + allwinner,function = "mmc0";
393 + allwinner,drive = <SUN4I_PINCTRL_30_MA>;
394 + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
397 + mmc0_cd_pin: mmc0_cd_pin@0 {
398 + allwinner,pins = "PF6";
399 + allwinner,function = "gpio_in";
400 + allwinner,drive = <SUN4I_PINCTRL_10_MA>;
401 + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
404 + mmc1_pins_a: mmc1@0 {
405 + allwinner,pins = "PG0", "PG1", "PG2", "PG3",
407 + allwinner,function = "mmc1";
408 + allwinner,drive = <SUN4I_PINCTRL_30_MA>;
409 + allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
413 + ahb_rst: reset@01c202c0 {
414 + #reset-cells = <1>;
415 + compatible = "allwinner,sun6i-a31-ahb1-reset";
416 + reg = <0x01c202c0 0xc>;
419 + apb1_rst: reset@01c202d0 {
420 + #reset-cells = <1>;
421 + compatible = "allwinner,sun6i-a31-clock-reset";
422 + reg = <0x01c202d0 0x4>;
425 + apb2_rst: reset@01c202d8 {
426 + #reset-cells = <1>;
427 + compatible = "allwinner,sun6i-a31-clock-reset";
428 + reg = <0x01c202d8 0x4>;
432 + compatible = "allwinner,sun4i-a10-timer";
433 + reg = <0x01c20c00 0xa0>;
434 + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
435 + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
436 + clocks = <&osc24M>;
439 + wdt0: watchdog@01c20ca0 {
440 + compatible = "allwinner,sun6i-a31-wdt";
441 + reg = <0x01c20ca0 0x20>;
442 + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
445 + uart0: serial@01c28000 {
446 + compatible = "snps,dw-apb-uart";
447 + reg = <0x01c28000 0x400>;
448 + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
450 + reg-io-width = <4>;
451 + clocks = <&bus_gates 112>;
452 + resets = <&apb2_rst 16>;
453 + dmas = <&dma 6>, <&dma 6>;
454 + dma-names = "rx", "tx";
455 + status = "disabled";
458 + uart1: serial@01c28400 {
459 + compatible = "snps,dw-apb-uart";
460 + reg = <0x01c28400 0x400>;
461 + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
463 + reg-io-width = <4>;
464 + clocks = <&bus_gates 113>;
465 + resets = <&apb2_rst 17>;
466 + dmas = <&dma 7>, <&dma 7>;
467 + dma-names = "rx", "tx";
468 + status = "disabled";
471 + uart2: serial@01c28800 {
472 + compatible = "snps,dw-apb-uart";
473 + reg = <0x01c28800 0x400>;
474 + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
476 + reg-io-width = <4>;
477 + clocks = <&bus_gates 114>;
478 + resets = <&apb2_rst 18>;
479 + dmas = <&dma 8>, <&dma 8>;
480 + dma-names = "rx", "tx";
481 + status = "disabled";
484 + uart3: serial@01c28c00 {
485 + compatible = "snps,dw-apb-uart";
486 + reg = <0x01c28c00 0x400>;
487 + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
489 + reg-io-width = <4>;
490 + clocks = <&bus_gates 115>;
491 + resets = <&apb2_rst 19>;
492 + dmas = <&dma 9>, <&dma 9>;
493 + dma-names = "rx", "tx";
494 + status = "disabled";
497 + gic: interrupt-controller@01c81000 {
498 + compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
499 + reg = <0x01c81000 0x1000>,
500 + <0x01c82000 0x1000>,
501 + <0x01c84000 0x2000>,
502 + <0x01c86000 0x2000>;
503 + interrupt-controller;
504 + #interrupt-cells = <3>;
505 + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
508 + rtc: rtc@01f00000 {
509 + compatible = "allwinner,sun6i-a31-rtc";
510 + reg = <0x01f00000 0x54>;
511 + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
512 + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;