1 From 3cdd9f5c4953465abb87ec757159cc0576ae6b0a Mon Sep 17 00:00:00 2001
2 From: Chen-Yu Tsai <wens@csie.org>
3 Date: Sat, 5 Dec 2015 21:16:43 +0800
4 Subject: [PATCH] clk: sunxi: Add VE (Video Engine) module clock driver for
7 The video engine has its own special module clock, consisting of a clock
8 gate, configurable dividers, and a reset control.
10 On later (sun[68]i) families, the reset control is moved out of this
11 piece of hardware and grouped with reset controls of other peripherals.
13 Signed-off-by: Chen-Yu Tsai <wens@csie.org>
14 Tested-by: Jens Kuske <jenskuske@gmail.com>
15 Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
17 Documentation/devicetree/bindings/clock/sunxi.txt | 4 +
18 drivers/clk/sunxi/Makefile | 1 +
19 drivers/clk/sunxi/clk-a10-ve.c | 171 ++++++++++++++++++++++
20 3 files changed, 176 insertions(+)
21 create mode 100644 drivers/clk/sunxi/clk-a10-ve.c
23 --- a/Documentation/devicetree/bindings/clock/sunxi.txt
24 +++ b/Documentation/devicetree/bindings/clock/sunxi.txt
25 @@ -71,6 +71,7 @@ Required properties:
26 "allwinner,sun8i-h3-usb-clk" - for usb gates + resets on H3
27 "allwinner,sun9i-a80-usb-mod-clk" - for usb gates + resets on A80
28 "allwinner,sun9i-a80-usb-phy-clk" - for usb phy gates + resets on A80
29 + "allwinner,sun4i-a10-ve-clk" - for the Video Engine clock
31 Required properties for all clocks:
32 - reg : shall be the control register address for the clock.
33 @@ -90,6 +91,9 @@ Required properties for all clocks:
34 And "allwinner,*-usb-clk" clocks also require:
35 - reset-cells : shall be set to 1
37 +The "allwinner,sun4i-a10-ve-clk" clock also requires:
38 +- reset-cells : shall be set to 0
40 The "allwinner,sun9i-a80-mmc-config-clk" clock also requires:
41 - #reset-cells : shall be set to 1
42 - resets : shall be the reset control phandle for the mmc block.
43 --- a/drivers/clk/sunxi/Makefile
44 +++ b/drivers/clk/sunxi/Makefile
45 @@ -7,6 +7,7 @@ obj-y += clk-a10-codec.o
46 obj-y += clk-a10-hosc.o
47 obj-y += clk-a10-mod1.o
48 obj-y += clk-a10-pll2.o
49 +obj-y += clk-a10-ve.o
50 obj-y += clk-a20-gmac.o
52 obj-y += clk-simple-gates.o
54 +++ b/drivers/clk/sunxi/clk-a10-ve.c
57 + * Copyright 2015 Chen-Yu Tsai
59 + * Chen-Yu Tsai <wens@csie.org>
61 + * This program is free software; you can redistribute it and/or modify
62 + * it under the terms of the GNU General Public License as published by
63 + * the Free Software Foundation; either version 2 of the License, or
64 + * (at your option) any later version.
66 + * This program is distributed in the hope that it will be useful,
67 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
68 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
69 + * GNU General Public License for more details.
72 +#include <linux/clk-provider.h>
73 +#include <linux/of.h>
74 +#include <linux/of_address.h>
75 +#include <linux/reset-controller.h>
76 +#include <linux/slab.h>
77 +#include <linux/spinlock.h>
79 +static DEFINE_SPINLOCK(ve_lock);
81 +#define SUN4I_VE_ENABLE 31
82 +#define SUN4I_VE_DIVIDER_SHIFT 16
83 +#define SUN4I_VE_DIVIDER_WIDTH 3
84 +#define SUN4I_VE_RESET 0
87 + * sunxi_ve_reset... - reset bit in ve clk registers handling
90 +struct ve_reset_data {
93 + struct reset_controller_dev rcdev;
96 +static int sunxi_ve_reset_assert(struct reset_controller_dev *rcdev,
99 + struct ve_reset_data *data = container_of(rcdev,
100 + struct ve_reset_data,
102 + unsigned long flags;
105 + spin_lock_irqsave(data->lock, flags);
107 + reg = readl(data->reg);
108 + writel(reg & ~BIT(SUN4I_VE_RESET), data->reg);
110 + spin_unlock_irqrestore(data->lock, flags);
115 +static int sunxi_ve_reset_deassert(struct reset_controller_dev *rcdev,
118 + struct ve_reset_data *data = container_of(rcdev,
119 + struct ve_reset_data,
121 + unsigned long flags;
124 + spin_lock_irqsave(data->lock, flags);
126 + reg = readl(data->reg);
127 + writel(reg | BIT(SUN4I_VE_RESET), data->reg);
129 + spin_unlock_irqrestore(data->lock, flags);
134 +static int sunxi_ve_of_xlate(struct reset_controller_dev *rcdev,
135 + const struct of_phandle_args *reset_spec)
137 + if (WARN_ON(reset_spec->args_count != 0))
143 +static struct reset_control_ops sunxi_ve_reset_ops = {
144 + .assert = sunxi_ve_reset_assert,
145 + .deassert = sunxi_ve_reset_deassert,
148 +static void __init sun4i_ve_clk_setup(struct device_node *node)
151 + struct clk_divider *div;
152 + struct clk_gate *gate;
153 + struct ve_reset_data *reset_data;
154 + const char *parent;
155 + const char *clk_name = node->name;
159 + reg = of_io_request_and_map(node, 0, of_node_full_name(node));
163 + div = kzalloc(sizeof(*div), GFP_KERNEL);
167 + gate = kzalloc(sizeof(*gate), GFP_KERNEL);
171 + of_property_read_string(node, "clock-output-names", &clk_name);
172 + parent = of_clk_get_parent_name(node, 0);
175 + gate->bit_idx = SUN4I_VE_ENABLE;
176 + gate->lock = &ve_lock;
179 + div->shift = SUN4I_VE_DIVIDER_SHIFT;
180 + div->width = SUN4I_VE_DIVIDER_WIDTH;
181 + div->lock = &ve_lock;
183 + clk = clk_register_composite(NULL, clk_name, &parent, 1,
185 + &div->hw, &clk_divider_ops,
186 + &gate->hw, &clk_gate_ops,
187 + CLK_SET_RATE_PARENT);
189 + goto err_free_gate;
191 + err = of_clk_add_provider(node, of_clk_src_simple_get, clk);
193 + goto err_unregister_clk;
195 + reset_data = kzalloc(sizeof(*reset_data), GFP_KERNEL);
197 + goto err_del_provider;
199 + reset_data->reg = reg;
200 + reset_data->lock = &ve_lock;
201 + reset_data->rcdev.nr_resets = 1;
202 + reset_data->rcdev.ops = &sunxi_ve_reset_ops;
203 + reset_data->rcdev.of_node = node;
204 + reset_data->rcdev.of_xlate = sunxi_ve_of_xlate;
205 + reset_data->rcdev.of_reset_n_cells = 0;
206 + err = reset_controller_register(&reset_data->rcdev);
208 + goto err_free_reset;
215 + of_clk_del_provider(node);
217 + clk_unregister(clk);
225 +CLK_OF_DECLARE(sun4i_ve, "allwinner,sun4i-a10-ve-clk",
226 + sun4i_ve_clk_setup);