target/linux/sunxi/patches-4.4/130-pinctrl-sunxi-add-h3-pio.patch

   1 From 03b83828e452418c18ba506e3e02b5deadbb53fa Mon Sep 17 00:00:00 2001
   2 From: Jens Kuske <jenskuske@gmail.com>
   3 Date: Tue, 27 Oct 2015 17:50:23 +0100
   4 Subject: [PATCH] pinctrl: sunxi: Add H3 PIO controller support
   5
   6 The H3 uses the same pin controller as previous SoC's from Allwinner.
   7 Add support for the pins controlled by the main PIO controller.
   8
   9 Signed-off-by: Jens Kuske <jenskuske@gmail.com>
  10 Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
  11 ---
  12  .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt   |   1 +
  13  drivers/pinctrl/sunxi/Kconfig                      |   4 +
  14  drivers/pinctrl/sunxi/Makefile                     |   1 +
  15  drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c           | 516 +++++++++++++++++++++
  16  4 files changed, 522 insertions(+)
  17  create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c
  18
  19 diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
  20 index b321b26..e6ba602 100644
  21 --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
  22 +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
  23 @@ -18,6 +18,7 @@ Required properties:
  24    "allwinner,sun8i-a23-r-pinctrl"
  25    "allwinner,sun8i-a33-pinctrl"
  26    "allwinner,sun8i-a83t-pinctrl"
  27 +  "allwinner,sun8i-h3-pinctrl"
  28
  29  - reg: Should contain the register physical address and length for the
  30    pin controller.
  31 diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
  32 index e68fd95..89ab7f5 100644
  33 --- a/drivers/pinctrl/sunxi/Kconfig
  34 +++ b/drivers/pinctrl/sunxi/Kconfig
  35 @@ -51,6 +51,10 @@ config PINCTRL_SUN8I_A23_R
  36         depends on RESET_CONTROLLER
  37         select PINCTRL_SUNXI_COMMON
  38
  39 +config PINCTRL_SUN8I_H3
  40 +       def_bool MACH_SUN8I
  41 +       select PINCTRL_SUNXI_COMMON
  42 +
  43  config PINCTRL_SUN9I_A80
  44         def_bool MACH_SUN9I
  45         select PINCTRL_SUNXI_COMMON
  46 diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
  47 index e080290..6bd818e 100644
  48 --- a/drivers/pinctrl/sunxi/Makefile
  49 +++ b/drivers/pinctrl/sunxi/Makefile
  50 @@ -13,4 +13,5 @@ obj-$(CONFIG_PINCTRL_SUN8I_A23)               += pinctrl-sun8i-a23.o
  51  obj-$(CONFIG_PINCTRL_SUN8I_A23_R)      += pinctrl-sun8i-a23-r.o
  52  obj-$(CONFIG_PINCTRL_SUN8I_A33)                += pinctrl-sun8i-a33.o
  53  obj-$(CONFIG_PINCTRL_SUN8I_A83T)       += pinctrl-sun8i-a83t.o
  54 +obj-$(CONFIG_PINCTRL_SUN8I_H3)         += pinctrl-sun8i-h3.o
  55  obj-$(CONFIG_PINCTRL_SUN9I_A80)                += pinctrl-sun9i-a80.o
  56 diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c
  57 new file mode 100644
  58 index 0000000..98d465d
  59 --- /dev/null
  60 +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c
  61 @@ -0,0 +1,516 @@
  62 +/*
  63 + * Allwinner H3 SoCs pinctrl driver.
  64 + *
  65 + * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
  66 + *
  67 + * Based on pinctrl-sun8i-a23.c, which is:
  68 + * Copyright (C) 2014 Chen-Yu Tsai <wens@csie.org>
  69 + * Copyright (C) 2014 Maxime Ripard <maxime.ripard@free-electrons.com>
  70 + *
  71 + * This file is licensed under the terms of the GNU General Public
  72 + * License version 2.  This program is licensed "as is" without any
  73 + * warranty of any kind, whether express or implied.
  74 + */
  75 +
  76 +#include <linux/module.h>
  77 +#include <linux/platform_device.h>
  78 +#include <linux/of.h>
  79 +#include <linux/of_device.h>
  80 +#include <linux/pinctrl/pinctrl.h>
  81 +
  82 +#include "pinctrl-sunxi.h"
  83 +
  84 +static const struct sunxi_desc_pin sun8i_h3_pins[] = {
  85 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
  86 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
  87 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
  88 +                 SUNXI_FUNCTION(0x2, "uart2"),         /* TX */
  89 +                 SUNXI_FUNCTION(0x3, "jtag"),          /* MS */
  90 +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),  /* PA_EINT0 */
  91 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
  92 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
  93 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
  94 +                 SUNXI_FUNCTION(0x2, "uart2"),         /* RX */
  95 +                 SUNXI_FUNCTION(0x3, "jtag"),          /* CK */
  96 +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),  /* PA_EINT1 */
  97 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
  98 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
  99 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 100 +                 SUNXI_FUNCTION(0x2, "uart2"),         /* RTS */
 101 +                 SUNXI_FUNCTION(0x3, "jtag"),          /* DO */
 102 +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),  /* PA_EINT2 */
 103 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
 104 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 105 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 106 +                 SUNXI_FUNCTION(0x2, "uart2"),         /* CTS */
 107 +                 SUNXI_FUNCTION(0x3, "jtag"),          /* DI */
 108 +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),  /* PA_EINT3 */
 109 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
 110 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 111 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 112 +                 SUNXI_FUNCTION(0x2, "uart0"),         /* TX */
 113 +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),  /* PA_EINT4 */
 114 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
 115 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 116 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 117 +                 SUNXI_FUNCTION(0x2, "uart0"),         /* RX */
 118 +                 SUNXI_FUNCTION(0x3, "pwm0"),
 119 +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)),  /* PA_EINT5 */
 120 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
 121 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 122 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 123 +                 SUNXI_FUNCTION(0x2, "sim"),           /* PWREN */
 124 +                 SUNXI_FUNCTION(0x3, "pwm1"),
 125 +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)),  /* PA_EINT6 */
 126 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
 127 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 128 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 129 +                 SUNXI_FUNCTION(0x2, "sim"),           /* CLK */
 130 +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)),  /* PA_EINT7 */
 131 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
 132 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 133 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 134 +                 SUNXI_FUNCTION(0x2, "sim"),           /* DATA */
 135 +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),  /* PA_EINT8 */
 136 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
 137 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 138 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 139 +                 SUNXI_FUNCTION(0x2, "sim"),           /* RST */
 140 +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)),  /* PA_EINT9 */
 141 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10),
 142 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 143 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 144 +                 SUNXI_FUNCTION(0x2, "sim"),           /* DET */
 145 +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PA_EINT10 */
 146 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11),
 147 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 148 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 149 +                 SUNXI_FUNCTION(0x2, "i2c0"),          /* SCK */
 150 +                 SUNXI_FUNCTION(0x3, "di"),            /* TX */
 151 +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PA_EINT11 */
 152 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12),
 153 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 154 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 155 +                 SUNXI_FUNCTION(0x2, "i2c0"),          /* SDA */
 156 +                 SUNXI_FUNCTION(0x3, "di"),            /* RX */
 157 +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PA_EINT12 */
 158 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13),
 159 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 160 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 161 +                 SUNXI_FUNCTION(0x2, "spi1"),          /* CS */
 162 +                 SUNXI_FUNCTION(0x3, "uart3"),         /* TX */
 163 +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)), /* PA_EINT13 */
 164 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14),
 165 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 166 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 167 +                 SUNXI_FUNCTION(0x2, "spi1"),          /* CLK */
 168 +                 SUNXI_FUNCTION(0x3, "uart3"),         /* RX */
 169 +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)), /* PA_EINT14 */
 170 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15),
 171 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 172 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 173 +                 SUNXI_FUNCTION(0x2, "spi1"),          /* MOSI */
 174 +                 SUNXI_FUNCTION(0x3, "uart3"),         /* RTS */
 175 +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), /* PA_EINT15 */
 176 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
 177 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 178 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 179 +                 SUNXI_FUNCTION(0x2, "spi1"),          /* MISO */
 180 +                 SUNXI_FUNCTION(0x3, "uart3"),         /* CTS */
 181 +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), /* PA_EINT16 */
 182 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
 183 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 184 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 185 +                 SUNXI_FUNCTION(0x2, "spdif"),         /* OUT */
 186 +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)), /* PA_EINT17 */
 187 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 18),
 188 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 189 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 190 +                 SUNXI_FUNCTION(0x2, "i2s0"),          /* SYNC */
 191 +                 SUNXI_FUNCTION(0x3, "i2c1"),          /* SCK */
 192 +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)), /* PA_EINT18 */
 193 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 19),
 194 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 195 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 196 +                 SUNXI_FUNCTION(0x2, "i2s0"),          /* CLK */
 197 +                 SUNXI_FUNCTION(0x3, "i2c1"),          /* SDA */
 198 +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 19)), /* PA_EINT19 */
 199 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 20),
 200 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 201 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 202 +                 SUNXI_FUNCTION(0x2, "i2s0"),          /* DOUT */
 203 +                 SUNXI_FUNCTION(0x3, "sim"),           /* VPPEN */
 204 +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 20)), /* PA_EINT20 */
 205 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 21),
 206 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 207 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 208 +                 SUNXI_FUNCTION(0x2, "i2s0"),          /* DIN */
 209 +                 SUNXI_FUNCTION(0x3, "sim"),           /* VPPPP */
 210 +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 21)), /* PA_EINT21 */
 211 +       /* Hole */
 212 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
 213 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 214 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 215 +                 SUNXI_FUNCTION(0x2, "nand0"),         /* WE */
 216 +                 SUNXI_FUNCTION(0x3, "spi0")),         /* MOSI */
 217 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
 218 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 219 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 220 +                 SUNXI_FUNCTION(0x2, "nand0"),         /* ALE */
 221 +                 SUNXI_FUNCTION(0x3, "spi0")),         /* MISO */
 222 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
 223 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 224 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 225 +                 SUNXI_FUNCTION(0x2, "nand0"),         /* CLE */
 226 +                 SUNXI_FUNCTION(0x3, "spi0")),         /* CLK */
 227 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
 228 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 229 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 230 +                 SUNXI_FUNCTION(0x2, "nand0"),         /* CE1 */
 231 +                 SUNXI_FUNCTION(0x3, "spi0")),         /* CS */
 232 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
 233 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 234 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 235 +                 SUNXI_FUNCTION(0x2, "nand0")),        /* CE0 */
 236 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
 237 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 238 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 239 +                 SUNXI_FUNCTION(0x2, "nand0"),         /* RE */
 240 +                 SUNXI_FUNCTION(0x3, "mmc2")),         /* CLK */
 241 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
 242 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 243 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 244 +                 SUNXI_FUNCTION(0x2, "nand0"),         /* RB0 */
 245 +                 SUNXI_FUNCTION(0x3, "mmc2")),         /* CMD */
 246 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
 247 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 248 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 249 +                 SUNXI_FUNCTION(0x2, "nand0")),        /* RB1 */
 250 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
 251 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 252 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 253 +                 SUNXI_FUNCTION(0x2, "nand0"),         /* DQ0 */
 254 +                 SUNXI_FUNCTION(0x3, "mmc2")),         /* D0 */
 255 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
 256 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 257 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 258 +                 SUNXI_FUNCTION(0x2, "nand0"),         /* DQ1 */
 259 +                 SUNXI_FUNCTION(0x3, "mmc2")),         /* D1 */
 260 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
 261 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 262 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 263 +                 SUNXI_FUNCTION(0x2, "nand0"),         /* DQ2 */
 264 +                 SUNXI_FUNCTION(0x3, "mmc2")),         /* D2 */
 265 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
 266 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 267 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 268 +                 SUNXI_FUNCTION(0x2, "nand0"),         /* DQ3 */
 269 +                 SUNXI_FUNCTION(0x3, "mmc2")),         /* D3 */
 270 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
 271 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 272 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 273 +                 SUNXI_FUNCTION(0x2, "nand0"),         /* DQ4 */
 274 +                 SUNXI_FUNCTION(0x3, "mmc2")),         /* D4 */
 275 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
 276 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 277 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 278 +                 SUNXI_FUNCTION(0x2, "nand0"),         /* DQ5 */
 279 +                 SUNXI_FUNCTION(0x3, "mmc2")),         /* D5 */
 280 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
 281 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 282 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 283 +                 SUNXI_FUNCTION(0x2, "nand"),          /* DQ6 */
 284 +                 SUNXI_FUNCTION(0x3, "mmc2")),         /* D6 */
 285 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
 286 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 287 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 288 +                 SUNXI_FUNCTION(0x2, "nand"),          /* DQ7 */
 289 +                 SUNXI_FUNCTION(0x3, "mmc2")),         /* D7 */
 290 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
 291 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 292 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 293 +                 SUNXI_FUNCTION(0x2, "nand"),          /* DQS */
 294 +                 SUNXI_FUNCTION(0x3, "mmc2")),         /* RST */
 295 +       /* Hole */
 296 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
 297 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 298 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 299 +                 SUNXI_FUNCTION(0x2, "emac")),         /* RXD3 */
 300 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
 301 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 302 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 303 +                 SUNXI_FUNCTION(0x2, "emac")),         /* RXD2 */
 304 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
 305 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 306 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 307 +                 SUNXI_FUNCTION(0x2, "emac")),         /* RXD1 */
 308 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
 309 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 310 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 311 +                 SUNXI_FUNCTION(0x2, "emac")),         /* RXD0 */
 312 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
 313 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 314 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 315 +                 SUNXI_FUNCTION(0x2, "emac")),         /* RXCK */
 316 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
 317 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 318 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 319 +                 SUNXI_FUNCTION(0x2, "emac")),         /* RXCTL/RCDV */
 320 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
 321 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 322 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 323 +                 SUNXI_FUNCTION(0x2, "emac")),         /* RXERR */
 324 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
 325 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 326 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 327 +                 SUNXI_FUNCTION(0x2, "emac")),         /* TXD3 */
 328 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
 329 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 330 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 331 +                 SUNXI_FUNCTION(0x2, "emac")),         /* TXD2L */
 332 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
 333 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 334 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 335 +                 SUNXI_FUNCTION(0x2, "emac")),         /* TXD1 */
 336 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
 337 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 338 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 339 +                 SUNXI_FUNCTION(0x2, "emac")),         /* TXD0 */
 340 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
 341 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 342 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 343 +                 SUNXI_FUNCTION(0x2, "emac")),         /* CRS */
 344 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
 345 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 346 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 347 +                 SUNXI_FUNCTION(0x2, "emac")),         /* TXCK */
 348 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
 349 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 350 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 351 +                 SUNXI_FUNCTION(0x2, "emac")),         /* TXCTL/TXEN */
 352 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
 353 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 354 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 355 +                 SUNXI_FUNCTION(0x2, "emac")),         /* TXERR */
 356 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
 357 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 358 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 359 +                 SUNXI_FUNCTION(0x2, "emac")),         /* CLKIN/COL */
 360 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
 361 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 362 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 363 +                 SUNXI_FUNCTION(0x2, "emac")),         /* MDC */
 364 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
 365 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 366 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 367 +                 SUNXI_FUNCTION(0x2, "emac")),         /* MDIO */
 368 +       /* Hole */
 369 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
 370 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 371 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 372 +                 SUNXI_FUNCTION(0x2, "csi"),           /* PCLK */
 373 +                 SUNXI_FUNCTION(0x3, "ts")),           /* CLK */
 374 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
 375 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 376 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 377 +                 SUNXI_FUNCTION(0x2, "csi"),           /* MCLK */
 378 +                 SUNXI_FUNCTION(0x3, "ts")),           /* ERR */
 379 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
 380 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 381 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 382 +                 SUNXI_FUNCTION(0x2, "csi"),           /* HSYNC */
 383 +                 SUNXI_FUNCTION(0x3, "ts")),           /* SYNC */
 384 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
 385 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 386 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 387 +                 SUNXI_FUNCTION(0x2, "csi"),           /* VSYNC */
 388 +                 SUNXI_FUNCTION(0x3, "ts")),           /* DVLD */
 389 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
 390 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 391 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 392 +                 SUNXI_FUNCTION(0x2, "csi"),           /* D0 */
 393 +                 SUNXI_FUNCTION(0x3, "ts")),           /* D0 */
 394 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
 395 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 396 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 397 +                 SUNXI_FUNCTION(0x2, "csi"),           /* D1 */
 398 +                 SUNXI_FUNCTION(0x3, "ts")),           /* D1 */
 399 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
 400 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 401 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 402 +                 SUNXI_FUNCTION(0x2, "csi"),           /* D2 */
 403 +                 SUNXI_FUNCTION(0x3, "ts")),           /* D2 */
 404 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
 405 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 406 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 407 +                 SUNXI_FUNCTION(0x2, "csi"),           /* D3 */
 408 +                 SUNXI_FUNCTION(0x3, "ts")),           /* D3 */
 409 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
 410 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 411 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 412 +                 SUNXI_FUNCTION(0x2, "csi"),           /* D4 */
 413 +                 SUNXI_FUNCTION(0x3, "ts")),           /* D4 */
 414 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
 415 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 416 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 417 +                 SUNXI_FUNCTION(0x2, "csi"),           /* D5 */
 418 +                 SUNXI_FUNCTION(0x3, "ts")),           /* D5 */
 419 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
 420 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 421 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 422 +                 SUNXI_FUNCTION(0x2, "csi"),           /* D6 */
 423 +                 SUNXI_FUNCTION(0x3, "ts")),           /* D6 */
 424 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
 425 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 426 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 427 +                 SUNXI_FUNCTION(0x2, "csi"),           /* D7 */
 428 +                 SUNXI_FUNCTION(0x3, "ts")),           /* D7 */
 429 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
 430 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 431 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 432 +                 SUNXI_FUNCTION(0x2, "csi"),           /* SCK */
 433 +                 SUNXI_FUNCTION(0x3, "i2c2")),         /* SCK */
 434 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
 435 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 436 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 437 +                 SUNXI_FUNCTION(0x2, "csi"),           /* SDA */
 438 +                 SUNXI_FUNCTION(0x3, "i2c2")),         /* SDA */
 439 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
 440 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 441 +                 SUNXI_FUNCTION(0x1, "gpio_out")),
 442 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
 443 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 444 +                 SUNXI_FUNCTION(0x1, "gpio_out")),
 445 +       /* Hole */
 446 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
 447 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 448 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 449 +                 SUNXI_FUNCTION(0x2, "mmc0"),          /* D1 */
 450 +                 SUNXI_FUNCTION(0x3, "jtag")),         /* MS */
 451 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
 452 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 453 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 454 +                 SUNXI_FUNCTION(0x2, "mmc0"),          /* D0 */
 455 +                 SUNXI_FUNCTION(0x3, "jtag")),         /* DI */
 456 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
 457 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 458 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 459 +                 SUNXI_FUNCTION(0x2, "mmc0"),          /* CLK */
 460 +                 SUNXI_FUNCTION(0x3, "uart0")),        /* TX */
 461 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
 462 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 463 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 464 +                 SUNXI_FUNCTION(0x2, "mmc0"),          /* CMD */
 465 +                 SUNXI_FUNCTION(0x3, "jtag")),         /* DO */
 466 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
 467 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 468 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 469 +                 SUNXI_FUNCTION(0x2, "mmc0"),          /* D3 */
 470 +                 SUNXI_FUNCTION(0x3, "uart0")),        /* RX */
 471 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
 472 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 473 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 474 +                 SUNXI_FUNCTION(0x2, "mmc0"),          /* D2 */
 475 +                 SUNXI_FUNCTION(0x3, "jtag")),         /* CK */
 476 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6),
 477 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 478 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 479 +                 SUNXI_FUNCTION(0x2, "mmc0")),         /* DET */
 480 +       /* Hole */
 481 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
 482 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 483 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 484 +                 SUNXI_FUNCTION(0x2, "mmc1"),          /* CLK */
 485 +                 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 0)),  /* PG_EINT0 */
 486 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
 487 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 488 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 489 +                 SUNXI_FUNCTION(0x2, "mmc1"),          /* CMD */
 490 +                 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 1)),  /* PG_EINT1 */
 491 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
 492 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 493 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 494 +                 SUNXI_FUNCTION(0x2, "mmc1"),          /* D0 */
 495 +                 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 2)),  /* PG_EINT2 */
 496 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
 497 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 498 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 499 +                 SUNXI_FUNCTION(0x2, "mmc1"),          /* D1 */
 500 +                 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 3)),  /* PG_EINT3 */
 501 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
 502 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 503 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 504 +                 SUNXI_FUNCTION(0x2, "mmc1"),          /* D2 */
 505 +                 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 4)),  /* PG_EINT4 */
 506 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
 507 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 508 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 509 +                 SUNXI_FUNCTION(0x2, "mmc1"),          /* D3 */
 510 +                 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 5)),  /* PG_EINT5 */
 511 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
 512 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 513 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 514 +                 SUNXI_FUNCTION(0x2, "uart1"),         /* TX */
 515 +                 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 6)),  /* PG_EINT6 */
 516 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
 517 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 518 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 519 +                 SUNXI_FUNCTION(0x2, "uart1"),         /* RX */
 520 +                 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 7)),  /* PG_EINT7 */
 521 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
 522 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 523 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 524 +                 SUNXI_FUNCTION(0x2, "uart1"),         /* RTS */
 525 +                 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 8)),  /* PG_EINT8 */
 526 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
 527 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 528 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 529 +                 SUNXI_FUNCTION(0x2, "uart1"),         /* CTS */
 530 +                 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 9)),  /* PG_EINT9 */
 531 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
 532 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 533 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 534 +                 SUNXI_FUNCTION(0x2, "i2s1"),          /* SYNC */
 535 +                 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 10)), /* PG_EINT10 */
 536 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
 537 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 538 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 539 +                 SUNXI_FUNCTION(0x2, "i2s1"),          /* CLK */
 540 +                 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 11)), /* PG_EINT11 */
 541 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
 542 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 543 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 544 +                 SUNXI_FUNCTION(0x2, "i2s1"),          /* DOUT */
 545 +                 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 12)), /* PG_EINT12 */
 546 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
 547 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 548 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 549 +                 SUNXI_FUNCTION(0x2, "i2s1"),          /* DIN */
 550 +                 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 13)), /* PG_EINT13 */
 551 +};
 552 +
 553 +static const struct sunxi_pinctrl_desc sun8i_h3_pinctrl_data = {
 554 +       .pins = sun8i_h3_pins,
 555 +       .npins = ARRAY_SIZE(sun8i_h3_pins),
 556 +       .irq_banks = 2,
 557 +};
 558 +
 559 +static int sun8i_h3_pinctrl_probe(struct platform_device *pdev)
 560 +{
 561 +       return sunxi_pinctrl_init(pdev,
 562 +                                 &sun8i_h3_pinctrl_data);
 563 +}
 564 +
 565 +static const struct of_device_id sun8i_h3_pinctrl_match[] = {
 566 +       { .compatible = "allwinner,sun8i-h3-pinctrl", },
 567 +       {}
 568 +};
 569 +
 570 +static struct platform_driver sun8i_h3_pinctrl_driver = {
 571 +       .probe  = sun8i_h3_pinctrl_probe,
 572 +       .driver = {
 573 +               .name           = "sun8i-h3-pinctrl",
 574 +               .of_match_table = sun8i_h3_pinctrl_match,
 575 +       },
 576 +};
 577 +builtin_platform_driver(sun8i_h3_pinctrl_driver);