1 From e53f67e981bcc5547857475241b3a4a066955f8c Mon Sep 17 00:00:00 2001
2 From: Corentin Labbe <clabbe.montjoie@gmail.com>
3 Date: Wed, 31 May 2017 09:18:46 +0200
4 Subject: arm64: allwinner: sun50i-a64: add dwmac-sun8i Ethernet driver
6 The dwmac-sun8i is an Ethernet MAC that supports 10/100/1000 Mbit
7 connections. It is very similar to the device found in the Allwinner
8 H3, but lacks the internal 100 Mbit PHY and its associated control
10 This adds the necessary bits to the Allwinner A64 SoC .dtsi, but keeps
11 it disabled at this level.
13 Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
14 Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
16 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 35 +++++++++++++++++++++++++++
17 1 file changed, 35 insertions(+)
19 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
20 +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
25 + rmii_pins: rmii_pins {
26 + pins = "PD10", "PD11", "PD13", "PD14", "PD17",
27 + "PD18", "PD19", "PD20", "PD22", "PD23";
29 + drive-strength = <40>;
32 + rgmii_pins: rgmii_pins {
33 + pins = "PD8", "PD9", "PD10", "PD11", "PD12",
34 + "PD13", "PD15", "PD16", "PD17", "PD18",
35 + "PD19", "PD20", "PD21", "PD22", "PD23";
37 + drive-strength = <40>;
40 uart0_pins_a: uart0@0 {
47 + emac: ethernet@1c30000 {
48 + compatible = "allwinner,sun50i-a64-emac";
50 + reg = <0x01c30000 0x100>;
51 + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
52 + interrupt-names = "macirq";
53 + resets = <&ccu RST_BUS_EMAC>;
54 + reset-names = "stmmaceth";
55 + clocks = <&ccu CLK_BUS_EMAC>;
56 + clock-names = "stmmaceth";
57 + status = "disabled";
58 + #address-cells = <1>;
62 + #address-cells = <1>;
67 gic: interrupt-controller@1c81000 {
68 compatible = "arm,gic-400";
69 reg = <0x01c81000 0x1000>,