1 From 0eba511a3cac29d6338b22b5b727f40cf8d163df Mon Sep 17 00:00:00 2001
2 From: Corentin Labbe <clabbe.montjoie@gmail.com>
3 Date: Wed, 31 May 2017 09:18:38 +0200
4 Subject: arm: sun8i: sunxi-h3-h5: add dwmac-sun8i ethernet driver
6 The dwmac-sun8i is an ethernet MAC hardware that support 10/100/1000
9 This patch enable the dwmac-sun8i on Allwinner H3/H5 SoC Device-tree.
10 SoC H3/H5 have an internal PHY, so optionals syscon and ephy are set.
12 Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
13 Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
15 arch/arm/boot/dts/sunxi-h3-h5.dtsi | 34 ++++++++++++++++++++++++++++++++++
16 1 file changed, 34 insertions(+)
18 --- a/arch/arm/boot/dts/sun8i-h3.dtsi
19 +++ b/arch/arm/boot/dts/sun8i-h3.dtsi
22 #interrupt-cells = <3>;
24 + emac_rgmii_pins: emac0 {
25 + pins = "PD0", "PD1", "PD2", "PD3", "PD4",
26 + "PD5", "PD7", "PD8", "PD9", "PD10",
27 + "PD12", "PD13", "PD15", "PD16", "PD17";
29 + drive-strength = <40>;
33 allwinner,pins = "PA11", "PA12";
34 allwinner,function = "i2c0";
39 + emac: ethernet@1c30000 {
40 + compatible = "allwinner,sun8i-h3-emac";
42 + reg = <0x01c30000 0x104>;
43 + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
44 + interrupt-names = "macirq";
45 + resets = <&ccu RST_BUS_EMAC>;
46 + reset-names = "stmmaceth";
47 + clocks = <&ccu CLK_BUS_EMAC>;
48 + clock-names = "stmmaceth";
49 + #address-cells = <1>;
51 + status = "disabled";
54 + #address-cells = <1>;
56 + int_mii_phy: ethernet-phy@1 {
57 + compatible = "ethernet-phy-ieee802.3-c22";
59 + clocks = <&ccu CLK_BUS_EPHY>;
60 + resets = <&ccu RST_BUS_EPHY>;
65 wdt0: watchdog@01c20ca0 {
66 compatible = "allwinner,sun6i-a31-wdt";
67 reg = <0x01c20ca0 0x20>;