1 From: Jernej Skrabec <jernej.skrabec@siol.net>
3 Allwinner H6 PWM is similar to that in A20 except that it has additional
4 bus clock and reset line.
6 Note that first PWM channel is connected to output pin and second
7 channel is used internally, as a clock source to AC200 co-packaged chip.
8 This means that any combination of these two channels can be used and
9 thus it doesn't make sense to add pinctrl nodes at this point.
11 Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
12 Signed-off-by: Clément Péron <peron.clem@gmail.com>
14 arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 10 ++++++++++
15 1 file changed, 10 insertions(+)
17 diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
18 index 29824081b43b..6d4bde488f15 100644
19 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
20 +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
26 + compatible = "allwinner,sun50i-h6-pwm";
27 + reg = <0x0300a000 0x400>;
28 + clocks = <&osc24M>, <&ccu CLK_BUS_PWM>;
29 + clock-names = "mod", "bus";
30 + resets = <&ccu RST_BUS_PWM>;
32 + status = "disabled";
35 pio: pinctrl@300b000 {
36 compatible = "allwinner,sun50i-h6-pinctrl";
37 reg = <0x0300b000 0x400>;