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[ubicom32]: move new files out from platform support patch
[openwrt/svn-archive/archive.git] / target / linux / ubicom32 / files / drivers / mtd / devices / ubi32-nand-spi-er.c
1 /*
2 * Micron SPI-ER NAND Flash Memory
3 * This code uses the built in Ubicom flash controller
4 *
5 * (C) Copyright 2009, Ubicom, Inc.
6 *
7 * This file is part of the Ubicom32 Linux Kernel Port.
8 *
9 * The Ubicom32 Linux Kernel Port is free software: you can redistribute
10 * it and/or modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation, either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * The Ubicom32 Linux Kernel Port is distributed in the hope that it
15 * will be useful, but WITHOUT ANY WARRANTY; without even the implied
16 * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
17 * the GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with the Ubicom32 Linux Kernel Port. If not,
21 * see <http://www.gnu.org/licenses/>.
22 */
23 #include <linux/module.h>
24 #include <linux/init.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
27 #include <linux/device.h>
28 #include <linux/platform_device.h>
29 #include <linux/mutex.h>
30 #include <linux/err.h>
31
32 #include <linux/mtd/mtd.h>
33 #include <linux/mtd/partitions.h>
34
35 #define DRIVER_NAME "ubi32-nand-spi-er"
36 #define UBI32_NAND_SPI_ER_BLOCK_FROM_ROW(row) (row >> 6)
37
38 #define UBI32_NAND_SPI_ER_STATUS_P_FAIL (1 << 3)
39 #define UBI32_NAND_SPI_ER_STATUS_E_FAIL (1 << 2)
40 #define UBI32_NAND_SPI_ER_STATUS_OIP (1 << 0)
41
42 #define UBI32_NAND_SPI_ER_LAST_ROW_INVALID 0xFFFFFFFF
43 #define UBI32_NAND_SPI_ER_BAD_BLOCK_MARK_OFFSET 0x08
44
45 struct ubi32_nand_spi_er_device {
46 const char *name;
47
48 uint16_t id;
49
50 unsigned int blocks;
51 unsigned int pages_per_block;
52 unsigned int page_size;
53 unsigned int write_size;
54 unsigned int erase_size;
55 };
56
57 struct ubi32_nand_spi_er {
58 char name[24];
59
60 const struct ubi32_nand_spi_er_device *device;
61
62 struct mutex lock;
63 struct platform_device *pdev;
64
65 struct mtd_info mtd;
66
67 unsigned int last_row; /* the last row we fetched */
68
69 /*
70 * Bad block table (MUST be last in strcuture)
71 */
72 unsigned long nbb;
73 unsigned long bbt[0];
74 };
75
76 /*
77 * Chip supports a write_size of 512, but we cannot do partial
78 * page with command 0x84.
79 *
80 * We need to use command 0x84 because we cannot fill the FIFO fast
81 * enough to transfer the whole 512 bytes at a time. (maybe through
82 * OCM?)
83 */
84 const struct ubi32_nand_spi_er_device ubi32_nand_spi_er_devices[] = {
85 {
86 name: "MT29F1G01ZDC",
87 id: 0x2C12,
88 blocks: 1024,
89 pages_per_block: 64,
90 page_size: 2048,
91 write_size: 2048,
92 erase_size: 64 * 2048,
93 },
94 {
95 name: "MT29F1G01ZDC",
96 id: 0x2C13,
97 blocks: 1024,
98 pages_per_block: 64,
99 page_size: 2048,
100 write_size: 2048,
101 erase_size: 64 * 2048,
102 },
103 };
104
105 static int read_only = 0;
106 module_param(read_only, int, 0);
107 MODULE_PARM_DESC(read_only, "Leave device locked");
108
109 /*
110 * Ubicom32 FLASH Command Set
111 */
112 #define FLASH_PORT RA
113
114 #define FLASH_FC_INST_CMD 0x00 /* for SPI command only transaction */
115 #define FLASH_FC_INST_WR 0x01 /* for SPI write transaction */
116 #define FLASH_FC_INST_RD 0x02 /* for SPI read transaction */
117
118 #define FLASH_COMMAND_KICK_OFF(io) \
119 asm volatile( \
120 " bset "D(IO_INT_CLR)"(%0), #0, #%%bit("D(IO_XFL_INT_DONE)") \n\t" \
121 " jmpt.t .+4 \n\t" \
122 " bset "D(IO_INT_SET)"(%0), #0, #%%bit("D(IO_XFL_INT_START)") \n\t" \
123 : \
124 : "a" (io) \
125 : "cc" \
126 );
127
128 #define FLASH_COMMAND_WAIT_FOR_COMPLETION(io) \
129 asm volatile( \
130 " btst "D(IO_INT_STATUS)"(%0), #%%bit("D(IO_XFL_INT_DONE)") \n\t" \
131 " jmpeq.f .-4 \n\t" \
132 : \
133 : "a" (io) \
134 : "cc" \
135 );
136
137 #define FLASH_COMMAND_EXEC(io) \
138 FLASH_COMMAND_KICK_OFF(io) \
139 FLASH_COMMAND_WAIT_FOR_COMPLETION(io)
140
141 /*
142 * ubi32_nand_spi_er_get_feature
143 * Get Feature register
144 */
145 static uint8_t ubi32_nand_spi_er_get_feature(uint32_t reg)
146 {
147 struct ubicom32_io_port *io = (struct ubicom32_io_port *)FLASH_PORT;
148
149 /*
150 * Note that this will produce the sequence:
151 * SI [0F][REG][00][00]
152 * SO ---------[SR][SR][SR]
153 * Since the flash controller can only output 24 bits of address, this is
154 * ok for this command since the data will just repeat as long as the CS
155 * is asserted and the clock is running.
156 */
157 io->ctl1 &= ~IO_XFL_CTL1_MASK;
158 io->ctl1 |= IO_XFL_CTL1_FC_INST(FLASH_FC_INST_RD) | IO_XFL_CTL1_FC_DATA(1) |
159 IO_XFL_CTL1_FC_ADDR;
160 io->ctl2 = IO_XFL_CTL2_FC_CMD(0x0F) | IO_XFL_CTL2_FC_ADDR(reg << 16);
161 FLASH_COMMAND_EXEC(io);
162
163 return io->status1 & 0xFF;
164 }
165
166 /*
167 * ubi32_nand_spi_er_write_buf
168 * writes a buffer to the bus
169 *
170 * Writes 511 + 1 bytes to the bus, we have to stuff one data byte into the address.
171 */
172 static void ubi32_nand_spi_er_write_buf(const uint8_t *buf, uint32_t col)
173 {
174 struct ubicom32_io_port *io = (struct ubicom32_io_port *)FLASH_PORT;
175 uint32_t tmp;
176
177 asm volatile (
178 " bset "D(IO_INT_SET)"(%[port]), #0, #%%bit("D(IO_PORTX_INT_FIFO_TX_RESET)") \n\t"
179 " pipe_flush 0 \n\t"
180 :
181 : [port] "a" (FLASH_PORT)
182 : "cc"
183 );
184
185 /*
186 * Write the data into the cache
187 */
188 io->ctl1 &= ~IO_XFL_CTL1_MASK;
189 #ifdef SUPPORT_512_FIFO
190 io->ctl1 |= IO_XFL_CTL1_FC_INST(FLASH_FC_INST_WR) | IO_XFL_CTL1_FC_DATA(511) |
191 #endif
192 io->ctl1 |= IO_XFL_CTL1_FC_INST(FLASH_FC_INST_WR) | IO_XFL_CTL1_FC_DATA(31) |
193 IO_XFL_CTL1_FC_ADDR;
194
195 /*
196 * Construct the address with the first byte of data
197 */
198 tmp = (col << 8) | *buf++;
199 io->ctl2 = IO_XFL_CTL2_FC_CMD(0x84) | IO_XFL_CTL2_FC_ADDR(tmp);
200
201 asm volatile (
202
203 /*
204 * Move 32 bytes
205 *
206 * The first word needs to be [11][22][33][33] to work around a flash
207 * controller bug.
208 */
209 " move.2 %[tmp], (%[data])2++ \n\t"
210 " shmrg.1 %[tmp], (%[data]), %[tmp] \n\t"
211 " shmrg.1 %[tmp], (%[data])1++, %[tmp] \n\t"
212 " move.4 "D(IO_TX_FIFO)"(%[port]), %[tmp] \n\t"
213
214 /*
215 * We're aligned again!
216 */
217 " .rept 7 \n\t"
218 " move.4 "D(IO_TX_FIFO)"(%[port]), (%[data])4++ \n\t"
219 " .endr \n\t"
220
221 /*
222 * Kick off the flash command
223 */
224 " bset "D(IO_INT_CLR)"(%[port]), #0, #%%bit("D(IO_XFL_INT_DONE)") \n\t"
225 " jmpt.t .+4 \n\t"
226 " bset "D(IO_INT_SET)"(%[port]), #0, #%%bit("D(IO_XFL_INT_START)") \n\t"
227
228 #ifdef SUPPORT_512_FIFO
229 /*
230 * Fill the remaining 120 words as space becomes available
231 */
232 "1: \n\t"
233 " cmpi "D(IO_FIFO_LEVEL)"(%[port]), #4 \n\t"
234 " jmpgt.s.t 1b \n\t"
235 " move.4 "D(IO_TX_FIFO)"(%[port]), (%[data])4++ \n\t"
236 " move.4 "D(IO_TX_FIFO)"(%[port]), (%[data])4++ \n\t"
237 " move.4 "D(IO_TX_FIFO)"(%[port]), (%[data])4++ \n\t"
238 " move.4 "D(IO_TX_FIFO)"(%[port]), (%[data])4++ \n\t"
239 " add.4 %[cnt], #-4, %[cnt] \n\t"
240 " jmpgt.t 1b \n\t"
241 #endif
242 /*
243 * Wait for the transaction to finish
244 */
245 " btst "D(IO_INT_STATUS)"(%[port]), #%%bit("D(IO_XFL_INT_DONE)") \n\t"
246 " jmpeq.f .-4 \n\t"
247
248 : [tmp] "=&d" (tmp),
249 [data] "+&a" (buf)
250 : [column] "d" (col),
251 [port] "a" (FLASH_PORT),
252 [cnt] "d" (120) // see above comment
253 : "cc"
254 );
255 }
256
257 /*
258 * ubi32_nand_spi_er_send_rd_addr
259 * perform FC_RD: CMD + address
260 */
261 static void ubi32_nand_spi_er_send_rd_addr(uint8_t command, uint32_t address)
262 {
263 struct ubicom32_io_port *io = (struct ubicom32_io_port *)FLASH_PORT;
264
265 io->ctl1 &= ~IO_XFL_CTL1_MASK;
266 io->ctl1 |= IO_XFL_CTL1_FC_INST(FLASH_FC_INST_RD) | IO_XFL_CTL1_FC_DATA(4) |
267 IO_XFL_CTL1_FC_ADDR;
268 io->ctl2 = IO_XFL_CTL2_FC_CMD(command) | IO_XFL_CTL2_FC_ADDR(address);
269 FLASH_COMMAND_EXEC(io);
270 }
271
272 /*
273 * ubi32_nand_spi_er_send_cmd_addr
274 * perform FC_(xxx): CMD + address
275 */
276 static void ubi32_nand_spi_er_send_cmd_addr(uint8_t command, uint32_t address)
277 {
278 struct ubicom32_io_port *io = (struct ubicom32_io_port *)FLASH_PORT;
279
280 io->ctl1 &= ~IO_XFL_CTL1_MASK;
281 io->ctl1 |= IO_XFL_CTL1_FC_INST(FLASH_FC_INST_CMD) | IO_XFL_CTL1_FC_ADDR;
282 io->ctl2 = IO_XFL_CTL2_FC_CMD(command) | IO_XFL_CTL2_FC_ADDR(address);
283 FLASH_COMMAND_EXEC(io);
284 }
285
286 /*
287 * ubi32_nand_spi_er_write_disable
288 * clear the write enable bit
289 */
290 static void ubi32_nand_spi_er_write_disable(void)
291 {
292 struct ubicom32_io_port *io = (struct ubicom32_io_port *)FLASH_PORT;
293
294 io->ctl1 &= ~IO_XFL_CTL1_MASK;
295 io->ctl1 |= IO_XFL_CTL1_FC_INST(FLASH_FC_INST_CMD);
296 io->ctl2 = IO_XFL_CTL2_FC_CMD(0x04);
297 FLASH_COMMAND_EXEC(io);
298 }
299
300 /*
301 * ubi32_nand_spi_er_write_enable
302 * set the write enable bit
303 */
304 static void ubi32_nand_spi_er_write_enable(void)
305 {
306 struct ubicom32_io_port *io = (struct ubicom32_io_port *)FLASH_PORT;
307
308 io->ctl1 &= ~IO_XFL_CTL1_MASK;
309 io->ctl1 |= IO_XFL_CTL1_FC_INST(FLASH_FC_INST_CMD);
310 io->ctl2 = IO_XFL_CTL2_FC_CMD(0x06);
311 FLASH_COMMAND_EXEC(io);
312 }
313
314 /*
315 * ubi32_nand_spi_er_busywait
316 * Wait until the chip is not busy
317 */
318 static uint8_t ubi32_nand_spi_er_busywait(void)
319 {
320 int i;
321 uint8_t data;
322
323 /*
324 * tRD is 100us, so don't delay too long, however, tERS is
325 * 10ms so you'd better loop enough.
326 */
327 for (i = 0; i < 200; i++) {
328 data = ubi32_nand_spi_er_get_feature(0xC0);
329 if (!(data & UBI32_NAND_SPI_ER_STATUS_OIP)) {
330 break;
331 }
332
333 udelay(50);
334 }
335
336 return data;
337 }
338
339 /*
340 * ubi32_nand_spi_er_erase
341 * Erase a block, parameters must be block aligned
342 */
343 static int ubi32_nand_spi_er_erase(struct mtd_info *mtd, struct erase_info *instr)
344 {
345 struct ubi32_nand_spi_er *chip = mtd->priv;
346 int res;
347
348 DEBUG(MTD_DEBUG_LEVEL3, "%s: erase addr:%x len:%x\n", chip->name, instr->addr, instr->len);
349
350 if ((instr->addr + instr->len) > mtd->size) {
351 return -EINVAL;
352 }
353
354 if (instr->addr & (chip->device->erase_size - 1)) {
355 DEBUG(MTD_DEBUG_LEVEL1, "%s: erase address is not aligned %x\n", chip->name, instr->addr);
356 return -EINVAL;
357 }
358
359 if (instr->len & (chip->device->erase_size - 1)) {
360 DEBUG(MTD_DEBUG_LEVEL1, "%s: erase len is not aligned %x\n", chip->name, instr->len);
361 return -EINVAL;
362 }
363
364 mutex_lock(&chip->lock);
365 chip->last_row = UBI32_NAND_SPI_ER_LAST_ROW_INVALID;
366
367 while (instr->len) {
368 uint32_t block = instr->addr >> 17;
369 uint32_t row = block << 6;
370 uint8_t stat;
371 DEBUG(MTD_DEBUG_LEVEL3, "%s: block erase row:%x block:%x addr:%x rem:%x\n", chip->name, row, block, instr->addr, instr->len);
372
373 /*
374 * Test for bad block
375 */
376 if (test_bit(block, chip->bbt)) {
377 instr->fail_addr = block << 17;
378 instr->state = MTD_ERASE_FAILED;
379 res = -EBADMSG;
380 goto done;
381 }
382
383 ubi32_nand_spi_er_write_enable();
384
385 /*
386 * Block erase
387 */
388 ubi32_nand_spi_er_send_cmd_addr(0xD8, row);
389
390 /*
391 * Wait
392 */
393 stat = ubi32_nand_spi_er_busywait();
394 if (stat & UBI32_NAND_SPI_ER_STATUS_OIP) {
395 instr->fail_addr = block << 17;
396 instr->state = MTD_ERASE_FAILED;
397 DEBUG(MTD_DEBUG_LEVEL1, "%s: chip is busy or nonresponsive stat=%02x\n", chip->name, stat);
398
399 /*
400 * Chip is stuck?
401 */
402 res = -EIO;
403 goto done;
404 }
405
406 /*
407 * Check the status register
408 */
409 if (stat & UBI32_NAND_SPI_ER_STATUS_E_FAIL) {
410 DEBUG(MTD_DEBUG_LEVEL1, "%s: E_FAIL signalled (%02x)\n", chip->name, stat);
411 instr->fail_addr = block << 17;
412 instr->state = MTD_ERASE_FAILED;
413 goto done;
414 }
415
416 /*
417 * Next
418 */
419 block++;
420 instr->len -= chip->device->erase_size;
421 instr->addr += chip->device->erase_size;
422 }
423
424 instr->state = MTD_ERASE_DONE;
425
426 mutex_unlock(&chip->lock);
427 return 0;
428
429 done:
430 ubi32_nand_spi_er_write_disable();
431
432 mutex_unlock(&chip->lock);
433
434 mtd_erase_callback(instr);
435 return 0;
436 }
437
438 /*
439 * ubi32_nand_spi_er_read
440 *
441 * return -EUCLEAN: ecc error recovered
442 * return -EBADMSG: ecc error not recovered
443 */
444 static int ubi32_nand_spi_er_read(struct mtd_info *mtd, loff_t from, size_t len,
445 size_t *retlen, u_char *buf)
446 {
447 struct ubi32_nand_spi_er *chip = mtd->priv;
448 struct ubicom32_io_port *io = (struct ubicom32_io_port *)FLASH_PORT;
449
450 uint32_t row;
451 uint32_t column;
452 int retval = 0;
453 uint32_t *pbuf = (uint32_t *)buf;
454
455 *retlen = 0;
456 DEBUG(MTD_DEBUG_LEVEL2, "%s: read block from %llx len %d into %p\n", chip->name, from, len, buf);
457
458 /*
459 * buf should be aligned
460 */
461 if ((uint32_t)buf & 0x03) {
462 return -EINVAL;
463 }
464
465 /*
466 * Zero length reads, nothing to do
467 */
468 if (len == 0) {
469 return 0;
470 }
471
472 /*
473 * Reject reads which go over the end of the flash
474 */
475 if ((from + len) > mtd->size) {
476 return -EINVAL;
477 }
478
479 /*
480 * Get the row and column address to start at
481 */
482 row = from >> 11;
483 column = from & 0x7FF;
484 DEBUG(MTD_DEBUG_LEVEL3, "%s: row=%x %d column=%x %d last_row=%x %d\n", chip->name, row, row, column, column, chip->last_row, chip->last_row);
485
486 /*
487 * Read the data from the chip
488 */
489 mutex_lock(&chip->lock);
490 while (len) {
491 uint8_t stat;
492 size_t toread;
493 int i;
494 int tmp;
495
496 /*
497 * Figure out how much to read
498 *
499 * If we are reading from the middle of a page then the most we
500 * can read is to the end of the page
501 */
502 toread = len;
503 if (toread > (chip->device->page_size - column)) {
504 toread = chip->device->page_size - column;
505 }
506
507 DEBUG(MTD_DEBUG_LEVEL3, "%s: buf=%p toread=%x row=%x column=%x last_row=%x\n", chip->name, pbuf, toread, row, column, chip->last_row);
508
509 if (chip->last_row != row) {
510 /*
511 * Check if the block is bad
512 */
513 if (test_bit(UBI32_NAND_SPI_ER_BLOCK_FROM_ROW(row), chip->bbt)) {
514 mutex_unlock(&chip->lock);
515 return -EBADMSG;
516 }
517
518 /*
519 * Load the appropriate page
520 */
521 ubi32_nand_spi_er_send_cmd_addr(0x13, row);
522
523 /*
524 * Wait
525 */
526 stat = ubi32_nand_spi_er_busywait();
527 if (stat & UBI32_NAND_SPI_ER_STATUS_OIP) {
528 DEBUG(MTD_DEBUG_LEVEL1, "%s: chip is busy or nonresponsive stat=%02x\n", chip->name, stat);
529
530 /*
531 * Chip is stuck?
532 */
533 mutex_unlock(&chip->lock);
534 return -EIO;
535 }
536
537 /*
538 * Check the ECC bits
539 */
540 stat >>= 4;
541 if (stat == 1) {
542 DEBUG(MTD_DEBUG_LEVEL1, "%s: ECC recovered, row=%x\n", chip->name, row);
543 retval = -EUCLEAN;
544 }
545 if (stat == 2) {
546 DEBUG(MTD_DEBUG_LEVEL0, "%s: failed ECC, row=%x\n", chip->name, row);
547 chip->last_row = UBI32_NAND_SPI_ER_LAST_ROW_INVALID;
548 mutex_unlock(&chip->lock);
549 return -EBADMSG;
550 }
551
552 }
553
554 chip->last_row = row;
555
556 /*
557 * Read out the data:
558 * We can always read a little too much since there is the
559 * OOB after byte addr 2047. The most we'll overread is 3 bytes.
560 */
561 if (((uint32_t)pbuf & 0x03) == 0) {
562 /*
563 * Aligned read
564 */
565 tmp = toread & (~0x03);
566 for (i = 0; i < tmp; i += 4) {
567 ubi32_nand_spi_er_send_rd_addr(0x03, column << 8);
568 *pbuf++ = io->status1;
569 column += 4;
570 }
571 } else {
572 /*
573 * Unaligned read
574 */
575 tmp = toread & (~0x03);
576 for (i = 0; i < tmp; i += 4) {
577 ubi32_nand_spi_er_send_rd_addr(0x03, column << 8);
578 memcpy(pbuf, &io->status1, 4);
579 column += 4;
580 }
581 }
582
583 /*
584 * Fill in any single bytes
585 */
586 tmp = toread & 0x03;
587 if (tmp) {
588 uint8_t *bbuf = pbuf;
589 uint32_t val;
590 ubi32_nand_spi_er_send_rd_addr(0x03, column << 8);
591 val = io->status1;
592 for (i = 0; i < tmp; i++) {
593 *bbuf++ = val >> 24;
594 val <<= 8;
595 }
596 }
597
598 len -= toread;
599 *retlen += toread;
600
601 /*
602 * For the next page, increment the row and always start at column 0
603 */
604 column = 0;
605 row++;
606 }
607
608 mutex_unlock(&chip->lock);
609 return retval;
610 }
611
612 /*
613 * ubi32_nand_spi_er_write
614 */
615 #define WRITE_NOT_ALIGNED(x) ((x & (device->write_size - 1)) != 0)
616 static int ubi32_nand_spi_er_write(struct mtd_info *mtd, loff_t to, size_t len,
617 size_t *retlen, const u_char *buf)
618 {
619 struct ubi32_nand_spi_er *chip = mtd->priv;
620 const struct ubi32_nand_spi_er_device *device = chip->device;
621 struct ubicom32_io_port *io = (struct ubicom32_io_port *)FLASH_PORT;
622 uint32_t row;
623 uint32_t col;
624 int res = 0;
625 size_t towrite;
626
627 DEBUG(MTD_DEBUG_LEVEL2, "%s: write block to %llx len %d from %p\n", chip->name, to, len, buf);
628
629 *retlen = 0;
630
631 /*
632 * nothing to write
633 */
634 if (!len) {
635 return 0;
636 }
637
638 /*
639 * Reject writes which go over the end of the flash
640 */
641 if ((to + len) > mtd->size) {
642 return -EINVAL;
643 }
644
645 /*
646 * buf should be aligned to 16 bits
647 */
648 if ((uint32_t)buf & 0x01) {
649 return -EINVAL;
650 }
651
652 /*
653 * Check to see if everything is page aligned
654 */
655 if (WRITE_NOT_ALIGNED(to) || WRITE_NOT_ALIGNED(len)) {
656 printk(KERN_NOTICE "ubi32_nand_spi_er_write: Attempt to write non page aligned data\n");
657 return -EINVAL;
658 }
659
660 mutex_lock(&chip->lock);
661
662 io->ctl0 |= IO_XFL_CTL0_MCB_LOCK;
663
664 chip->last_row = UBI32_NAND_SPI_ER_LAST_ROW_INVALID;
665
666 /*
667 * If the first write is a partial write then write at most the number of
668 * bytes to get us page aligned and then the remainder will be
669 * page aligned. The last bit may be a partial page as well.
670 */
671 col = to & (device->page_size - 1);
672 towrite = device->page_size - col;
673 if (towrite > len) {
674 towrite = len;
675 }
676
677 /*
678 * Write the data
679 */
680 row = to >> 11;
681 while (len) {
682 uint8_t stat;
683 uint32_t my_towrite;
684
685 DEBUG(MTD_DEBUG_LEVEL3, "%s: write %p to row:%x col:%x len:%x rem:%x\n", chip->name, buf, row, col, towrite, len);
686
687 ubi32_nand_spi_er_write_enable();
688
689 /*
690 * Move the data into the cache
691 */
692 my_towrite = towrite;
693 while (my_towrite) {
694 uint32_t len = my_towrite;
695 if (len > 32) {
696 len = 32;
697 }
698
699 ubi32_nand_spi_er_write_buf(buf, col);
700 buf += len;
701 col += len;
702 my_towrite -= len;
703 }
704
705 /*
706 * Program execute
707 */
708 ubi32_nand_spi_er_send_cmd_addr(0x10, row);
709
710 /*
711 * Wait
712 */
713 stat = ubi32_nand_spi_er_busywait();
714 if (stat & UBI32_NAND_SPI_ER_STATUS_OIP) {
715 DEBUG(MTD_DEBUG_LEVEL1, "%s: chip is busy or nonresponsive stat=%02x\n", chip->name, stat);
716
717 /*
718 * Chip is stuck?
719 */
720 res = -EIO;
721 goto done;
722 }
723
724 if (stat & (1 << 3)) {
725 res = -EBADMSG;
726 goto done;
727 }
728
729 row++;
730 len -= towrite;
731 *retlen += towrite;
732
733 /*
734 * At this point, we are always page aligned so start at column 0.
735 * Note we may not have a full page to write at the end, hence the
736 * check if towrite > len.
737 */
738 col = 0;
739 towrite = device->page_size;
740 if (towrite > len) {
741 towrite = len;
742 }
743 }
744
745 io->ctl0 &= ~IO_XFL_CTL0_MCB_LOCK;
746
747 mutex_unlock(&chip->lock);
748 return res;
749
750 done:
751 ubi32_nand_spi_er_write_disable();
752
753 io->ctl0 &= ~IO_XFL_CTL0_MCB_LOCK;
754
755 mutex_unlock(&chip->lock);
756
757 return res;
758 }
759
760 /*
761 * ubi32_nand_spi_er_isbad
762 */
763 static int ubi32_nand_spi_er_isbad(struct mtd_info *mtd, loff_t ofs)
764 {
765 struct ubi32_nand_spi_er *chip = mtd->priv;
766 uint32_t block;
767
768 if (ofs & (chip->device->erase_size - 1)) {
769 DEBUG(MTD_DEBUG_LEVEL1, "%s: address not aligned %llx\n", chip->name, ofs);
770 return -EINVAL;
771 }
772
773 block = ofs >> 17;
774
775 return test_bit(block, chip->bbt);
776 }
777
778 /*
779 * ubi32_nand_spi_er_markbad
780 */
781 static int ubi32_nand_spi_er_markbad(struct mtd_info *mtd, loff_t ofs)
782 {
783 struct ubi32_nand_spi_er *chip = mtd->priv;
784 struct ubicom32_io_port *io = (struct ubicom32_io_port *)FLASH_PORT;
785 uint32_t block;
786 uint32_t row;
787 int res = 0;
788 uint8_t stat;
789
790 if (ofs & (chip->device->erase_size - 1)) {
791 DEBUG(MTD_DEBUG_LEVEL1, "%s: address not aligned %llx\n", chip->name, ofs);
792 return -EINVAL;
793 }
794
795 block = ofs >> 17;
796
797 /*
798 * If it's already marked bad, no need to mark it
799 */
800 if (test_bit(block, chip->bbt)) {
801 return 0;
802 }
803
804 /*
805 * Mark it in our cache
806 */
807 __set_bit(block, chip->bbt);
808
809 /*
810 * Write the user bad block mark. If it fails, then we really
811 * can't do anything about it.
812 */
813 mutex_lock(&chip->lock);
814 chip->last_row = UBI32_NAND_SPI_ER_LAST_ROW_INVALID;
815
816 ubi32_nand_spi_er_write_enable();
817
818 /*
819 * Write the mark
820 */
821 io->ctl0 |= IO_XFL_CTL0_MCB_LOCK;
822 io->ctl1 &= ~IO_XFL_CTL1_MASK;
823 io->ctl1 |= IO_XFL_CTL1_FC_INST(FLASH_FC_INST_WR) | IO_XFL_CTL1_FC_DATA(6);
824 io->ctl2 = IO_XFL_CTL2_FC_CMD(0x84);
825
826 asm volatile (
827 " bset "D(IO_INT_SET)"(%[port]), #0, #%%bit("D(IO_PORTX_INT_FIFO_TX_RESET)") \n\t"
828 " pipe_flush 0 \n\t"
829
830 /*
831 * Move the data into the FIFO
832 */
833 " move.4 "D(IO_TX_FIFO)"(%[port]), %[word1] \n\t"
834 " move.4 "D(IO_TX_FIFO)"(%[port]), %[word2] \n\t"
835
836 /*
837 * Kick off the flash command
838 */
839 " bset "D(IO_INT_CLR)"(%[port]), #0, #%%bit("D(IO_XFL_INT_DONE)") \n\t"
840 " jmpt.t .+4 \n\t"
841 " bset "D(IO_INT_SET)"(%[port]), #0, #%%bit("D(IO_XFL_INT_START)") \n\t"
842
843 /*
844 * Wait for the transaction to finish
845 */
846 " btst "D(IO_INT_STATUS)"(%[port]), #%%bit("D(IO_XFL_INT_DONE)") \n\t"
847 " jmpeq.f .-4 \n\t"
848
849 :
850 : [word1] "d" (0x0800dead | (UBI32_NAND_SPI_ER_BAD_BLOCK_MARK_OFFSET << 16)),
851 [word2] "d" (0xbeef0000),
852 [port] "a" (FLASH_PORT)
853 : "cc"
854 );
855
856 io->ctl0 &= ~IO_XFL_CTL0_MCB_LOCK;
857
858 /*
859 * Program execute
860 */
861 row = block << 6;
862 ubi32_nand_spi_er_send_cmd_addr(0x10, row);
863
864 /*
865 * Wait
866 */
867 stat = ubi32_nand_spi_er_busywait();
868 if (stat & UBI32_NAND_SPI_ER_STATUS_OIP) {
869 DEBUG(MTD_DEBUG_LEVEL1, "%s: chip is busy or nonresponsive stat=%02x\n", chip->name, stat);
870
871 /*
872 * Chip is stuck?
873 */
874 res = -EIO;
875 goto done;
876 }
877
878 if (stat & (1 << 3)) {
879 res = -EBADMSG;
880 }
881
882 done:
883 ubi32_nand_spi_er_write_disable();
884
885 mutex_unlock(&chip->lock);
886
887 return res;
888 }
889
890 /*
891 * ubi32_nand_spi_er_read_bbt
892 */
893 static int ubi32_nand_spi_er_read_bbt(struct ubi32_nand_spi_er *chip)
894 {
895 int j;
896 struct ubicom32_io_port *io = (struct ubicom32_io_port *)FLASH_PORT;
897
898 for (j = 0; j < chip->device->blocks; j++) {
899 unsigned short row = j << 6;
900 uint8_t stat;
901
902 /*
903 * Read Page
904 */
905 ubi32_nand_spi_er_send_cmd_addr(0x13, row);
906
907 /*
908 * Wait
909 */
910 stat = ubi32_nand_spi_er_busywait();
911 if (stat & UBI32_NAND_SPI_ER_STATUS_OIP) {
912 DEBUG(MTD_DEBUG_LEVEL1, "%s: chip is busy or nonresponsive stat=%02x\n", chip->name, stat);
913
914 /*
915 * Chip is stuck?
916 */
917 return -EIO;
918 }
919
920 /*
921 * Check factory bad block mark
922 */
923 ubi32_nand_spi_er_send_rd_addr(0x03, 0x080000);
924
925 if ((io->status1 >> 24) != 0xFF) {
926 chip->nbb++;
927 __set_bit(j, chip->bbt);
928 continue;
929 }
930
931 ubi32_nand_spi_er_send_rd_addr(0x03, 0x080000 | (UBI32_NAND_SPI_ER_BAD_BLOCK_MARK_OFFSET << 8));
932 if (io->status1 == 0xdeadbeef) {
933 chip->nbb++;
934 __set_bit(j, chip->bbt);
935 }
936 }
937
938 #if defined(CONFIG_MTD_DEBUG) && (MTD_DEBUG_LEVEL3 <= CONFIG_MTD_DEBUG_VERBOSE)
939 printk("%s: Bad Block Table:", chip->name);
940 for (j = 0; j < chip->device->blocks; j++) {
941 if ((j % 64) == 0) {
942 printk("\n%s: block %03x: ", chip->name, j);
943 }
944 printk("%c", test_bit(j, chip->bbt) ? 'X' : '.');
945 }
946 printk("\n%s: Bad Block Numbers: ", chip->name);
947 for (j = 0; j < chip->device->blocks; j++) {
948 if (test_bit(j, chip->bbt)) {
949 printk("%x ", j);
950 }
951 }
952 printk("\n");
953 #endif
954
955 return 0;
956 }
957
958 #ifndef MODULE
959 /*
960 * Called at boot time:
961 *
962 * ubi32_nand_spi_er=read_only
963 * if read_only specified then do not unlock device
964 */
965 static int __init ubi32_nand_spi_er_setup(char *str)
966 {
967 if (str && (strncasecmp(str, "read_only", 9) == 0)) {
968 read_only = 1;
969 }
970 return 0;
971 }
972
973 __setup("ubi32_nand_spi_er=", ubi32_nand_spi_er_setup);
974 #endif
975
976 /*
977 * ubi32_nand_spi_er_probe
978 * Detect and initialize ubi32_nand_spi_er device.
979 */
980 static int __devinit ubi32_nand_spi_er_probe(struct platform_device *pdev)
981 {
982 uint32_t i;
983 uint32_t id;
984 int res;
985 size_t bbt_bytes;
986 struct ubi32_nand_spi_er *chip;
987 const struct ubi32_nand_spi_er_device *device;
988 struct ubicom32_io_port *io = (struct ubicom32_io_port *)FLASH_PORT;
989
990 /*
991 * Reset
992 */
993 for (i = 0; i < 2; i++) {
994 io->ctl1 &= ~IO_XFL_CTL1_MASK;
995 io->ctl1 |= IO_XFL_CTL1_FC_INST(FLASH_FC_INST_CMD);
996 io->ctl2 = IO_XFL_CTL2_FC_CMD(0xFF);
997 FLASH_COMMAND_EXEC(io);
998 udelay(250);
999 }
1000 udelay(1000);
1001
1002 /*
1003 * Read out ID
1004 */
1005 io->ctl1 &= ~IO_XFL_CTL1_MASK;
1006 io->ctl1 |= IO_XFL_CTL1_FC_INST(FLASH_FC_INST_RD) | IO_XFL_CTL1_FC_DATA(2) |
1007 IO_XFL_CTL1_FC_ADDR;
1008 io->ctl2 = IO_XFL_CTL2_FC_CMD(0x9F);
1009 FLASH_COMMAND_EXEC(io);
1010
1011 id = io->status1 >> 16;
1012 device = ubi32_nand_spi_er_devices;
1013 for (i = 0; i < ARRAY_SIZE(ubi32_nand_spi_er_devices); i++) {
1014 if (device->id == id) {
1015 break;
1016 }
1017 device++;
1018 }
1019 if (i == ARRAY_SIZE(ubi32_nand_spi_er_devices)) {
1020 return -ENODEV;
1021 }
1022
1023 /*
1024 * Initialize our chip structure
1025 */
1026 bbt_bytes = DIV_ROUND_UP(device->blocks, BITS_PER_BYTE);
1027 chip = kzalloc(sizeof(struct ubi32_nand_spi_er) + bbt_bytes, GFP_KERNEL);
1028 if (!chip) {
1029 return -ENOMEM;
1030 }
1031 snprintf(chip->name, sizeof(chip->name), "%s", device->name);
1032
1033 chip->device = device;
1034 chip->last_row = UBI32_NAND_SPI_ER_LAST_ROW_INVALID;
1035
1036 mutex_init(&chip->lock);
1037
1038 chip->mtd.type = MTD_NANDFLASH;
1039 chip->mtd.flags = MTD_WRITEABLE;
1040
1041 /*
1042 * #blocks * block size * n blocks
1043 */
1044 chip->mtd.size = device->blocks * device->pages_per_block * device->page_size;
1045 chip->mtd.erasesize = device->erase_size;
1046
1047 /*
1048 * 1 page, optionally we can support partial write (512)
1049 */
1050 chip->mtd.writesize = device->write_size;
1051 chip->mtd.name = device->name;
1052 chip->mtd.erase = ubi32_nand_spi_er_erase;
1053 chip->mtd.read = ubi32_nand_spi_er_read;
1054 chip->mtd.write = ubi32_nand_spi_er_write;
1055 chip->mtd.block_isbad = ubi32_nand_spi_er_isbad;
1056 chip->mtd.block_markbad = ubi32_nand_spi_er_markbad;
1057 chip->mtd.priv = chip;
1058
1059 /*
1060 * Cache the bad block table
1061 */
1062 res = ubi32_nand_spi_er_read_bbt(chip);
1063 if (res) {
1064 kfree(chip);
1065 return res;
1066 }
1067
1068 /*
1069 * Un/lock the chip
1070 */
1071 io->ctl0 |= IO_XFL_CTL0_MCB_LOCK;
1072 io->ctl1 &= ~IO_XFL_CTL1_MASK;
1073 io->ctl1 |= IO_XFL_CTL1_FC_INST(FLASH_FC_INST_WR) | IO_XFL_CTL1_FC_DATA(2);
1074 io->ctl2 = IO_XFL_CTL2_FC_CMD(0x1F);
1075
1076 if (read_only) {
1077 i = 0xa0380000;
1078 } else {
1079 i = 0xa0000000;
1080 }
1081 asm volatile (
1082 " bset "D(IO_INT_SET)"(%[port]), #0, #%%bit("D(IO_PORTX_INT_FIFO_TX_RESET)") \n\t"
1083 " pipe_flush 0 \n\t"
1084
1085 /*
1086 * Move the data into the FIFO
1087 */
1088 " move.4 "D(IO_TX_FIFO)"(%[port]), %[word1] \n\t"
1089
1090 /*
1091 * Kick off the flash command
1092 */
1093 " bset "D(IO_INT_CLR)"(%[port]), #0, #%%bit("D(IO_XFL_INT_DONE)") \n\t"
1094 " jmpt.t .+4 \n\t"
1095 " bset "D(IO_INT_SET)"(%[port]), #0, #%%bit("D(IO_XFL_INT_START)") \n\t"
1096
1097 /*
1098 * Wait for the transaction to finish
1099 */
1100 " btst "D(IO_INT_STATUS)"(%[port]), #%%bit("D(IO_XFL_INT_DONE)") \n\t"
1101 " jmpeq.f .-4 \n\t"
1102
1103 :
1104 : [word1] "d" (i),
1105 [port] "a" (FLASH_PORT)
1106 : "cc"
1107 );
1108 io->ctl0 &= ~IO_XFL_CTL0_MCB_LOCK;
1109
1110 dev_set_drvdata(&pdev->dev, chip);
1111
1112 printk(KERN_INFO "%s: added device size: %u KBytes %lu bad blocks %s\n", chip->mtd.name, DIV_ROUND_UP(chip->mtd.size, 1024), chip->nbb, read_only ? "[read only]" : "");
1113 return add_mtd_device(&chip->mtd);
1114 }
1115
1116 /*
1117 * ubi32_nand_spi_er_remove
1118 */
1119 static int __devexit ubi32_nand_spi_er_remove(struct platform_device *pdev)
1120 {
1121 struct ubi32_nand_spi_er *chip = dev_get_drvdata(&pdev->dev);
1122 int status;
1123
1124 DEBUG(MTD_DEBUG_LEVEL1, "%s: remove\n", chip->name);
1125
1126 status = del_mtd_device(&chip->mtd);
1127 if (status == 0) {
1128 kfree(chip);
1129 }
1130
1131 dev_set_drvdata(&pdev->dev, NULL);
1132 return status;
1133 }
1134
1135 static struct platform_device *ubi32_nand_spi_er_device;
1136
1137 static struct platform_driver ubi32_nand_spi_er_driver = {
1138 .driver = {
1139 .name = DRIVER_NAME,
1140 .owner = THIS_MODULE,
1141 },
1142
1143 .probe = ubi32_nand_spi_er_probe,
1144 .remove = ubi32_nand_spi_er_remove,
1145 };
1146
1147 /*
1148 * ubi32_nand_spi_er_init
1149 */
1150 static int __init ubi32_nand_spi_er_init(void)
1151 {
1152 int ret;
1153
1154 ret = platform_driver_register(&ubi32_nand_spi_er_driver);
1155
1156 if (ret) {
1157 return ret;
1158 }
1159
1160 ubi32_nand_spi_er_device = platform_device_alloc(DRIVER_NAME, 0);
1161 if (!ubi32_nand_spi_er_device) {
1162 return -ENOMEM;
1163 }
1164
1165 ret = platform_device_add(ubi32_nand_spi_er_device);
1166 if (ret) {
1167 platform_device_put(ubi32_nand_spi_er_device);
1168 platform_driver_unregister(&ubi32_nand_spi_er_driver);
1169 }
1170
1171 return ret;
1172 }
1173 module_init(ubi32_nand_spi_er_init);
1174
1175 /*
1176 * ubi32_nand_spi_er_exit
1177 */
1178 static void __exit ubi32_nand_spi_er_exit(void)
1179 {
1180 platform_device_unregister(ubi32_nand_spi_er_device);
1181 platform_driver_unregister(&ubi32_nand_spi_er_driver);
1182 }
1183 module_exit(ubi32_nand_spi_er_exit);
1184
1185
1186 MODULE_LICENSE("GPL");
1187 MODULE_AUTHOR("Patrick Tjin");
1188 MODULE_DESCRIPTION("MTD ubi32_nand_spi_er driver for ubicom32 SPI flash controller.");
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