target/linux/xburst/patches-2.6.32/001-core.patch

   1 From 42789dfb077bb7b640ee19d0e3f7808dc5318adf Mon Sep 17 00:00:00 2001
   2 From: Lars-Peter Clausen <lars@metafoo.de>
   3 Date: Mon, 11 Jan 2010 04:29:35 +0100
   4 Subject: [PATCH] /opt/Projects/openwrt/target/linux/xburst/patches-2.6.31/001-core.patch
   5
   6 ---
   7  arch/mips/Kconfig                        |   29 ++++
   8  arch/mips/Makefile                       |   18 +++
   9  arch/mips/boot/Makefile                  |   23 +++-
  10  arch/mips/include/asm/bootinfo.h         |    6 +
  11  arch/mips/include/asm/cpu.h              |   13 ++-
  12  arch/mips/include/asm/mach-generic/irq.h |    2 +-
  13  arch/mips/include/asm/r4kcache.h         |  231 ++++++++++++++++++++++++++++++
  14  arch/mips/include/asm/suspend.h          |    3 +
  15  arch/mips/kernel/cpu-probe.c             |   21 +++
  16  arch/mips/mm/c-r4k.c                     |   30 ++++
  17  arch/mips/mm/cache.c                     |    2 +
  18  arch/mips/mm/tlbex.c                     |    5 +
  19  12 files changed, 379 insertions(+), 4 deletions(-)
  20
  21 --- a/arch/mips/Kconfig
  22 +++ b/arch/mips/Kconfig
  23 @@ -174,6 +174,9 @@ config MACH_JAZZ
  24          Members include the Acer PICA, MIPS Magnum 4000, MIPS Millennium and
  25          Olivetti M700-10 workstations.
  26
  27 +config MACH_JZ
  28 +       bool "Ingenic JZ4720/JZ4740 based machines"
  29 +
  30  config LASAT
  31         bool "LASAT Networks platforms"
  32         select CEVT_R4K
  33 --- a/arch/mips/Makefile
  34 +++ b/arch/mips/Makefile
  35 @@ -184,6 +184,14 @@ cflags-$(CONFIG_AR7)               += -I$(srctree)/ar
  36  load-$(CONFIG_AR7)             += 0xffffffff94100000
  37
  38  #
  39 +# Commond Ingenic JZ4740 series
  40 +#
  41 +
  42 +core-$(CONFIG_SOC_JZ4740)      += arch/mips/jz4740/
  43 +cflags-$(CONFIG_SOC_JZ4740)    += -I$(srctree)/arch/mips/include/asm/mach-jz4740
  44 +load-$(CONFIG_SOC_JZ4740)      += 0xffffffff80010000
  45 +
  46 +#
  47  # Acer PICA 61, Mips Magnum 4000 and Olivetti M700.
  48  #
  49  core-$(CONFIG_MACH_JAZZ)       += arch/mips/jazz/
  50 @@ -705,6 +713,12 @@ makeboot =$(Q)$(MAKE) $(build)=arch/mips
  51
  52  all:   $(all-y)
  53
  54 +uImage: $(vmlinux-32)
  55 +       +@$(call makeboot,$@)
  56 +
  57 +zImage: $(vmlinux-32)
  58 +       +@$(call makeboot,$@)
  59 +
  60  vmlinux.bin: $(vmlinux-32)
  61         +@$(call makeboot,$@)
  62
  63 @@ -734,6 +748,7 @@ install:
  64
  65  archclean:
  66         @$(MAKE) $(clean)=arch/mips/boot
  67 +       @$(MAKE) $(clean)=arch/mips/boot/compressed
  68         @$(MAKE) $(clean)=arch/mips/lasat
  69
  70  define archhelp
  71 @@ -741,6 +756,9 @@ define archhelp
  72         echo '  vmlinux.ecoff        - ECOFF boot image'
  73         echo '  vmlinux.bin          - Raw binary boot image'
  74         echo '  vmlinux.srec         - SREC boot image'
  75 +       echo  '  uImage - u-boot format image (arch/$(ARCH)/boot/uImage)'
  76 +       echo  '  zImage - Compressed binary image (arch/$(ARCH)/boot/compressed/zImage)'
  77 +       echo  '  vmlinux.bin    - Uncompressed binary image (arch/$(ARCH)/boot/vmlinux.bin)'
  78         echo
  79         echo '  These will be default as apropriate for a configured platform.'
  80  endef
  81 --- a/arch/mips/boot/Makefile
  82 +++ b/arch/mips/boot/Makefile
  83 @@ -7,6 +7,9 @@
  84  # Copyright (C) 2004  Maciej W. Rozycki
  85  #
  86
  87 +# This one must match the LOADADDR in arch/mips/Makefile!
  88 +LOADADDR=0x80010000
  89 +
  90  #
  91  # Some DECstations need all possible sections of an ECOFF executable
  92  #
  93 @@ -25,7 +28,7 @@ strip-flags   = $(addprefix --remove-secti
  94
  95  VMLINUX = vmlinux
  96
  97 -all: vmlinux.ecoff vmlinux.srec addinitrd
  98 +all: vmlinux.ecoff vmlinux.srec addinitrd uImage zImage
  99
 100  vmlinux.ecoff: $(obj)/elf2ecoff $(VMLINUX)
 101         $(obj)/elf2ecoff $(VMLINUX) vmlinux.ecoff $(E2EFLAGS)
 102 @@ -42,8 +45,24 @@ vmlinux.srec: $(VMLINUX)
 103  $(obj)/addinitrd: $(obj)/addinitrd.c
 104         $(HOSTCC) -o $@ $^
 105
 106 +uImage: $(VMLINUX) vmlinux.bin
 107 +       rm -f $(obj)/vmlinux.bin.gz
 108 +       gzip -9 $(obj)/vmlinux.bin
 109 +       mkimage -A mips -O linux -T kernel -C gzip \
 110 +               -a $(LOADADDR) -e $(shell sh ./$(obj)/tools/entry $(NM) $(VMLINUX) ) \
 111 +               -n 'Linux-$(KERNELRELEASE)' \
 112 +               -d $(obj)/vmlinux.bin.gz $(obj)/uImage
 113 +       @echo '  Kernel: arch/mips/boot/$@ is ready'
 114 +
 115 +zImage:
 116 +       $(Q)$(MAKE) $(build)=$(obj)/compressed loadaddr=$(LOADADDR) $@
 117 +       @echo '  Kernel: arch/mips/boot/compressed/$@ is ready'
 118 +
 119  clean-files += addinitrd \
 120                elf2ecoff \
 121                vmlinux.bin \
 122                vmlinux.ecoff \
 123 -              vmlinux.srec
 124 +              vmlinux.srec \
 125 +              vmlinux.bin.gz \
 126 +              uImage \
 127 +              zImage
 128 --- a/arch/mips/include/asm/bootinfo.h
 129 +++ b/arch/mips/include/asm/bootinfo.h
 130 @@ -69,6 +69,12 @@
 131  #define MACH_DEXXON_GDIUM2F10  5
 132  #define MACH_LOONGSON_END      6
 133
 134 +/*
 135 + * Valid machtype for group INGENIC
 136 + */
 137 +#define  MACH_INGENIC_JZ4730   0       /* JZ4730 SOC           */
 138 +#define  MACH_INGENIC_JZ4740   1       /* JZ4740 SOC           */
 139 +
 140  #define CL_SIZE                        COMMAND_LINE_SIZE
 141
 142  extern char *system_type;
 143 --- a/arch/mips/include/asm/cpu.h
 144 +++ b/arch/mips/include/asm/cpu.h
 145 @@ -34,7 +34,7 @@
 146  #define PRID_COMP_LSI          0x080000
 147  #define PRID_COMP_LEXRA                0x0b0000
 148  #define PRID_COMP_CAVIUM       0x0d0000
 149 -
 150 +#define PRID_COMP_INGENIC      0xd00000
 151
 152  /*
 153   * Assigned values for the product ID register.  In order to detect a
 154 @@ -133,6 +133,12 @@
 155  #define PRID_IMP_CAVIUM_CN52XX 0x0700
 156
 157  /*
 158 + * These are the PRID's for when 23:16 == PRID_COMP_INGENIC
 159 + */
 160 +
 161 +#define PRID_IMP_JZRISC        0x0200
 162 +
 163 +/*
 164   * Definitions for 7:0 on legacy processors
 165   */
 166
 167 @@ -224,6 +230,11 @@ enum cpu_type_enum {
 168         CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
 169         CPU_CAVIUM_OCTEON,
 170
 171 +       /*
 172 +        * Ingenic class processors
 173 +        */
 174 +       CPU_JZRISC, CPU_XBURST,
 175 +
 176         CPU_LAST
 177  };
 178
 179 --- a/arch/mips/include/asm/r4kcache.h
 180 +++ b/arch/mips/include/asm/r4kcache.h
 181 @@ -17,6 +17,58 @@
 182  #include <asm/cpu-features.h>
 183  #include <asm/mipsmtregs.h>
 184
 185 +#ifdef CONFIG_JZRISC
 186 +
 187 +#define K0_TO_K1()                             \
 188 +do {                                           \
 189 +       unsigned long __k0_addr;                \
 190 +                                               \
 191 +       __asm__ __volatile__(                   \
 192 +       "la %0, 1f\n\t"                         \
 193 +       "or     %0, %0, %1\n\t"                 \
 194 +       "jr     %0\n\t"                         \
 195 +       "nop\n\t"                               \
 196 +       "1: nop\n"                              \
 197 +       : "=&r"(__k0_addr)                      \
 198 +       : "r" (0x20000000) );                   \
 199 +} while(0)
 200 +
 201 +#define K1_TO_K0()                             \
 202 +do {                                           \
 203 +       unsigned long __k0_addr;                \
 204 +       __asm__ __volatile__(                   \
 205 +       "nop;nop;nop;nop;nop;nop;nop\n\t"       \
 206 +       "la %0, 1f\n\t"                         \
 207 +       "jr     %0\n\t"                         \
 208 +       "nop\n\t"                               \
 209 +       "1:     nop\n"                          \
 210 +       : "=&r" (__k0_addr));                   \
 211 +} while (0)
 212 +
 213 +#define INVALIDATE_BTB()                       \
 214 +do {                                           \
 215 +       unsigned long tmp;                      \
 216 +       __asm__ __volatile__(                   \
 217 +       ".set mips32\n\t"                       \
 218 +       "mfc0 %0, $16, 7\n\t"                   \
 219 +       "nop\n\t"                               \
 220 +       "ori %0, 2\n\t"                         \
 221 +       "mtc0 %0, $16, 7\n\t"                   \
 222 +       "nop\n\t"                               \
 223 +       : "=&r" (tmp));                         \
 224 +} while (0)
 225 +
 226 +#define SYNC_WB() __asm__ __volatile__ ("sync")
 227 +
 228 +#else /* CONFIG_JZRISC */
 229 +
 230 +#define K0_TO_K1() do { } while (0)
 231 +#define K1_TO_K0() do { } while (0)
 232 +#define INVALIDATE_BTB() do { } while (0)
 233 +#define SYNC_WB() do { } while (0)
 234 +
 235 +#endif /* CONFIG_JZRISC */
 236 +
 237  /*
 238   * This macro return a properly sign-extended address suitable as base address
 239   * for indexed cache operations.  Two issues here:
 240 @@ -144,6 +196,7 @@ static inline void flush_icache_line_ind
 241  {
 242         __iflush_prologue
 243         cache_op(Index_Invalidate_I, addr);
 244 +       INVALIDATE_BTB();
 245         __iflush_epilogue
 246  }
 247
 248 @@ -151,6 +204,7 @@ static inline void flush_dcache_line_ind
 249  {
 250         __dflush_prologue
 251         cache_op(Index_Writeback_Inv_D, addr);
 252 +       SYNC_WB();
 253         __dflush_epilogue
 254  }
 255
 256 @@ -163,6 +217,7 @@ static inline void flush_icache_line(uns
 257  {
 258         __iflush_prologue
 259         cache_op(Hit_Invalidate_I, addr);
 260 +       INVALIDATE_BTB();
 261         __iflush_epilogue
 262  }
 263
 264 @@ -170,6 +225,7 @@ static inline void flush_dcache_line(uns
 265  {
 266         __dflush_prologue
 267         cache_op(Hit_Writeback_Inv_D, addr);
 268 +       SYNC_WB();
 269         __dflush_epilogue
 270  }
 271
 272 @@ -177,6 +233,7 @@ static inline void invalidate_dcache_lin
 273  {
 274         __dflush_prologue
 275         cache_op(Hit_Invalidate_D, addr);
 276 +       SYNC_WB();
 277         __dflush_epilogue
 278  }
 279
 280 @@ -209,6 +266,7 @@ static inline void flush_scache_line(uns
 281  static inline void protected_flush_icache_line(unsigned long addr)
 282  {
 283         protected_cache_op(Hit_Invalidate_I, addr);
 284 +       INVALIDATE_BTB();
 285  }
 286
 287  /*
 288 @@ -220,6 +278,7 @@ static inline void protected_flush_icach
 289  static inline void protected_writeback_dcache_line(unsigned long addr)
 290  {
 291         protected_cache_op(Hit_Writeback_Inv_D, addr);
 292 +       SYNC_WB();
 293  }
 294
 295  static inline void protected_writeback_scache_line(unsigned long addr)
 296 @@ -396,8 +455,10 @@ static inline void blast_##pfx##cache##l
 297  __BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16)
 298  __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16)
 299  __BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16)
 300 +#ifndef CONFIG_JZRISC
 301  __BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32)
 302  __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32)
 303 +#endif
 304  __BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32)
 305  __BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64)
 306  __BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
 307 @@ -405,12 +466,122 @@ __BUILD_BLAST_CACHE(s, scache, Index_Wri
 308  __BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128)
 309
 310  __BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16)
 311 +#ifndef CONFIG_JZRISC
 312  __BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32)
 313 +#endif
 314  __BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16)
 315  __BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32)
 316  __BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64)
 317  __BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128)
 318
 319 +#ifdef CONFIG_JZRISC
 320 +
 321 +static inline void blast_dcache32(void)
 322 +{
 323 +       unsigned long start = INDEX_BASE;
 324 +       unsigned long end = start + current_cpu_data.dcache.waysize;
 325 +       unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
 326 +       unsigned long ws_end = current_cpu_data.dcache.ways <<
 327 +                              current_cpu_data.dcache.waybit;
 328 +       unsigned long ws, addr;
 329 +
 330 +       for (ws = 0; ws < ws_end; ws += ws_inc)
 331 +               for (addr = start; addr < end; addr += 0x400)
 332 +                       cache32_unroll32(addr|ws,Index_Writeback_Inv_D);
 333 +
 334 +       SYNC_WB();
 335 +}
 336 +
 337 +static inline void blast_dcache32_page(unsigned long page)
 338 +{
 339 +       unsigned long start = page;
 340 +       unsigned long end = page + PAGE_SIZE;
 341 +
 342 +       do {
 343 +               cache32_unroll32(start,Hit_Writeback_Inv_D);
 344 +               start += 0x400;
 345 +       } while (start < end);
 346 +
 347 +       SYNC_WB();
 348 +}
 349 +
 350 +static inline void blast_dcache32_page_indexed(unsigned long page)
 351 +{
 352 +       unsigned long indexmask = current_cpu_data.dcache.waysize - 1;
 353 +       unsigned long start = INDEX_BASE + (page & indexmask);
 354 +       unsigned long end = start + PAGE_SIZE;
 355 +       unsigned long ws_inc = 1UL << current_cpu_data.dcache.waybit;
 356 +       unsigned long ws_end = current_cpu_data.dcache.ways <<
 357 +                              current_cpu_data.dcache.waybit;
 358 +       unsigned long ws, addr;
 359 +
 360 +       for (ws = 0; ws < ws_end; ws += ws_inc)
 361 +               for (addr = start; addr < end; addr += 0x400)
 362 +                       cache32_unroll32(addr|ws,Index_Writeback_Inv_D);
 363 +
 364 +       SYNC_WB();
 365 +}
 366 +
 367 +static inline void blast_icache32(void)
 368 +{
 369 +       unsigned long start = INDEX_BASE;
 370 +       unsigned long end = start + current_cpu_data.icache.waysize;
 371 +       unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
 372 +       unsigned long ws_end = current_cpu_data.icache.ways <<
 373 +                              current_cpu_data.icache.waybit;
 374 +       unsigned long ws, addr;
 375 +
 376 +       K0_TO_K1();
 377 +
 378 +       for (ws = 0; ws < ws_end; ws += ws_inc)
 379 +               for (addr = start; addr < end; addr += 0x400)
 380 +                       cache32_unroll32(addr|ws,Index_Invalidate_I);
 381 +
 382 +       INVALIDATE_BTB();
 383 +
 384 +       K1_TO_K0();
 385 +}
 386 +
 387 +static inline void blast_icache32_page(unsigned long page)
 388 +{
 389 +       unsigned long start = page;
 390 +       unsigned long end = page + PAGE_SIZE;
 391 +
 392 +       K0_TO_K1();
 393 +
 394 +       do {
 395 +               cache32_unroll32(start,Hit_Invalidate_I);
 396 +               start += 0x400;
 397 +       } while (start < end);
 398 +
 399 +       INVALIDATE_BTB();
 400 +
 401 +       K1_TO_K0();
 402 +}
 403 +
 404 +static inline void blast_icache32_page_indexed(unsigned long page)
 405 +{
 406 +       unsigned long indexmask = current_cpu_data.icache.waysize - 1;
 407 +       unsigned long start = INDEX_BASE + (page & indexmask);
 408 +       unsigned long end = start + PAGE_SIZE;
 409 +       unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
 410 +       unsigned long ws_end = current_cpu_data.icache.ways <<
 411 +                              current_cpu_data.icache.waybit;
 412 +       unsigned long ws, addr;
 413 +
 414 +       K0_TO_K1();
 415 +
 416 +       for (ws = 0; ws < ws_end; ws += ws_inc)
 417 +               for (addr = start; addr < end; addr += 0x400)
 418 +                       cache32_unroll32(addr|ws,Index_Invalidate_I);
 419 +
 420 +       INVALIDATE_BTB();
 421 +
 422 +       K1_TO_K0();
 423 +}
 424 +
 425 +#endif /* CONFIG_JZRISC */
 426 +
 427  /* build blast_xxx_range, protected_blast_xxx_range */
 428  #define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot) \
 429  static inline void prot##blast_##pfx##cache##_range(unsigned long start, \
 430 @@ -432,13 +603,73 @@ static inline void prot##blast_##pfx##ca
 431         __##pfx##flush_epilogue                                         \
 432  }
 433
 434 +#ifndef CONFIG_JZRISC
 435  __BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_)
 436 +#endif
 437  __BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_)
 438 +#ifndef CONFIG_JZRISC
 439  __BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_)
 440  __BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, )
 441 +#endif
 442  __BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, )
 443  /* blast_inv_dcache_range */
 444  __BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, )
 445  __BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, )
 446
 447 +#ifdef CONFIG_JZRISC
 448 +
 449 +static inline void protected_blast_dcache_range(unsigned long start,
 450 +                                               unsigned long end)
 451 +{
 452 +       unsigned long lsize = cpu_dcache_line_size();
 453 +       unsigned long addr = start & ~(lsize - 1);
 454 +       unsigned long aend = (end - 1) & ~(lsize - 1);
 455 +
 456 +       while (1) {
 457 +               protected_cache_op(Hit_Writeback_Inv_D, addr);
 458 +               if (addr == aend)
 459 +                       break;
 460 +               addr += lsize;
 461 +       }
 462 +       SYNC_WB();
 463 +}
 464 +
 465 +static inline void protected_blast_icache_range(unsigned long start,
 466 +                                               unsigned long end)
 467 +{
 468 +       unsigned long lsize = cpu_icache_line_size();
 469 +       unsigned long addr = start & ~(lsize - 1);
 470 +       unsigned long aend = (end - 1) & ~(lsize - 1);
 471 +
 472 +       K0_TO_K1();
 473 +
 474 +       while (1) {
 475 +               protected_cache_op(Hit_Invalidate_I, addr);
 476 +               if (addr == aend)
 477 +                       break;
 478 +               addr += lsize;
 479 +       }
 480 +       INVALIDATE_BTB();
 481 +
 482 +       K1_TO_K0();
 483 +}
 484 +
 485 +static inline void blast_dcache_range(unsigned long start,
 486 +                                     unsigned long end)
 487 +{
 488 +       unsigned long lsize = cpu_dcache_line_size();
 489 +       unsigned long addr = start & ~(lsize - 1);
 490 +       unsigned long aend = (end - 1) & ~(lsize - 1);
 491 +
 492 +       while (1) {
 493 +               cache_op(Hit_Writeback_Inv_D, addr);
 494 +               if (addr == aend)
 495 +                       break;
 496 +               addr += lsize;
 497 +       }
 498 +       SYNC_WB();
 499 +}
 500 +
 501 +#endif /* CONFIG_JZRISC */
 502 +
 503  #endif /* _ASM_R4KCACHE_H */
 504 --- a/arch/mips/kernel/cpu-probe.c
 505 +++ b/arch/mips/kernel/cpu-probe.c
 506 @@ -160,6 +160,7 @@ void __init check_wait(void)
 507         case CPU_BCM6348:
 508         case CPU_BCM6358:
 509         case CPU_CAVIUM_OCTEON:
 510 +       case CPU_JZRISC:
 511                 cpu_wait = r4k_wait;
 512                 break;
 513
 514 @@ -902,6 +903,21 @@ static inline void cpu_probe_cavium(stru
 515         }
 516  }
 517
 518 +static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
 519 +{
 520 +       decode_configs(c);
 521 +       c->options &= ~MIPS_CPU_COUNTER; /* JZRISC does not implement the CP0 counter. */
 522 +       switch (c->processor_id & 0xff00) {
 523 +       case PRID_IMP_JZRISC:
 524 +               c->cputype = CPU_JZRISC;
 525 +               __cpu_name[cpu] = "Ingenic JZRISC";
 526 +               break;
 527 +       default:
 528 +               panic("Unknown Ingenic Processor ID!");
 529 +               break;
 530 +       }
 531 +}
 532 +
 533  const char *__cpu_name[NR_CPUS];
 534
 535  __cpuinit void cpu_probe(void)
 536 @@ -939,6 +957,9 @@ __cpuinit void cpu_probe(void)
 537         case PRID_COMP_CAVIUM:
 538                 cpu_probe_cavium(c, cpu);
 539                 break;
 540 +       case PRID_COMP_INGENIC:
 541 +               cpu_probe_ingenic(c, cpu);
 542 +               break;
 543         }
 544
 545         BUG_ON(!__cpu_name[cpu]);
 546 --- a/arch/mips/mm/tlbex.c
 547 +++ b/arch/mips/mm/tlbex.c
 548 @@ -389,6 +389,11 @@ static void __cpuinit build_tlb_write_en
 549                 tlbw(p);
 550                 break;
 551
 552 +       case CPU_JZRISC:
 553 +               tlbw(p);
 554 +               uasm_i_nop(p);
 555 +               break;
 556 +
 557         default:
 558                 panic("No TLB refill handler yet (CPU type: %d)",
 559                       current_cpu_data.cputype);