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xburst: Add 3.10 support
[openwrt/staging/yousong.git] / target / linux / xburst / patches-3.10 / 008-Add-jz4740-udc-driver.patch
1 From b3e08e29f6f32dfb400374dc96d0a2f61e6adceb Mon Sep 17 00:00:00 2001
2 From: Lars-Peter Clausen <lars@metafoo.de>
3 Date: Sat, 24 Apr 2010 12:18:46 +0200
4 Subject: [PATCH 08/16] Add jz4740 udc driver
5
6 Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
7 ---
8 drivers/usb/gadget/Kconfig | 8 +
9 drivers/usb/gadget/Makefile | 1 +
10 drivers/usb/gadget/gadget_chips.h | 1 +
11 drivers/usb/gadget/jz4740_udc.c | 2155 +++++++++++++++++++++++++++++++++++++
12 drivers/usb/gadget/jz4740_udc.h | 101 ++
13 5 files changed, 2266 insertions(+)
14 create mode 100644 drivers/usb/gadget/jz4740_udc.c
15 create mode 100644 drivers/usb/gadget/jz4740_udc.h
16
17 diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
18 index f41aa0d..c96b7ef 100644
19 --- a/drivers/usb/gadget/Kconfig
20 +++ b/drivers/usb/gadget/Kconfig
21 @@ -192,6 +192,14 @@ config USB_FUSB300
22 help
23 Faraday usb device controller FUSB300 driver
24
25 +config USB_JZ4740
26 + tristate "JZ4740 UDC"
27 + depends on MACH_JZ4740
28 + select USB_GADGET_DUALSPEED
29 + help
30 + Select this to support the Ingenic JZ4740 processor
31 + high speed USB device controller.
32 +
33 config USB_OMAP
34 tristate "OMAP USB Device Controller"
35 depends on ARCH_OMAP1
36 diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile
37 index 6afd166..f18db69 100644
38 --- a/drivers/usb/gadget/Makefile
39 +++ b/drivers/usb/gadget/Makefile
40 @@ -34,6 +34,7 @@ obj-$(CONFIG_USB_MV_UDC) += mv_udc.o
41 mv_udc-y := mv_udc_core.o
42 obj-$(CONFIG_USB_FUSB300) += fusb300_udc.o
43 obj-$(CONFIG_USB_MV_U3D) += mv_u3d_core.o
44 +obj-$(CONFIG_USB_JZ4740) += jz4740_udc.o
45
46 # USB Functions
47 usb_f_acm-y := f_acm.o
48 diff --git a/drivers/usb/gadget/gadget_chips.h b/drivers/usb/gadget/gadget_chips.h
49 index bcd04bc..a3b069f 100644
50 --- a/drivers/usb/gadget/gadget_chips.h
51 +++ b/drivers/usb/gadget/gadget_chips.h
52 @@ -29,6 +29,7 @@
53 */
54 #define gadget_is_at91(g) (!strcmp("at91_udc", (g)->name))
55 #define gadget_is_goku(g) (!strcmp("goku_udc", (g)->name))
56 +#define gadget_is_jz4740(g) (!strcmp("ingenic_hsusb", (g)->name))
57 #define gadget_is_musbhdrc(g) (!strcmp("musb-hdrc", (g)->name))
58 #define gadget_is_net2280(g) (!strcmp("net2280", (g)->name))
59 #define gadget_is_pxa(g) (!strcmp("pxa25x_udc", (g)->name))
60 diff --git a/drivers/usb/gadget/jz4740_udc.c b/drivers/usb/gadget/jz4740_udc.c
61 new file mode 100644
62 index 0000000..72e9a6c
63 --- /dev/null
64 +++ b/drivers/usb/gadget/jz4740_udc.c
65 @@ -0,0 +1,2155 @@
66 +/*
67 + * linux/drivers/usb/gadget/jz4740_udc.c
68 + *
69 + * Ingenic JZ4740 on-chip high speed USB device controller
70 + *
71 + * Copyright (C) 2006 - 2008 Ingenic Semiconductor Inc.
72 + * Author: <jlwei@ingenic.cn>
73 + *
74 + * This program is free software; you can redistribute it and/or modify
75 + * it under the terms of the GNU General Public License as published by
76 + * the Free Software Foundation; either version 2 of the License, or
77 + * (at your option) any later version.
78 + */
79 +
80 +/*
81 + * This device has ep0, two bulk-in/interrupt-in endpoints, and one bulk-out endpoint.
82 + *
83 + * - Endpoint numbering is fixed: ep0, ep1in-int, ep2in-bulk, ep1out-bulk.
84 + * - DMA works with bulk-in (channel 1) and bulk-out (channel 2) endpoints.
85 + */
86 +
87 +#include <linux/kernel.h>
88 +#include <linux/module.h>
89 +#include <linux/platform_device.h>
90 +#include <linux/delay.h>
91 +#include <linux/ioport.h>
92 +#include <linux/slab.h>
93 +#include <linux/errno.h>
94 +#include <linux/init.h>
95 +#include <linux/list.h>
96 +#include <linux/interrupt.h>
97 +#include <linux/proc_fs.h>
98 +#include <linux/usb.h>
99 +#include <linux/usb/gadget.h>
100 +#include <linux/clk.h>
101 +
102 +#include <asm/byteorder.h>
103 +#include <asm/io.h>
104 +#include <asm/irq.h>
105 +#include <asm/mach-jz4740/clock.h>
106 +
107 +#include "jz4740_udc.h"
108 +
109 +#define JZ_REG_UDC_FADDR 0x00 /* Function Address 8-bit */
110 +#define JZ_REG_UDC_POWER 0x01 /* Power Management 8-bit */
111 +#define JZ_REG_UDC_INTRIN 0x02 /* Interrupt IN 16-bit */
112 +#define JZ_REG_UDC_INTROUT 0x04 /* Interrupt OUT 16-bit */
113 +#define JZ_REG_UDC_INTRINE 0x06 /* Intr IN enable 16-bit */
114 +#define JZ_REG_UDC_INTROUTE 0x08 /* Intr OUT enable 16-bit */
115 +#define JZ_REG_UDC_INTRUSB 0x0a /* Interrupt USB 8-bit */
116 +#define JZ_REG_UDC_INTRUSBE 0x0b /* Interrupt USB Enable 8-bit */
117 +#define JZ_REG_UDC_FRAME 0x0c /* Frame number 16-bit */
118 +#define JZ_REG_UDC_INDEX 0x0e /* Index register 8-bit */
119 +#define JZ_REG_UDC_TESTMODE 0x0f /* USB test mode 8-bit */
120 +
121 +#define JZ_REG_UDC_CSR0 0x12 /* EP0 CSR 8-bit */
122 +#define JZ_REG_UDC_INMAXP 0x10 /* EP1-2 IN Max Pkt Size 16-bit */
123 +#define JZ_REG_UDC_INCSR 0x12 /* EP1-2 IN CSR LSB 8/16bit */
124 +#define JZ_REG_UDC_INCSRH 0x13 /* EP1-2 IN CSR MSB 8-bit */
125 +
126 +#define JZ_REG_UDC_OUTMAXP 0x14 /* EP1 OUT Max Pkt Size 16-bit */
127 +#define JZ_REG_UDC_OUTCSR 0x16 /* EP1 OUT CSR LSB 8/16bit */
128 +#define JZ_REG_UDC_OUTCSRH 0x17 /* EP1 OUT CSR MSB 8-bit */
129 +#define JZ_REG_UDC_OUTCOUNT 0x18 /* bytes in EP0/1 OUT FIFO 16-bit */
130 +
131 +#define JZ_REG_UDC_EP_FIFO(x) (4 * (x) + 0x20)
132 +
133 +#define JZ_REG_UDC_EPINFO 0x78 /* Endpoint information */
134 +#define JZ_REG_UDC_RAMINFO 0x79 /* RAM information */
135 +
136 +#define JZ_REG_UDC_INTR 0x200 /* DMA pending interrupts */
137 +#define JZ_REG_UDC_CNTL1 0x204 /* DMA channel 1 control */
138 +#define JZ_REG_UDC_ADDR1 0x208 /* DMA channel 1 AHB memory addr */
139 +#define JZ_REG_UDC_COUNT1 0x20c /* DMA channel 1 byte count */
140 +#define JZ_REG_UDC_CNTL2 0x214 /* DMA channel 2 control */
141 +#define JZ_REG_UDC_ADDR2 0x218 /* DMA channel 2 AHB memory addr */
142 +#define JZ_REG_UDC_COUNT2 0x21c /* DMA channel 2 byte count */
143 +
144 +/* Power register bit masks */
145 +#define USB_POWER_SUSPENDM 0x01
146 +#define USB_POWER_RESUME 0x04
147 +#define USB_POWER_HSMODE 0x10
148 +#define USB_POWER_HSENAB 0x20
149 +#define USB_POWER_SOFTCONN 0x40
150 +
151 +/* Interrupt register bit masks */
152 +#define USB_INTR_SUSPEND 0x01
153 +#define USB_INTR_RESUME 0x02
154 +#define USB_INTR_RESET 0x04
155 +
156 +#define USB_INTR_EP0 0x0001
157 +#define USB_INTR_INEP1 0x0002
158 +#define USB_INTR_INEP2 0x0004
159 +#define USB_INTR_OUTEP1 0x0002
160 +
161 +/* CSR0 bit masks */
162 +#define USB_CSR0_OUTPKTRDY 0x01
163 +#define USB_CSR0_INPKTRDY 0x02
164 +#define USB_CSR0_SENTSTALL 0x04
165 +#define USB_CSR0_DATAEND 0x08
166 +#define USB_CSR0_SETUPEND 0x10
167 +#define USB_CSR0_SENDSTALL 0x20
168 +#define USB_CSR0_SVDOUTPKTRDY 0x40
169 +#define USB_CSR0_SVDSETUPEND 0x80
170 +
171 +/* Endpoint CSR register bits */
172 +#define USB_INCSRH_AUTOSET 0x80
173 +#define USB_INCSRH_ISO 0x40
174 +#define USB_INCSRH_MODE 0x20
175 +#define USB_INCSRH_DMAREQENAB 0x10
176 +#define USB_INCSRH_DMAREQMODE 0x04
177 +#define USB_INCSR_CDT 0x40
178 +#define USB_INCSR_SENTSTALL 0x20
179 +#define USB_INCSR_SENDSTALL 0x10
180 +#define USB_INCSR_FF 0x08
181 +#define USB_INCSR_UNDERRUN 0x04
182 +#define USB_INCSR_FFNOTEMPT 0x02
183 +#define USB_INCSR_INPKTRDY 0x01
184 +
185 +#define USB_OUTCSRH_AUTOCLR 0x80
186 +#define USB_OUTCSRH_ISO 0x40
187 +#define USB_OUTCSRH_DMAREQENAB 0x20
188 +#define USB_OUTCSRH_DNYT 0x10
189 +#define USB_OUTCSRH_DMAREQMODE 0x08
190 +#define USB_OUTCSR_CDT 0x80
191 +#define USB_OUTCSR_SENTSTALL 0x40
192 +#define USB_OUTCSR_SENDSTALL 0x20
193 +#define USB_OUTCSR_FF 0x10
194 +#define USB_OUTCSR_DATAERR 0x08
195 +#define USB_OUTCSR_OVERRUN 0x04
196 +#define USB_OUTCSR_FFFULL 0x02
197 +#define USB_OUTCSR_OUTPKTRDY 0x01
198 +
199 +/* DMA control bits */
200 +#define USB_CNTL_ENA 0x01
201 +#define USB_CNTL_DIR_IN 0x02
202 +#define USB_CNTL_MODE_1 0x04
203 +#define USB_CNTL_INTR_EN 0x08
204 +#define USB_CNTL_EP(n) ((n) << 4)
205 +#define USB_CNTL_BURST_0 (0 << 9)
206 +#define USB_CNTL_BURST_4 (1 << 9)
207 +#define USB_CNTL_BURST_8 (2 << 9)
208 +#define USB_CNTL_BURST_16 (3 << 9)
209 +
210 +
211 +#ifndef DEBUG
212 +# define DEBUG(fmt,args...) do {} while(0)
213 +#endif
214 +#ifndef DEBUG_EP0
215 +# define NO_STATES
216 +# define DEBUG_EP0(fmt,args...) do {} while(0)
217 +#endif
218 +#ifndef DEBUG_SETUP
219 +# define DEBUG_SETUP(fmt,args...) do {} while(0)
220 +#endif
221 +
222 +/*
223 + * Local declarations.
224 + */
225 +static void jz4740_ep0_kick(struct jz4740_udc *dev, struct jz4740_ep *ep);
226 +static void jz4740_handle_ep0(struct jz4740_udc *dev, uint32_t intr);
227 +
228 +static void done(struct jz4740_ep *ep, struct jz4740_request *req,
229 + int status);
230 +static void pio_irq_enable(struct jz4740_ep *ep);
231 +static void pio_irq_disable(struct jz4740_ep *ep);
232 +static void stop_activity(struct jz4740_udc *dev,
233 + struct usb_gadget_driver *driver);
234 +static void nuke(struct jz4740_ep *ep, int status);
235 +static void flush(struct jz4740_ep *ep);
236 +static void udc_set_address(struct jz4740_udc *dev, unsigned char address);
237 +
238 +/*-------------------------------------------------------------------------*/
239 +
240 +/* inline functions of register read/write/set/clear */
241 +
242 +static inline uint8_t usb_readb(struct jz4740_udc *udc, size_t reg)
243 +{
244 + return readb(udc->base + reg);
245 +}
246 +
247 +static inline uint16_t usb_readw(struct jz4740_udc *udc, size_t reg)
248 +{
249 + return readw(udc->base + reg);
250 +}
251 +
252 +static inline uint32_t usb_readl(struct jz4740_udc *udc, size_t reg)
253 +{
254 + return readl(udc->base + reg);
255 +}
256 +
257 +static inline void usb_writeb(struct jz4740_udc *udc, size_t reg, uint8_t val)
258 +{
259 + writeb(val, udc->base + reg);
260 +}
261 +
262 +static inline void usb_writew(struct jz4740_udc *udc, size_t reg, uint16_t val)
263 +{
264 + writew(val, udc->base + reg);
265 +}
266 +
267 +static inline void usb_writel(struct jz4740_udc *udc, size_t reg, uint32_t val)
268 +{
269 + writel(val, udc->base + reg);
270 +}
271 +
272 +static inline void usb_setb(struct jz4740_udc *udc, size_t reg, uint8_t mask)
273 +{
274 + usb_writeb(udc, reg, usb_readb(udc, reg) | mask);
275 +}
276 +
277 +static inline void usb_setw(struct jz4740_udc *udc, size_t reg, uint16_t mask)
278 +{
279 + usb_writew(udc, reg, usb_readw(udc, reg) | mask);
280 +}
281 +
282 +static inline void usb_clearb(struct jz4740_udc *udc, size_t reg, uint8_t mask)
283 +{
284 + usb_writeb(udc, reg, usb_readb(udc, reg) & ~mask);
285 +}
286 +
287 +static inline void usb_clearw(struct jz4740_udc *udc, size_t reg, uint16_t mask)
288 +{
289 + usb_writew(udc, reg, usb_readw(udc, reg) & ~mask);
290 +}
291 +
292 +/*-------------------------------------------------------------------------*/
293 +
294 +static inline void jz_udc_set_index(struct jz4740_udc *udc, uint8_t index)
295 +{
296 + usb_writeb(udc, JZ_REG_UDC_INDEX, index);
297 +}
298 +
299 +static inline void jz_udc_select_ep(struct jz4740_ep *ep)
300 +{
301 + jz_udc_set_index(ep->dev, ep_index(ep));
302 +}
303 +
304 +static inline int write_packet(struct jz4740_ep *ep,
305 + struct jz4740_request *req, unsigned int count)
306 +{
307 + uint8_t *buf;
308 + unsigned int length;
309 + void __iomem *fifo = ep->dev->base + ep->fifo;
310 +
311 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
312 +
313 + buf = req->req.buf + req->req.actual;
314 +
315 + length = req->req.length - req->req.actual;
316 + if (length > count)
317 + length = count;
318 + req->req.actual += length;
319 +
320 + DEBUG("Write %d (count %d), fifo %x\n", length, count, ep->fifo);
321 +
322 + writesl(fifo, buf, length >> 2);
323 + writesb(fifo, &buf[length - (length & 3)], length & 3);
324 +
325 + return length;
326 +}
327 +
328 +static int read_packet(struct jz4740_ep *ep,
329 + struct jz4740_request *req, unsigned int count)
330 +{
331 + uint8_t *buf;
332 + unsigned int length;
333 + void __iomem *fifo = ep->dev->base + ep->fifo;
334 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
335 +
336 + buf = req->req.buf + req->req.actual;
337 +
338 + length = req->req.length - req->req.actual;
339 + if (length > count)
340 + length = count;
341 + req->req.actual += length;
342 +
343 + DEBUG("Read %d, fifo %x\n", length, ep->fifo);
344 +
345 + readsl(fifo, buf, length >> 2);
346 + readsb(fifo, &buf[length - (length & 3)], length & 3);
347 +
348 + return length;
349 +}
350 +
351 +/*-------------------------------------------------------------------------*/
352 +
353 +/*
354 + * udc_disable - disable USB device controller
355 + */
356 +static void udc_disable(struct jz4740_udc *dev)
357 +{
358 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
359 +
360 + udc_set_address(dev, 0);
361 +
362 + /* Disable interrupts */
363 + usb_writew(dev, JZ_REG_UDC_INTRINE, 0);
364 + usb_writew(dev, JZ_REG_UDC_INTROUTE, 0);
365 + usb_writeb(dev, JZ_REG_UDC_INTRUSBE, 0);
366 +
367 + /* Disable DMA */
368 + usb_writel(dev, JZ_REG_UDC_CNTL1, 0);
369 + usb_writel(dev, JZ_REG_UDC_CNTL2, 0);
370 +
371 + /* Disconnect from usb */
372 + usb_clearb(dev, JZ_REG_UDC_POWER, USB_POWER_SOFTCONN);
373 +
374 + /* Disable the USB PHY */
375 + clk_disable_unprepare(dev->clk);
376 +
377 + dev->ep0state = WAIT_FOR_SETUP;
378 + dev->gadget.speed = USB_SPEED_UNKNOWN;
379 +
380 + return;
381 +}
382 +
383 +/*
384 + * udc_reinit - initialize software state
385 + */
386 +static void udc_reinit(struct jz4740_udc *dev)
387 +{
388 + int i;
389 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
390 +
391 + /* device/ep0 records init */
392 + INIT_LIST_HEAD(&dev->gadget.ep_list);
393 + INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
394 + dev->ep0state = WAIT_FOR_SETUP;
395 +
396 + for (i = 0; i < UDC_MAX_ENDPOINTS; i++) {
397 + struct jz4740_ep *ep = &dev->ep[i];
398 +
399 + if (i != 0)
400 + list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
401 +
402 + INIT_LIST_HEAD(&ep->queue);
403 + ep->desc = 0;
404 + ep->stopped = 0;
405 + }
406 +}
407 +
408 +/* until it's enabled, this UDC should be completely invisible
409 + * to any USB host.
410 + */
411 +static void udc_enable(struct jz4740_udc *dev)
412 +{
413 + int i;
414 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
415 +
416 + /* UDC state is incorrect - Added by River */
417 + if (dev->state != UDC_STATE_ENABLE) {
418 + return;
419 + }
420 +
421 + dev->gadget.speed = USB_SPEED_UNKNOWN;
422 +
423 + /* Flush FIFO for each */
424 + for (i = 0; i < UDC_MAX_ENDPOINTS; i++) {
425 + struct jz4740_ep *ep = &dev->ep[i];
426 +
427 + jz_udc_select_ep(ep);
428 + flush(ep);
429 + }
430 +
431 + /* Set this bit to allow the UDC entering low-power mode when
432 + * there are no actions on the USB bus.
433 + * UDC still works during this bit was set.
434 + */
435 + jz4740_clock_udc_enable_auto_suspend();
436 +
437 + /* Enable the USB PHY */
438 + clk_prepare_enable(dev->clk);
439 +
440 + /* Disable interrupts */
441 +/* usb_writew(dev, JZ_REG_UDC_INTRINE, 0);
442 + usb_writew(dev, JZ_REG_UDC_INTROUTE, 0);
443 + usb_writeb(dev, JZ_REG_UDC_INTRUSBE, 0);*/
444 +
445 + /* Enable interrupts */
446 + usb_setw(dev, JZ_REG_UDC_INTRINE, USB_INTR_EP0);
447 + usb_setb(dev, JZ_REG_UDC_INTRUSBE, USB_INTR_RESET);
448 + /* Don't enable rest of the interrupts */
449 + /* usb_setw(dev, JZ_REG_UDC_INTRINE, USB_INTR_INEP1 | USB_INTR_INEP2);
450 + usb_setw(dev, JZ_REG_UDC_INTROUTE, USB_INTR_OUTEP1); */
451 +
452 + /* Enable SUSPEND */
453 + /* usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_SUSPENDM); */
454 +
455 + /* Enable HS Mode */
456 + usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_HSENAB);
457 +
458 + /* Let host detect UDC:
459 + * Software must write a 1 to the PMR:USB_POWER_SOFTCONN bit to turn this
460 + * transistor on and pull the USBDP pin HIGH.
461 + */
462 + usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_SOFTCONN);
463 +
464 + return;
465 +}
466 +
467 +/*-------------------------------------------------------------------------*/
468 +
469 +/* keeping it simple:
470 + * - one bus driver, initted first;
471 + * - one function driver, initted second
472 + */
473 +
474 +/*
475 + * Register entry point for the peripheral controller driver.
476 + */
477 +
478 +static int jz4740_udc_start(struct usb_gadget *gadget,
479 + struct usb_gadget_driver *driver)
480 +{
481 + struct jz4740_udc *udc = container_of(gadget, struct jz4740_udc, gadget);
482 +
483 + /* hook up the driver */
484 + udc->driver = driver;
485 +
486 +
487 + /* then enable host detection and ep0; and we're ready
488 + * for set_configuration as well as eventual disconnect.
489 + */
490 + udc_enable(udc);
491 +
492 + DEBUG("%s: registered gadget driver '%s'\n", gadget->name,
493 + driver->driver.name);
494 +
495 + return 0;
496 +}
497 +
498 +static void stop_activity(struct jz4740_udc *dev,
499 + struct usb_gadget_driver *driver)
500 +{
501 + int i;
502 +
503 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
504 +
505 + /* don't disconnect drivers more than once */
506 + if (dev->gadget.speed == USB_SPEED_UNKNOWN)
507 + driver = 0;
508 + dev->gadget.speed = USB_SPEED_UNKNOWN;
509 +
510 + /* prevent new request submissions, kill any outstanding requests */
511 + for (i = 0; i < UDC_MAX_ENDPOINTS; i++) {
512 + struct jz4740_ep *ep = &dev->ep[i];
513 +
514 + ep->stopped = 1;
515 +
516 + jz_udc_select_ep(ep);
517 + nuke(ep, -ESHUTDOWN);
518 + }
519 +
520 + /* report disconnect; the driver is already quiesced */
521 + if (driver) {
522 + spin_unlock(&dev->lock);
523 + driver->disconnect(&dev->gadget);
524 + spin_lock(&dev->lock);
525 + }
526 +
527 + /* re-init driver-visible data structures */
528 + udc_reinit(dev);
529 +}
530 +
531 +
532 +/*
533 + * Unregister entry point for the peripheral controller driver.
534 + */
535 +static int jz4740_udc_stop(struct usb_gadget *gadget,
536 + struct usb_gadget_driver *driver)
537 +{
538 + struct jz4740_udc *udc = container_of(gadget, struct jz4740_udc, gadget);
539 + unsigned long flags;
540 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
541 +
542 + spin_lock_irqsave(&udc->lock, flags);
543 + udc->driver = NULL;
544 + stop_activity(udc, driver);
545 + spin_unlock_irqrestore(&udc->lock, flags);
546 +
547 + udc_disable(udc);
548 +
549 + DEBUG("unregistered driver '%s'\n", driver->driver.name);
550 +
551 + return 0;
552 +}
553 +
554 +/*-------------------------------------------------------------------------*/
555 +
556 +/** Write request to FIFO (max write == maxp size)
557 + * Return: 0 = still running, 1 = completed, negative = errno
558 + * NOTE: INDEX register must be set for EP
559 + */
560 +static int write_fifo(struct jz4740_ep *ep, struct jz4740_request *req)
561 +{
562 + struct jz4740_udc *dev = ep->dev;
563 + uint32_t max, csr;
564 +
565 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
566 + max = le16_to_cpu(ep->desc->wMaxPacketSize);
567 +
568 + csr = usb_readb(dev, ep->csr);
569 +
570 + if (!(csr & USB_INCSR_FFNOTEMPT)) {
571 + unsigned count;
572 + int is_last, is_short;
573 +
574 + count = write_packet(ep, req, max);
575 + usb_setb(dev, ep->csr, USB_INCSR_INPKTRDY);
576 +
577 + /* last packet is usually short (or a zlp) */
578 + if (unlikely(count != max))
579 + is_last = is_short = 1;
580 + else {
581 + if (likely(req->req.length != req->req.actual)
582 + || req->req.zero)
583 + is_last = 0;
584 + else
585 + is_last = 1;
586 + /* interrupt/iso maxpacket may not fill the fifo */
587 + is_short = unlikely(max < ep_maxpacket(ep));
588 + }
589 +
590 + DEBUG("%s: wrote %s %d bytes%s%s %d left %p\n", __FUNCTION__,
591 + ep->ep.name, count,
592 + is_last ? "/L" : "", is_short ? "/S" : "",
593 + req->req.length - req->req.actual, req);
594 +
595 + /* requests complete when all IN data is in the FIFO */
596 + if (is_last) {
597 + done(ep, req, 0);
598 + if (list_empty(&ep->queue)) {
599 + pio_irq_disable(ep);
600 + }
601 + return 1;
602 + }
603 + } else {
604 + DEBUG("Hmm.. %d ep FIFO is not empty!\n", ep_index(ep));
605 + }
606 +
607 + return 0;
608 +}
609 +
610 +/** Read to request from FIFO (max read == bytes in fifo)
611 + * Return: 0 = still running, 1 = completed, negative = errno
612 + * NOTE: INDEX register must be set for EP
613 + */
614 +static int read_fifo(struct jz4740_ep *ep, struct jz4740_request *req)
615 +{
616 + struct jz4740_udc *dev = ep->dev;
617 + uint32_t csr;
618 + unsigned count, is_short;
619 +
620 + /* make sure there's a packet in the FIFO. */
621 + csr = usb_readb(dev, ep->csr);
622 + if (!(csr & USB_OUTCSR_OUTPKTRDY)) {
623 + DEBUG("%s: Packet NOT ready!\n", __FUNCTION__);
624 + return -EINVAL;
625 + }
626 +
627 + /* read all bytes from this packet */
628 + count = usb_readw(dev, JZ_REG_UDC_OUTCOUNT);
629 +
630 + is_short = (count < ep->ep.maxpacket);
631 +
632 + count = read_packet(ep, req, count);
633 +
634 + DEBUG("read %s %02x, %d bytes%s req %p %d/%d\n",
635 + ep->ep.name, csr, count,
636 + is_short ? "/S" : "", req, req->req.actual, req->req.length);
637 +
638 + /* Clear OutPktRdy */
639 + usb_clearb(dev, ep->csr, USB_OUTCSR_OUTPKTRDY);
640 +
641 + /* completion */
642 + if (is_short || req->req.actual == req->req.length) {
643 + done(ep, req, 0);
644 +
645 + if (list_empty(&ep->queue))
646 + pio_irq_disable(ep);
647 + return 1;
648 + }
649 +
650 + /* finished that packet. the next one may be waiting... */
651 + return 0;
652 +}
653 +
654 +/*
655 + * done - retire a request; caller blocked irqs
656 + * INDEX register is preserved to keep same
657 + */
658 +static void done(struct jz4740_ep *ep, struct jz4740_request *req, int status)
659 +{
660 + unsigned int stopped = ep->stopped;
661 + uint32_t index;
662 +
663 + DEBUG("%s, %p\n", __FUNCTION__, ep);
664 + list_del_init(&req->queue);
665 +
666 + if (likely(req->req.status == -EINPROGRESS))
667 + req->req.status = status;
668 + else
669 + status = req->req.status;
670 +
671 + if (status && status != -ESHUTDOWN)
672 + DEBUG("complete %s req %p stat %d len %u/%u\n",
673 + ep->ep.name, &req->req, status,
674 + req->req.actual, req->req.length);
675 +
676 + /* don't modify queue heads during completion callback */
677 + ep->stopped = 1;
678 + /* Read current index (completion may modify it) */
679 + index = usb_readb(ep->dev, JZ_REG_UDC_INDEX);
680 + spin_unlock_irqrestore(&ep->dev->lock, ep->dev->lock_flags);
681 +
682 + req->req.complete(&ep->ep, &req->req);
683 +
684 + spin_lock_irqsave(&ep->dev->lock, ep->dev->lock_flags);
685 + /* Restore index */
686 + jz_udc_set_index(ep->dev, index);
687 + ep->stopped = stopped;
688 +}
689 +
690 +static inline unsigned int jz4740_udc_ep_irq_enable_reg(struct jz4740_ep *ep)
691 +{
692 + if (ep_is_in(ep))
693 + return JZ_REG_UDC_INTRINE;
694 + else
695 + return JZ_REG_UDC_INTROUTE;
696 +}
697 +
698 +/** Enable EP interrupt */
699 +static void pio_irq_enable(struct jz4740_ep *ep)
700 +{
701 + DEBUG("%s: EP%d %s\n", __FUNCTION__, ep_index(ep), ep_is_in(ep) ? "IN": "OUT");
702 +
703 + usb_setw(ep->dev, jz4740_udc_ep_irq_enable_reg(ep), BIT(ep_index(ep)));
704 +}
705 +
706 +/** Disable EP interrupt */
707 +static void pio_irq_disable(struct jz4740_ep *ep)
708 +{
709 + DEBUG("%s: EP%d %s\n", __FUNCTION__, ep_index(ep), ep_is_in(ep) ? "IN": "OUT");
710 +
711 + usb_clearw(ep->dev, jz4740_udc_ep_irq_enable_reg(ep), BIT(ep_index(ep)));
712 +}
713 +
714 +/*
715 + * nuke - dequeue ALL requests
716 + */
717 +static void nuke(struct jz4740_ep *ep, int status)
718 +{
719 + struct jz4740_request *req;
720 +
721 + DEBUG("%s, %p\n", __FUNCTION__, ep);
722 +
723 + /* Flush FIFO */
724 + flush(ep);
725 +
726 + /* called with irqs blocked */
727 + while (!list_empty(&ep->queue)) {
728 + req = list_entry(ep->queue.next, struct jz4740_request, queue);
729 + done(ep, req, status);
730 + }
731 +
732 + /* Disable IRQ if EP is enabled (has descriptor) */
733 + if (ep->desc)
734 + pio_irq_disable(ep);
735 +}
736 +
737 +/** Flush EP FIFO
738 + * NOTE: INDEX register must be set before this call
739 + */
740 +static void flush(struct jz4740_ep *ep)
741 +{
742 + DEBUG("%s: %s\n", __FUNCTION__, ep->ep.name);
743 +
744 + switch (ep->type) {
745 + case ep_bulk_in:
746 + case ep_interrupt:
747 + usb_setb(ep->dev, ep->csr, USB_INCSR_FF);
748 + break;
749 + case ep_bulk_out:
750 + usb_setb(ep->dev, ep->csr, USB_OUTCSR_FF);
751 + break;
752 + case ep_control:
753 + break;
754 + }
755 +}
756 +
757 +/**
758 + * jz4740_in_epn - handle IN interrupt
759 + */
760 +static void jz4740_in_epn(struct jz4740_udc *dev, uint32_t ep_idx, uint32_t intr)
761 +{
762 + uint32_t csr;
763 + struct jz4740_ep *ep = &dev->ep[ep_idx + 1];
764 + struct jz4740_request *req;
765 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
766 +
767 + jz_udc_select_ep(ep);
768 +
769 + csr = usb_readb(dev, ep->csr);
770 + DEBUG("%s: %d, csr %x\n", __FUNCTION__, ep_idx, csr);
771 +
772 + if (csr & USB_INCSR_SENTSTALL) {
773 + DEBUG("USB_INCSR_SENTSTALL\n");
774 + usb_clearb(dev, ep->csr, USB_INCSR_SENTSTALL);
775 + return;
776 + }
777 +
778 + if (!ep->desc) {
779 + DEBUG("%s: NO EP DESC\n", __FUNCTION__);
780 + return;
781 + }
782 +
783 + if (!list_empty(&ep->queue)) {
784 + req = list_first_entry(&ep->queue, struct jz4740_request, queue);
785 + write_fifo(ep, req);
786 + }
787 +}
788 +
789 +/*
790 + * Bulk OUT (recv)
791 + */
792 +static void jz4740_out_epn(struct jz4740_udc *dev, uint32_t ep_idx, uint32_t intr)
793 +{
794 + struct jz4740_ep *ep = &dev->ep[ep_idx];
795 + struct jz4740_request *req;
796 +
797 + DEBUG("%s: %d\n", __FUNCTION__, ep_idx);
798 +
799 + jz_udc_select_ep(ep);
800 + if (ep->desc) {
801 + uint32_t csr;
802 +
803 + while ((csr = usb_readb(dev, ep->csr)) &
804 + (USB_OUTCSR_OUTPKTRDY | USB_OUTCSR_SENTSTALL)) {
805 + DEBUG("%s: %x\n", __FUNCTION__, csr);
806 +
807 + if (csr & USB_OUTCSR_SENTSTALL) {
808 + DEBUG("%s: stall sent, flush fifo\n",
809 + __FUNCTION__);
810 + /* usb_set(USB_OUT_CSR1_FIFO_FLUSH, ep->csr1); */
811 + flush(ep);
812 + } else if (csr & USB_OUTCSR_OUTPKTRDY) {
813 + if (list_empty(&ep->queue))
814 + req = 0;
815 + else
816 + req =
817 + list_entry(ep->queue.next,
818 + struct jz4740_request,
819 + queue);
820 +
821 + if (!req) {
822 + DEBUG("%s: NULL REQ %d\n",
823 + __FUNCTION__, ep_idx);
824 + break;
825 + } else {
826 + read_fifo(ep, req);
827 + }
828 + }
829 + }
830 + } else {
831 + /* Throw packet away.. */
832 + DEBUG("%s: ep %p ep_indx %d No descriptor?!?\n", __FUNCTION__, ep, ep_idx);
833 + flush(ep);
834 + }
835 +}
836 +
837 +/** Halt specific EP
838 + * Return 0 if success
839 + * NOTE: Sets INDEX register to EP !
840 + */
841 +static int jz4740_set_halt(struct usb_ep *_ep, int value)
842 +{
843 + struct jz4740_udc *dev;
844 + struct jz4740_ep *ep;
845 + unsigned long flags;
846 +
847 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
848 +
849 + ep = container_of(_ep, struct jz4740_ep, ep);
850 + if (unlikely(!_ep || (!ep->desc && ep->type != ep_control))) {
851 + DEBUG("%s, bad ep\n", __FUNCTION__);
852 + return -EINVAL;
853 + }
854 +
855 + dev = ep->dev;
856 +
857 + spin_lock_irqsave(&dev->lock, flags);
858 +
859 + jz_udc_select_ep(ep);
860 +
861 + DEBUG("%s, ep %d, val %d\n", __FUNCTION__, ep_index(ep), value);
862 +
863 + if (ep_index(ep) == 0) {
864 + /* EP0 */
865 + usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SENDSTALL);
866 + } else if (ep_is_in(ep)) {
867 + uint32_t csr = usb_readb(dev, ep->csr);
868 + if (value && ((csr & USB_INCSR_FFNOTEMPT)
869 + || !list_empty(&ep->queue))) {
870 + /*
871 + * Attempts to halt IN endpoints will fail (returning -EAGAIN)
872 + * if any transfer requests are still queued, or if the controller
873 + * FIFO still holds bytes that the host hasn\92t collected.
874 + */
875 + spin_unlock_irqrestore(&dev->lock, flags);
876 + DEBUG
877 + ("Attempt to halt IN endpoint failed (returning -EAGAIN) %d %d\n",
878 + (csr & USB_INCSR_FFNOTEMPT),
879 + !list_empty(&ep->queue));
880 + return -EAGAIN;
881 + }
882 + flush(ep);
883 + if (value) {
884 + usb_setb(dev, ep->csr, USB_INCSR_SENDSTALL);
885 + } else {
886 + usb_clearb(dev, ep->csr, USB_INCSR_SENDSTALL);
887 + usb_setb(dev, ep->csr, USB_INCSR_CDT);
888 + }
889 + } else {
890 +
891 + flush(ep);
892 + if (value) {
893 + usb_setb(dev, ep->csr, USB_OUTCSR_SENDSTALL);
894 + } else {
895 + usb_clearb(dev, ep->csr, USB_OUTCSR_SENDSTALL);
896 + usb_setb(dev, ep->csr, USB_OUTCSR_CDT);
897 + }
898 + }
899 +
900 + ep->stopped = value;
901 +
902 + spin_unlock_irqrestore(&dev->lock, flags);
903 +
904 + DEBUG("%s %s halted\n", _ep->name, value == 0 ? "NOT" : "IS");
905 +
906 + return 0;
907 +}
908 +
909 +
910 +static int jz4740_ep_enable(struct usb_ep *_ep,
911 + const struct usb_endpoint_descriptor *desc)
912 +{
913 + struct jz4740_ep *ep;
914 + struct jz4740_udc *dev;
915 + unsigned long flags;
916 + uint32_t max, csrh = 0;
917 +
918 + DEBUG("%s: trying to enable %s\n", __FUNCTION__, _ep->name);
919 +
920 + if (!_ep || !desc)
921 + return -EINVAL;
922 +
923 + ep = container_of(_ep, struct jz4740_ep, ep);
924 + if (ep->desc || ep->type == ep_control
925 + || desc->bDescriptorType != USB_DT_ENDPOINT
926 + || ep->bEndpointAddress != desc->bEndpointAddress) {
927 + DEBUG("%s, bad ep or descriptor\n", __FUNCTION__);
928 + return -EINVAL;
929 + }
930 +
931 + /* xfer types must match, except that interrupt ~= bulk */
932 + if (ep->bmAttributes != desc->bmAttributes
933 + && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
934 + && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
935 + DEBUG("%s, %s type mismatch\n", __FUNCTION__, _ep->name);
936 + return -EINVAL;
937 + }
938 +
939 + dev = ep->dev;
940 + if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) {
941 + DEBUG("%s, bogus device state\n", __FUNCTION__);
942 + return -ESHUTDOWN;
943 + }
944 +
945 + max = le16_to_cpu(desc->wMaxPacketSize);
946 +
947 + spin_lock_irqsave(&ep->dev->lock, flags);
948 +
949 + /* Configure the endpoint */
950 + jz_udc_select_ep(ep);
951 + if (ep_is_in(ep)) {
952 + usb_writew(dev, JZ_REG_UDC_INMAXP, max);
953 + switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
954 + case USB_ENDPOINT_XFER_BULK:
955 + case USB_ENDPOINT_XFER_INT:
956 + csrh &= ~USB_INCSRH_ISO;
957 + break;
958 + case USB_ENDPOINT_XFER_ISOC:
959 + csrh |= USB_INCSRH_ISO;
960 + break;
961 + }
962 + usb_writeb(dev, JZ_REG_UDC_INCSRH, csrh);
963 + }
964 + else {
965 + usb_writew(dev, JZ_REG_UDC_OUTMAXP, max);
966 + switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
967 + case USB_ENDPOINT_XFER_BULK:
968 + csrh &= ~USB_OUTCSRH_ISO;
969 + break;
970 + case USB_ENDPOINT_XFER_INT:
971 + csrh &= ~USB_OUTCSRH_ISO;
972 + csrh |= USB_OUTCSRH_DNYT;
973 + break;
974 + case USB_ENDPOINT_XFER_ISOC:
975 + csrh |= USB_OUTCSRH_ISO;
976 + break;
977 + }
978 + usb_writeb(dev, JZ_REG_UDC_OUTCSRH, csrh);
979 + }
980 +
981 +
982 + ep->stopped = 0;
983 + ep->desc = desc;
984 + ep->ep.maxpacket = max;
985 +
986 + spin_unlock_irqrestore(&ep->dev->lock, flags);
987 +
988 + /* Reset halt state (does flush) */
989 + jz4740_set_halt(_ep, 0);
990 +
991 + DEBUG("%s: enabled %s\n", __FUNCTION__, _ep->name);
992 +
993 + return 0;
994 +}
995 +
996 +/** Disable EP
997 + * NOTE: Sets INDEX register
998 + */
999 +static int jz4740_ep_disable(struct usb_ep *_ep)
1000 +{
1001 + struct jz4740_ep *ep;
1002 + unsigned long flags;
1003 +
1004 + DEBUG("%s, %p\n", __FUNCTION__, _ep);
1005 +
1006 + ep = container_of(_ep, struct jz4740_ep, ep);
1007 + if (!_ep || !ep->desc) {
1008 + DEBUG("%s, %s not enabled\n", __FUNCTION__,
1009 + _ep ? ep->ep.name : NULL);
1010 + return -EINVAL;
1011 + }
1012 +
1013 + spin_lock_irqsave(&ep->dev->lock, flags);
1014 +
1015 + jz_udc_select_ep(ep);
1016 +
1017 + /* Nuke all pending requests (does flush) */
1018 + nuke(ep, -ESHUTDOWN);
1019 +
1020 + /* Disable ep IRQ */
1021 + pio_irq_disable(ep);
1022 +
1023 + ep->desc = 0;
1024 + ep->stopped = 1;
1025 +
1026 + spin_unlock_irqrestore(&ep->dev->lock, flags);
1027 +
1028 + DEBUG("%s: disabled %s\n", __FUNCTION__, _ep->name);
1029 + return 0;
1030 +}
1031 +
1032 +static struct usb_request *jz4740_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
1033 +{
1034 + struct jz4740_request *req;
1035 +
1036 + req = kzalloc(sizeof(*req), gfp_flags);
1037 + if (!req)
1038 + return NULL;
1039 +
1040 + INIT_LIST_HEAD(&req->queue);
1041 +
1042 + return &req->req;
1043 +}
1044 +
1045 +static void jz4740_free_request(struct usb_ep *ep, struct usb_request *_req)
1046 +{
1047 + struct jz4740_request *req;
1048 +
1049 + req = container_of(_req, struct jz4740_request, req);
1050 + WARN_ON(!list_empty(&req->queue));
1051 +
1052 + kfree(req);
1053 +}
1054 +
1055 +/*--------------------------------------------------------------------*/
1056 +
1057 +/** Queue one request
1058 + * Kickstart transfer if needed
1059 + * NOTE: Sets INDEX register
1060 + */
1061 +static int jz4740_queue(struct usb_ep *_ep, struct usb_request *_req,
1062 + gfp_t gfp_flags)
1063 +{
1064 + struct jz4740_request *req;
1065 + struct jz4740_ep *ep;
1066 + struct jz4740_udc *dev;
1067 +
1068 + DEBUG("%s, %p\n", __FUNCTION__, _ep);
1069 +
1070 + req = container_of(_req, struct jz4740_request, req);
1071 + if (unlikely
1072 + (!_req || !_req->complete || !_req->buf
1073 + || !list_empty(&req->queue))) {
1074 + DEBUG("%s, bad params\n", __FUNCTION__);
1075 + return -EINVAL;
1076 + }
1077 +
1078 + ep = container_of(_ep, struct jz4740_ep, ep);
1079 + if (unlikely(!_ep || (!ep->desc && ep->type != ep_control))) {
1080 + DEBUG("%s, bad ep\n", __FUNCTION__);
1081 + return -EINVAL;
1082 + }
1083 +
1084 + dev = ep->dev;
1085 + if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
1086 + DEBUG("%s, bogus device state %p\n", __FUNCTION__, dev->driver);
1087 + return -ESHUTDOWN;
1088 + }
1089 +
1090 + DEBUG("%s queue req %p, len %d buf %p\n", _ep->name, _req, _req->length,
1091 + _req->buf);
1092 +
1093 + spin_lock_irqsave(&dev->lock, dev->lock_flags);
1094 +
1095 + _req->status = -EINPROGRESS;
1096 + _req->actual = 0;
1097 +
1098 + /* kickstart this i/o queue? */
1099 + DEBUG("Add to %d Q %d %d\n", ep_index(ep), list_empty(&ep->queue),
1100 + ep->stopped);
1101 + if (list_empty(&ep->queue) && likely(!ep->stopped)) {
1102 + uint32_t csr;
1103 +
1104 + if (unlikely(ep_index(ep) == 0)) {
1105 + /* EP0 */
1106 + list_add_tail(&req->queue, &ep->queue);
1107 + jz4740_ep0_kick(dev, ep);
1108 + req = 0;
1109 + }
1110 + else if (ep_is_in(ep)) {
1111 + /* EP1 & EP2 */
1112 + jz_udc_select_ep(ep);
1113 + csr = usb_readb(dev, ep->csr);
1114 + pio_irq_enable(ep);
1115 + if (!(csr & USB_INCSR_FFNOTEMPT)) {
1116 + if (write_fifo(ep, req) == 1)
1117 + req = 0;
1118 + }
1119 + } else {
1120 + /* EP1 */
1121 + jz_udc_select_ep(ep);
1122 + csr = usb_readb(dev, ep->csr);
1123 + pio_irq_enable(ep);
1124 + if (csr & USB_OUTCSR_OUTPKTRDY) {
1125 + if (read_fifo(ep, req) == 1)
1126 + req = 0;
1127 + }
1128 + }
1129 + }
1130 +
1131 + /* pio or dma irq handler advances the queue. */
1132 + if (likely(req != 0))
1133 + list_add_tail(&req->queue, &ep->queue);
1134 +
1135 + spin_unlock_irqrestore(&dev->lock, dev->lock_flags);
1136 +
1137 + return 0;
1138 +}
1139 +
1140 +/* dequeue JUST ONE request */
1141 +static int jz4740_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1142 +{
1143 + struct jz4740_ep *ep;
1144 + struct jz4740_request *req;
1145 + unsigned long flags;
1146 +
1147 + DEBUG("%s, %p\n", __FUNCTION__, _ep);
1148 +
1149 + ep = container_of(_ep, struct jz4740_ep, ep);
1150 + if (!_ep || ep->type == ep_control)
1151 + return -EINVAL;
1152 +
1153 + spin_lock_irqsave(&ep->dev->lock, flags);
1154 +
1155 + /* make sure it's actually queued on this endpoint */
1156 + list_for_each_entry(req, &ep->queue, queue) {
1157 + if (&req->req == _req)
1158 + break;
1159 + }
1160 + if (&req->req != _req) {
1161 + spin_unlock_irqrestore(&ep->dev->lock, flags);
1162 + return -EINVAL;
1163 + }
1164 + done(ep, req, -ECONNRESET);
1165 +
1166 + spin_unlock_irqrestore(&ep->dev->lock, flags);
1167 + return 0;
1168 +}
1169 +
1170 +/** Return bytes in EP FIFO
1171 + * NOTE: Sets INDEX register to EP
1172 + */
1173 +static int jz4740_fifo_status(struct usb_ep *_ep)
1174 +{
1175 + uint32_t csr;
1176 + int count = 0;
1177 + struct jz4740_ep *ep;
1178 + unsigned long flags;
1179 +
1180 + ep = container_of(_ep, struct jz4740_ep, ep);
1181 + if (!_ep) {
1182 + DEBUG("%s, bad ep\n", __FUNCTION__);
1183 + return -ENODEV;
1184 + }
1185 +
1186 + DEBUG("%s, %d\n", __FUNCTION__, ep_index(ep));
1187 +
1188 + /* LPD can't report unclaimed bytes from IN fifos */
1189 + if (ep_is_in(ep))
1190 + return -EOPNOTSUPP;
1191 +
1192 + spin_lock_irqsave(&ep->dev->lock, flags);
1193 + jz_udc_select_ep(ep);
1194 +
1195 + csr = usb_readb(ep->dev, ep->csr);
1196 + if (ep->dev->gadget.speed != USB_SPEED_UNKNOWN ||
1197 + csr & 0x1) {
1198 + count = usb_readw(ep->dev, JZ_REG_UDC_OUTCOUNT);
1199 + }
1200 +
1201 + spin_unlock_irqrestore(&ep->dev->lock, flags);
1202 +
1203 + return count;
1204 +}
1205 +
1206 +/** Flush EP FIFO
1207 + * NOTE: Sets INDEX register to EP
1208 + */
1209 +static void jz4740_fifo_flush(struct usb_ep *_ep)
1210 +{
1211 + struct jz4740_ep *ep;
1212 + unsigned long flags;
1213 +
1214 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1215 +
1216 + ep = container_of(_ep, struct jz4740_ep, ep);
1217 + if (unlikely(!_ep || (!ep->desc && ep->type == ep_control))) {
1218 + DEBUG("%s, bad ep\n", __FUNCTION__);
1219 + return;
1220 + }
1221 +
1222 + spin_lock_irqsave(&ep->dev->lock, flags);
1223 +
1224 + jz_udc_select_ep(ep);
1225 + flush(ep);
1226 +
1227 + spin_unlock_irqrestore(&ep->dev->lock, flags);
1228 +}
1229 +
1230 +/****************************************************************/
1231 +/* End Point 0 related functions */
1232 +/****************************************************************/
1233 +
1234 +/* return: 0 = still running, 1 = completed, negative = errno */
1235 +static int write_fifo_ep0(struct jz4740_ep *ep, struct jz4740_request *req)
1236 +{
1237 + uint32_t max;
1238 + unsigned count;
1239 + int is_last;
1240 +
1241 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1242 + max = ep_maxpacket(ep);
1243 +
1244 + count = write_packet(ep, req, max);
1245 +
1246 + /* last packet is usually short (or a zlp) */
1247 + if (unlikely(count != max))
1248 + is_last = 1;
1249 + else {
1250 + if (likely(req->req.length != req->req.actual) || req->req.zero)
1251 + is_last = 0;
1252 + else
1253 + is_last = 1;
1254 + }
1255 +
1256 + DEBUG_EP0("%s: wrote %s %d bytes%s %d left %p\n", __FUNCTION__,
1257 + ep->ep.name, count,
1258 + is_last ? "/L" : "", req->req.length - req->req.actual, req);
1259 +
1260 + /* requests complete when all IN data is in the FIFO */
1261 + if (is_last) {
1262 + done(ep, req, 0);
1263 + return 1;
1264 + }
1265 +
1266 + return 0;
1267 +}
1268 +
1269 +static inline int jz4740_fifo_read(struct jz4740_ep *ep,
1270 + unsigned char *cp, int max)
1271 +{
1272 + int bytes;
1273 + int count = usb_readw(ep->dev, JZ_REG_UDC_OUTCOUNT);
1274 +
1275 + if (count > max)
1276 + count = max;
1277 + bytes = count;
1278 + while (count--)
1279 + *cp++ = usb_readb(ep->dev, ep->fifo);
1280 +
1281 + return bytes;
1282 +}
1283 +
1284 +static inline void jz4740_fifo_write(struct jz4740_ep *ep,
1285 + unsigned char *cp, int count)
1286 +{
1287 + DEBUG("fifo_write: %d %d\n", ep_index(ep), count);
1288 + while (count--)
1289 + usb_writeb(ep->dev, ep->fifo, *cp++);
1290 +}
1291 +
1292 +static int read_fifo_ep0(struct jz4740_ep *ep, struct jz4740_request *req)
1293 +{
1294 + struct jz4740_udc *dev = ep->dev;
1295 + uint32_t csr;
1296 + uint8_t *buf;
1297 + unsigned bufferspace, count, is_short;
1298 +
1299 + DEBUG_EP0("%s\n", __FUNCTION__);
1300 +
1301 + csr = usb_readb(dev, JZ_REG_UDC_CSR0);
1302 + if (!(csr & USB_CSR0_OUTPKTRDY))
1303 + return 0;
1304 +
1305 + buf = req->req.buf + req->req.actual;
1306 + prefetchw(buf);
1307 + bufferspace = req->req.length - req->req.actual;
1308 +
1309 + /* read all bytes from this packet */
1310 + if (likely(csr & USB_CSR0_OUTPKTRDY)) {
1311 + count = usb_readw(dev, JZ_REG_UDC_OUTCOUNT);
1312 + req->req.actual += min(count, bufferspace);
1313 + } else /* zlp */
1314 + count = 0;
1315 +
1316 + is_short = (count < ep->ep.maxpacket);
1317 + DEBUG_EP0("read %s %02x, %d bytes%s req %p %d/%d\n",
1318 + ep->ep.name, csr, count,
1319 + is_short ? "/S" : "", req, req->req.actual, req->req.length);
1320 +
1321 + while (likely(count-- != 0)) {
1322 + uint8_t byte = (uint8_t)usb_readl(dev, ep->fifo);
1323 +
1324 + if (unlikely(bufferspace == 0)) {
1325 + /* this happens when the driver's buffer
1326 + * is smaller than what the host sent.
1327 + * discard the extra data.
1328 + */
1329 + if (req->req.status != -EOVERFLOW)
1330 + DEBUG_EP0("%s overflow %d\n", ep->ep.name,
1331 + count);
1332 + req->req.status = -EOVERFLOW;
1333 + } else {
1334 + *buf++ = byte;
1335 + bufferspace--;
1336 + }
1337 + }
1338 +
1339 + /* completion */
1340 + if (is_short || req->req.actual == req->req.length) {
1341 + done(ep, req, 0);
1342 + return 1;
1343 + }
1344 +
1345 + /* finished that packet. the next one may be waiting... */
1346 + return 0;
1347 +}
1348 +
1349 +/**
1350 + * udc_set_address - set the USB address for this device
1351 + * @address:
1352 + *
1353 + * Called from control endpoint function after it decodes a set address setup packet.
1354 + */
1355 +static void udc_set_address(struct jz4740_udc *dev, unsigned char address)
1356 +{
1357 + DEBUG_EP0("%s: %d\n", __FUNCTION__, address);
1358 +
1359 + usb_writeb(dev, JZ_REG_UDC_FADDR, address);
1360 +}
1361 +
1362 +/*
1363 + * DATA_STATE_RECV (USB_CSR0_OUTPKTRDY)
1364 + * - if error
1365 + * set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL bits
1366 + * - else
1367 + * set USB_CSR0_SVDOUTPKTRDY bit
1368 + if last set USB_CSR0_DATAEND bit
1369 + */
1370 +static void jz4740_ep0_out(struct jz4740_udc *dev, uint32_t csr, int kickstart)
1371 +{
1372 + struct jz4740_request *req;
1373 + struct jz4740_ep *ep = &dev->ep[0];
1374 + int ret;
1375 +
1376 + DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
1377 +
1378 + if (list_empty(&ep->queue))
1379 + req = 0;
1380 + else
1381 + req = list_entry(ep->queue.next, struct jz4740_request, queue);
1382 +
1383 + if (req) {
1384 + if (req->req.length == 0) {
1385 + DEBUG_EP0("ZERO LENGTH OUT!\n");
1386 + usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));
1387 + dev->ep0state = WAIT_FOR_SETUP;
1388 + return;
1389 + } else if (kickstart) {
1390 + usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY));
1391 + return;
1392 + }
1393 + ret = read_fifo_ep0(ep, req);
1394 + if (ret) {
1395 + /* Done! */
1396 + DEBUG_EP0("%s: finished, waiting for status\n",
1397 + __FUNCTION__);
1398 + usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));
1399 + dev->ep0state = WAIT_FOR_SETUP;
1400 + } else {
1401 + /* Not done yet.. */
1402 + DEBUG_EP0("%s: not finished\n", __FUNCTION__);
1403 + usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY);
1404 + }
1405 + } else {
1406 + DEBUG_EP0("NO REQ??!\n");
1407 + }
1408 +}
1409 +
1410 +/*
1411 + * DATA_STATE_XMIT
1412 + */
1413 +static int jz4740_ep0_in(struct jz4740_udc *dev, uint32_t csr)
1414 +{
1415 + struct jz4740_request *req;
1416 + struct jz4740_ep *ep = &dev->ep[0];
1417 + int ret, need_zlp = 0;
1418 +
1419 + DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
1420 +
1421 + if (list_empty(&ep->queue))
1422 + req = 0;
1423 + else
1424 + req = list_entry(ep->queue.next, struct jz4740_request, queue);
1425 +
1426 + if (!req) {
1427 + DEBUG_EP0("%s: NULL REQ\n", __FUNCTION__);
1428 + return 0;
1429 + }
1430 +
1431 + if (req->req.length == 0) {
1432 + usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND));
1433 + dev->ep0state = WAIT_FOR_SETUP;
1434 + return 1;
1435 + }
1436 +
1437 + if (req->req.length - req->req.actual == EP0_MAXPACKETSIZE) {
1438 + /* Next write will end with the packet size, */
1439 + /* so we need zero-length-packet */
1440 + need_zlp = 1;
1441 + }
1442 +
1443 + ret = write_fifo_ep0(ep, req);
1444 +
1445 + if (ret == 1 && !need_zlp) {
1446 + /* Last packet */
1447 + DEBUG_EP0("%s: finished, waiting for status\n", __FUNCTION__);
1448 +
1449 + usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND));
1450 + dev->ep0state = WAIT_FOR_SETUP;
1451 + } else {
1452 + DEBUG_EP0("%s: not finished\n", __FUNCTION__);
1453 + usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_INPKTRDY);
1454 + }
1455 +
1456 + if (need_zlp) {
1457 + DEBUG_EP0("%s: Need ZLP!\n", __FUNCTION__);
1458 + usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_INPKTRDY);
1459 + dev->ep0state = DATA_STATE_NEED_ZLP;
1460 + }
1461 +
1462 + return 1;
1463 +}
1464 +
1465 +static int jz4740_handle_get_status(struct jz4740_udc *dev,
1466 + struct usb_ctrlrequest *ctrl)
1467 +{
1468 + struct jz4740_ep *ep0 = &dev->ep[0];
1469 + struct jz4740_ep *qep;
1470 + int reqtype = (ctrl->bRequestType & USB_RECIP_MASK);
1471 + uint16_t val = 0;
1472 +
1473 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1474 +
1475 + if (reqtype == USB_RECIP_INTERFACE) {
1476 + /* This is not supported.
1477 + * And according to the USB spec, this one does nothing..
1478 + * Just return 0
1479 + */
1480 + DEBUG_SETUP("GET_STATUS: USB_RECIP_INTERFACE\n");
1481 + } else if (reqtype == USB_RECIP_DEVICE) {
1482 + DEBUG_SETUP("GET_STATUS: USB_RECIP_DEVICE\n");
1483 + val |= (1 << 0); /* Self powered */
1484 + /*val |= (1<<1); *//* Remote wakeup */
1485 + } else if (reqtype == USB_RECIP_ENDPOINT) {
1486 + int ep_num = (ctrl->wIndex & ~USB_DIR_IN);
1487 +
1488 + DEBUG_SETUP
1489 + ("GET_STATUS: USB_RECIP_ENDPOINT (%d), ctrl->wLength = %d\n",
1490 + ep_num, ctrl->wLength);
1491 +
1492 + if (ctrl->wLength > 2 || ep_num > 3)
1493 + return -EOPNOTSUPP;
1494 +
1495 + qep = &dev->ep[ep_num];
1496 + if (ep_is_in(qep) != ((ctrl->wIndex & USB_DIR_IN) ? 1 : 0)
1497 + && ep_index(qep) != 0) {
1498 + return -EOPNOTSUPP;
1499 + }
1500 +
1501 + jz_udc_select_ep(qep);
1502 +
1503 + /* Return status on next IN token */
1504 + switch (qep->type) {
1505 + case ep_control:
1506 + val =
1507 + (usb_readb(dev, qep->csr) & USB_CSR0_SENDSTALL) ==
1508 + USB_CSR0_SENDSTALL;
1509 + break;
1510 + case ep_bulk_in:
1511 + case ep_interrupt:
1512 + val =
1513 + (usb_readb(dev, qep->csr) & USB_INCSR_SENDSTALL) ==
1514 + USB_INCSR_SENDSTALL;
1515 + break;
1516 + case ep_bulk_out:
1517 + val =
1518 + (usb_readb(dev, qep->csr) & USB_OUTCSR_SENDSTALL) ==
1519 + USB_OUTCSR_SENDSTALL;
1520 + break;
1521 + }
1522 +
1523 + /* Back to EP0 index */
1524 + jz_udc_set_index(dev, 0);
1525 +
1526 + DEBUG_SETUP("GET_STATUS, ep: %d (%x), val = %d\n", ep_num,
1527 + ctrl->wIndex, val);
1528 + } else {
1529 + DEBUG_SETUP("Unknown REQ TYPE: %d\n", reqtype);
1530 + return -EOPNOTSUPP;
1531 + }
1532 +
1533 + /* Clear "out packet ready" */
1534 + usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY);
1535 + /* Put status to FIFO */
1536 + jz4740_fifo_write(ep0, (uint8_t *)&val, sizeof(val));
1537 + /* Issue "In packet ready" */
1538 + usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND));
1539 +
1540 + return 0;
1541 +}
1542 +
1543 +/*
1544 + * WAIT_FOR_SETUP (OUTPKTRDY)
1545 + * - read data packet from EP0 FIFO
1546 + * - decode command
1547 + * - if error
1548 + * set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL bits
1549 + * - else
1550 + * set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND bits
1551 + */
1552 +static void jz4740_ep0_setup(struct jz4740_udc *dev, uint32_t csr)
1553 +{
1554 + struct jz4740_ep *ep = &dev->ep[0];
1555 + struct usb_ctrlrequest ctrl;
1556 + int i;
1557 +
1558 + DEBUG_SETUP("%s: %x\n", __FUNCTION__, csr);
1559 +
1560 + /* Nuke all previous transfers */
1561 + nuke(ep, -EPROTO);
1562 +
1563 + /* read control req from fifo (8 bytes) */
1564 + jz4740_fifo_read(ep, (unsigned char *)&ctrl, 8);
1565 +
1566 + DEBUG_SETUP("SETUP %02x.%02x v%04x i%04x l%04x\n",
1567 + ctrl.bRequestType, ctrl.bRequest,
1568 + ctrl.wValue, ctrl.wIndex, ctrl.wLength);
1569 +
1570 + /* Set direction of EP0 */
1571 + if (likely(ctrl.bRequestType & USB_DIR_IN)) {
1572 + ep->bEndpointAddress |= USB_DIR_IN;
1573 + } else {
1574 + ep->bEndpointAddress &= ~USB_DIR_IN;
1575 + }
1576 +
1577 + /* Handle some SETUP packets ourselves */
1578 + switch (ctrl.bRequest) {
1579 + case USB_REQ_SET_ADDRESS:
1580 + if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1581 + break;
1582 +
1583 + DEBUG_SETUP("USB_REQ_SET_ADDRESS (%d)\n", ctrl.wValue);
1584 + udc_set_address(dev, ctrl.wValue);
1585 + usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));
1586 + return;
1587 +
1588 + case USB_REQ_SET_CONFIGURATION:
1589 + if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1590 + break;
1591 +
1592 + DEBUG_SETUP("USB_REQ_SET_CONFIGURATION (%d)\n", ctrl.wValue);
1593 +/* usb_setb(JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));*/
1594 +
1595 + /* Enable RESUME and SUSPEND interrupts */
1596 + usb_setb(dev, JZ_REG_UDC_INTRUSBE, (USB_INTR_RESUME | USB_INTR_SUSPEND));
1597 + break;
1598 +
1599 + case USB_REQ_SET_INTERFACE:
1600 + if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1601 + break;
1602 +
1603 + DEBUG_SETUP("USB_REQ_SET_INTERFACE (%d)\n", ctrl.wValue);
1604 +/* usb_setb(JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));*/
1605 + break;
1606 +
1607 + case USB_REQ_GET_STATUS:
1608 + if (jz4740_handle_get_status(dev, &ctrl) == 0)
1609 + return;
1610 +
1611 + case USB_REQ_CLEAR_FEATURE:
1612 + case USB_REQ_SET_FEATURE:
1613 + if (ctrl.bRequestType == USB_RECIP_ENDPOINT) {
1614 + struct jz4740_ep *qep;
1615 + int ep_num = (ctrl.wIndex & 0x0f);
1616 +
1617 + /* Support only HALT feature */
1618 + if (ctrl.wValue != 0 || ctrl.wLength != 0
1619 + || ep_num > 3 || ep_num < 1)
1620 + break;
1621 +
1622 + qep = &dev->ep[ep_num];
1623 + spin_unlock(&dev->lock);
1624 + if (ctrl.bRequest == USB_REQ_SET_FEATURE) {
1625 + DEBUG_SETUP("SET_FEATURE (%d)\n",
1626 + ep_num);
1627 + jz4740_set_halt(&qep->ep, 1);
1628 + } else {
1629 + DEBUG_SETUP("CLR_FEATURE (%d)\n",
1630 + ep_num);
1631 + jz4740_set_halt(&qep->ep, 0);
1632 + }
1633 + spin_lock(&dev->lock);
1634 +
1635 + jz_udc_set_index(dev, 0);
1636 +
1637 + /* Reply with a ZLP on next IN token */
1638 + usb_setb(dev, JZ_REG_UDC_CSR0,
1639 + (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));
1640 + return;
1641 + }
1642 + break;
1643 +
1644 + default:
1645 + break;
1646 + }
1647 +
1648 + /* gadget drivers see class/vendor specific requests,
1649 + * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION},
1650 + * and more.
1651 + */
1652 + if (dev->driver) {
1653 + /* device-2-host (IN) or no data setup command, process immediately */
1654 + spin_unlock(&dev->lock);
1655 +
1656 + i = dev->driver->setup(&dev->gadget, &ctrl);
1657 + spin_lock(&dev->lock);
1658 +
1659 + if (unlikely(i < 0)) {
1660 + /* setup processing failed, force stall */
1661 + DEBUG_SETUP
1662 + (" --> ERROR: gadget setup FAILED (stalling), setup returned %d\n",
1663 + i);
1664 + jz_udc_set_index(dev, 0);
1665 + usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL));
1666 +
1667 + /* ep->stopped = 1; */
1668 + dev->ep0state = WAIT_FOR_SETUP;
1669 + }
1670 + else {
1671 + DEBUG_SETUP("gadget driver setup ok (%d)\n", ctrl.wLength);
1672 +/* if (!ctrl.wLength) {
1673 + usb_setb(JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY);
1674 + }*/
1675 + }
1676 + }
1677 +}
1678 +
1679 +/*
1680 + * DATA_STATE_NEED_ZLP
1681 + */
1682 +static void jz4740_ep0_in_zlp(struct jz4740_udc *dev, uint32_t csr)
1683 +{
1684 + DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
1685 +
1686 + usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND));
1687 + dev->ep0state = WAIT_FOR_SETUP;
1688 +}
1689 +
1690 +/*
1691 + * handle ep0 interrupt
1692 + */
1693 +static void jz4740_handle_ep0(struct jz4740_udc *dev, uint32_t intr)
1694 +{
1695 + struct jz4740_ep *ep = &dev->ep[0];
1696 + uint32_t csr;
1697 +
1698 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1699 + /* Set index 0 */
1700 + jz_udc_set_index(dev, 0);
1701 + csr = usb_readb(dev, JZ_REG_UDC_CSR0);
1702 +
1703 + DEBUG_EP0("%s: csr = %x state = \n", __FUNCTION__, csr);//, state_names[dev->ep0state]);
1704 +
1705 + /*
1706 + * if SENT_STALL is set
1707 + * - clear the SENT_STALL bit
1708 + */
1709 + if (csr & USB_CSR0_SENTSTALL) {
1710 + DEBUG_EP0("%s: USB_CSR0_SENTSTALL is set: %x\n", __FUNCTION__, csr);
1711 + usb_clearb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SENDSTALL | USB_CSR0_SENTSTALL);
1712 + nuke(ep, -ECONNABORTED);
1713 + dev->ep0state = WAIT_FOR_SETUP;
1714 + return;
1715 + }
1716 +
1717 + /*
1718 + * if a transfer is in progress && INPKTRDY and OUTPKTRDY are clear
1719 + * - fill EP0 FIFO
1720 + * - if last packet
1721 + * - set IN_PKT_RDY | DATA_END
1722 + * - else
1723 + * set IN_PKT_RDY
1724 + */
1725 + if (!(csr & (USB_CSR0_INPKTRDY | USB_CSR0_OUTPKTRDY))) {
1726 + DEBUG_EP0("%s: INPKTRDY and OUTPKTRDY are clear\n",
1727 + __FUNCTION__);
1728 +
1729 + switch (dev->ep0state) {
1730 + case DATA_STATE_XMIT:
1731 + DEBUG_EP0("continue with DATA_STATE_XMIT\n");
1732 + jz4740_ep0_in(dev, csr);
1733 + return;
1734 + case DATA_STATE_NEED_ZLP:
1735 + DEBUG_EP0("continue with DATA_STATE_NEED_ZLP\n");
1736 + jz4740_ep0_in_zlp(dev, csr);
1737 + return;
1738 + default:
1739 + /* Stall? */
1740 +// DEBUG_EP0("Odd state!! state = %s\n",
1741 +// state_names[dev->ep0state]);
1742 + dev->ep0state = WAIT_FOR_SETUP;
1743 + /* nuke(ep, 0); */
1744 + /* usb_setb(ep->csr, USB_CSR0_SENDSTALL); */
1745 +// break;
1746 + return;
1747 + }
1748 + }
1749 +
1750 + /*
1751 + * if SETUPEND is set
1752 + * - abort the last transfer
1753 + * - set SERVICED_SETUP_END_BIT
1754 + */
1755 + if (csr & USB_CSR0_SETUPEND) {
1756 + DEBUG_EP0("%s: USB_CSR0_SETUPEND is set: %x\n", __FUNCTION__, csr);
1757 +
1758 + usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDSETUPEND);
1759 + nuke(ep, 0);
1760 + dev->ep0state = WAIT_FOR_SETUP;
1761 + }
1762 +
1763 + /*
1764 + * if USB_CSR0_OUTPKTRDY is set
1765 + * - read data packet from EP0 FIFO
1766 + * - decode command
1767 + * - if error
1768 + * set SVDOUTPKTRDY | DATAEND | SENDSTALL bits
1769 + * - else
1770 + * set SVDOUTPKTRDY | DATAEND bits
1771 + */
1772 + if (csr & USB_CSR0_OUTPKTRDY) {
1773 +
1774 + DEBUG_EP0("%s: EP0_OUT_PKT_RDY is set: %x\n", __FUNCTION__,
1775 + csr);
1776 +
1777 + switch (dev->ep0state) {
1778 + case WAIT_FOR_SETUP:
1779 + DEBUG_EP0("WAIT_FOR_SETUP\n");
1780 + jz4740_ep0_setup(dev, csr);
1781 + break;
1782 +
1783 + case DATA_STATE_RECV:
1784 + DEBUG_EP0("DATA_STATE_RECV\n");
1785 + jz4740_ep0_out(dev, csr, 0);
1786 + break;
1787 +
1788 + default:
1789 + /* send stall? */
1790 + DEBUG_EP0("strange state!! 2. send stall? state = %d\n",
1791 + dev->ep0state);
1792 + break;
1793 + }
1794 + }
1795 +}
1796 +
1797 +static void jz4740_ep0_kick(struct jz4740_udc *dev, struct jz4740_ep *ep)
1798 +{
1799 + uint32_t csr;
1800 +
1801 + jz_udc_set_index(dev, 0);
1802 +
1803 + DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
1804 +
1805 + /* Clear "out packet ready" */
1806 +
1807 + if (ep_is_in(ep)) {
1808 + usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY);
1809 + csr = usb_readb(dev, JZ_REG_UDC_CSR0);
1810 + dev->ep0state = DATA_STATE_XMIT;
1811 + jz4740_ep0_in(dev, csr);
1812 + } else {
1813 + csr = usb_readb(dev, JZ_REG_UDC_CSR0);
1814 + dev->ep0state = DATA_STATE_RECV;
1815 + jz4740_ep0_out(dev, csr, 1);
1816 + }
1817 +}
1818 +
1819 +/** Handle USB RESET interrupt
1820 + */
1821 +static void jz4740_reset_irq(struct jz4740_udc *dev)
1822 +{
1823 + dev->gadget.speed = (usb_readb(dev, JZ_REG_UDC_POWER) & USB_POWER_HSMODE) ?
1824 + USB_SPEED_HIGH : USB_SPEED_FULL;
1825 +
1826 + DEBUG_SETUP("%s: address = %d, speed = %s\n", __FUNCTION__, 0,
1827 + (dev->gadget.speed == USB_SPEED_HIGH) ? "HIGH":"FULL" );
1828 +}
1829 +
1830 +/*
1831 + * jz4740 usb device interrupt handler.
1832 + */
1833 +static irqreturn_t jz4740_udc_irq(int irq, void *devid)
1834 +{
1835 + struct jz4740_udc *jz4740_udc = devid;
1836 + uint8_t index;
1837 +
1838 + uint32_t intr_usb = usb_readb(jz4740_udc, JZ_REG_UDC_INTRUSB) & 0x7; /* mask SOF */
1839 + uint32_t intr_in = usb_readw(jz4740_udc, JZ_REG_UDC_INTRIN);
1840 + uint32_t intr_out = usb_readw(jz4740_udc, JZ_REG_UDC_INTROUT);
1841 + uint32_t intr_dma = usb_readb(jz4740_udc, JZ_REG_UDC_INTR);
1842 +
1843 + if (!intr_usb && !intr_in && !intr_out && !intr_dma)
1844 + return IRQ_HANDLED;
1845 +
1846 +
1847 + DEBUG("intr_out=%x intr_in=%x intr_usb=%x\n",
1848 + intr_out, intr_in, intr_usb);
1849 +
1850 + spin_lock(&jz4740_udc->lock);
1851 + index = usb_readb(jz4740_udc, JZ_REG_UDC_INDEX);
1852 +
1853 + /* Check for resume from suspend mode */
1854 + if ((intr_usb & USB_INTR_RESUME) &&
1855 + (usb_readb(jz4740_udc, JZ_REG_UDC_INTRUSBE) & USB_INTR_RESUME)) {
1856 + DEBUG("USB resume\n");
1857 + jz4740_udc->driver->resume(&jz4740_udc->gadget); /* We have suspend(), so we must have resume() too. */
1858 + }
1859 +
1860 + /* Check for system interrupts */
1861 + if (intr_usb & USB_INTR_RESET) {
1862 + DEBUG("USB reset\n");
1863 + jz4740_reset_irq(jz4740_udc);
1864 + }
1865 +
1866 + /* Check for endpoint 0 interrupt */
1867 + if (intr_in & USB_INTR_EP0) {
1868 + DEBUG("USB_INTR_EP0 (control)\n");
1869 + jz4740_handle_ep0(jz4740_udc, intr_in);
1870 + }
1871 +
1872 + /* Check for Bulk-IN DMA interrupt */
1873 + if (intr_dma & 0x1) {
1874 + int ep_num;
1875 + struct jz4740_ep *ep;
1876 + ep_num = (usb_readl(jz4740_udc, JZ_REG_UDC_CNTL1) >> 4) & 0xf;
1877 + ep = &jz4740_udc->ep[ep_num + 1];
1878 + jz_udc_select_ep(ep);
1879 + usb_setb(jz4740_udc, ep->csr, USB_INCSR_INPKTRDY);
1880 +/* jz4740_in_epn(jz4740_udc, ep_num, intr_in);*/
1881 + }
1882 +
1883 + /* Check for Bulk-OUT DMA interrupt */
1884 + if (intr_dma & 0x2) {
1885 + int ep_num;
1886 + ep_num = (usb_readl(jz4740_udc, JZ_REG_UDC_CNTL2) >> 4) & 0xf;
1887 + jz4740_out_epn(jz4740_udc, ep_num, intr_out);
1888 + }
1889 +
1890 + /* Check for each configured endpoint interrupt */
1891 + if (intr_in & USB_INTR_INEP1) {
1892 + DEBUG("USB_INTR_INEP1\n");
1893 + jz4740_in_epn(jz4740_udc, 1, intr_in);
1894 + }
1895 +
1896 + if (intr_in & USB_INTR_INEP2) {
1897 + DEBUG("USB_INTR_INEP2\n");
1898 + jz4740_in_epn(jz4740_udc, 2, intr_in);
1899 + }
1900 +
1901 + if (intr_out & USB_INTR_OUTEP1) {
1902 + DEBUG("USB_INTR_OUTEP1\n");
1903 + jz4740_out_epn(jz4740_udc, 1, intr_out);
1904 + }
1905 +
1906 + /* Check for suspend mode */
1907 + if ((intr_usb & USB_INTR_SUSPEND) &&
1908 + (usb_readb(jz4740_udc, JZ_REG_UDC_INTRUSBE) & USB_INTR_SUSPEND)) {
1909 + DEBUG("USB suspend\n");
1910 + jz4740_udc->driver->suspend(&jz4740_udc->gadget);
1911 + /* Host unloaded from us, can do something, such as flushing
1912 + the NAND block cache etc. */
1913 + }
1914 +
1915 + jz_udc_set_index(jz4740_udc, index);
1916 +
1917 + spin_unlock(&jz4740_udc->lock);
1918 +
1919 + return IRQ_HANDLED;
1920 +}
1921 +
1922 +
1923 +
1924 +/*-------------------------------------------------------------------------*/
1925 +
1926 +
1927 +static inline struct jz4740_udc *gadget_to_udc(struct usb_gadget *gadget)
1928 +{
1929 + return container_of(gadget, struct jz4740_udc, gadget);
1930 +}
1931 +
1932 +static int jz4740_udc_get_frame(struct usb_gadget *_gadget)
1933 +{
1934 + DEBUG("%s, %p\n", __FUNCTION__, _gadget);
1935 + return usb_readw(gadget_to_udc(_gadget), JZ_REG_UDC_FRAME);
1936 +}
1937 +
1938 +static int jz4740_udc_wakeup(struct usb_gadget *_gadget)
1939 +{
1940 + /* host may not have enabled remote wakeup */
1941 + /*if ((UDCCS0 & UDCCS0_DRWF) == 0)
1942 + return -EHOSTUNREACH;
1943 + udc_set_mask_UDCCR(UDCCR_RSM); */
1944 + return -ENOTSUPP;
1945 +}
1946 +
1947 +static int jz4740_udc_pullup(struct usb_gadget *_gadget, int on)
1948 +{
1949 + struct jz4740_udc *udc = gadget_to_udc(_gadget);
1950 + unsigned long flags;
1951 +
1952 + local_irq_save(flags);
1953 +
1954 + if (on) {
1955 + udc->state = UDC_STATE_ENABLE;
1956 + udc_enable(udc);
1957 + } else {
1958 + udc->state = UDC_STATE_DISABLE;
1959 + udc_disable(udc);
1960 + }
1961 +
1962 + local_irq_restore(flags);
1963 +
1964 + return 0;
1965 +}
1966 +
1967 +static const struct usb_gadget_ops jz4740_udc_ops = {
1968 + .get_frame = jz4740_udc_get_frame,
1969 + .wakeup = jz4740_udc_wakeup,
1970 + .pullup = jz4740_udc_pullup,
1971 + .udc_start = jz4740_udc_start,
1972 + .udc_stop = jz4740_udc_stop,
1973 +};
1974 +
1975 +static struct usb_ep_ops jz4740_ep_ops = {
1976 + .enable = jz4740_ep_enable,
1977 + .disable = jz4740_ep_disable,
1978 +
1979 + .alloc_request = jz4740_alloc_request,
1980 + .free_request = jz4740_free_request,
1981 +
1982 + .queue = jz4740_queue,
1983 + .dequeue = jz4740_dequeue,
1984 +
1985 + .set_halt = jz4740_set_halt,
1986 + .fifo_status = jz4740_fifo_status,
1987 + .fifo_flush = jz4740_fifo_flush,
1988 +};
1989 +
1990 +
1991 +/*-------------------------------------------------------------------------*/
1992 +
1993 +static struct jz4740_udc jz4740_udc_controller = {
1994 + .gadget = {
1995 + .ops = &jz4740_udc_ops,
1996 + .ep0 = &jz4740_udc_controller.ep[0].ep,
1997 + .max_speed = USB_SPEED_HIGH,
1998 + .name = "jz4740-udc",
1999 + .dev = {
2000 + .init_name = "gadget",
2001 + },
2002 + },
2003 +
2004 + /* control endpoint */
2005 + .ep[0] = {
2006 + .ep = {
2007 + .name = "ep0",
2008 + .ops = &jz4740_ep_ops,
2009 + .maxpacket = EP0_MAXPACKETSIZE,
2010 + },
2011 + .dev = &jz4740_udc_controller,
2012 +
2013 + .bEndpointAddress = 0,
2014 + .bmAttributes = 0,
2015 +
2016 + .type = ep_control,
2017 + .fifo = JZ_REG_UDC_EP_FIFO(0),
2018 + .csr = JZ_REG_UDC_CSR0,
2019 + },
2020 +
2021 + /* bulk out endpoint */
2022 + .ep[1] = {
2023 + .ep = {
2024 + .name = "ep1out-bulk",
2025 + .ops = &jz4740_ep_ops,
2026 + .maxpacket = EPBULK_MAXPACKETSIZE,
2027 + },
2028 + .dev = &jz4740_udc_controller,
2029 +
2030 + .bEndpointAddress = 1,
2031 + .bmAttributes = USB_ENDPOINT_XFER_BULK,
2032 +
2033 + .type = ep_bulk_out,
2034 + .fifo = JZ_REG_UDC_EP_FIFO(1),
2035 + .csr = JZ_REG_UDC_OUTCSR,
2036 + },
2037 +
2038 + /* bulk in endpoint */
2039 + .ep[2] = {
2040 + .ep = {
2041 + .name = "ep1in-bulk",
2042 + .ops = &jz4740_ep_ops,
2043 + .maxpacket = EPBULK_MAXPACKETSIZE,
2044 + },
2045 + .dev = &jz4740_udc_controller,
2046 +
2047 + .bEndpointAddress = 1 | USB_DIR_IN,
2048 + .bmAttributes = USB_ENDPOINT_XFER_BULK,
2049 +
2050 + .type = ep_bulk_in,
2051 + .fifo = JZ_REG_UDC_EP_FIFO(1),
2052 + .csr = JZ_REG_UDC_INCSR,
2053 + },
2054 +
2055 + /* interrupt in endpoint */
2056 + .ep[3] = {
2057 + .ep = {
2058 + .name = "ep2in-int",
2059 + .ops = &jz4740_ep_ops,
2060 + .maxpacket = EPINTR_MAXPACKETSIZE,
2061 + },
2062 + .dev = &jz4740_udc_controller,
2063 +
2064 + .bEndpointAddress = 2 | USB_DIR_IN,
2065 + .bmAttributes = USB_ENDPOINT_XFER_INT,
2066 +
2067 + .type = ep_interrupt,
2068 + .fifo = JZ_REG_UDC_EP_FIFO(2),
2069 + .csr = JZ_REG_UDC_INCSR,
2070 + },
2071 +};
2072 +
2073 +static int jz4740_udc_probe(struct platform_device *pdev)
2074 +{
2075 + struct jz4740_udc *jz4740_udc = &jz4740_udc_controller;
2076 + int ret;
2077 +
2078 + spin_lock_init(&jz4740_udc->lock);
2079 +
2080 + jz4740_udc->dev = &pdev->dev;
2081 +
2082 + jz4740_udc->clk = clk_get(&pdev->dev, "udc");
2083 + if (IS_ERR(jz4740_udc->clk)) {
2084 + ret = PTR_ERR(jz4740_udc->clk);
2085 + dev_err(&pdev->dev, "Failed to get udc clock: %d\n", ret);
2086 + return ret;
2087 + }
2088 +
2089 + platform_set_drvdata(pdev, jz4740_udc);
2090 +
2091 + jz4740_udc->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2092 +
2093 + if (!jz4740_udc->mem) {
2094 + ret = -ENOENT;
2095 + dev_err(&pdev->dev, "Failed to get mmio memory resource\n");
2096 + goto err_clk_put;
2097 + }
2098 +
2099 + jz4740_udc->mem = request_mem_region(jz4740_udc->mem->start,
2100 + resource_size(jz4740_udc->mem), pdev->name);
2101 +
2102 + if (!jz4740_udc->mem) {
2103 + ret = -EBUSY;
2104 + dev_err(&pdev->dev, "Failed to request mmio memory region\n");
2105 + goto err_clk_put;
2106 + }
2107 +
2108 + jz4740_udc->base = ioremap(jz4740_udc->mem->start, resource_size(jz4740_udc->mem));
2109 +
2110 + if (!jz4740_udc->base) {
2111 + ret = -EBUSY;
2112 + dev_err(&pdev->dev, "Failed to ioremap mmio memory\n");
2113 + goto err_release_mem_region;
2114 + }
2115 +
2116 + jz4740_udc->irq = platform_get_irq(pdev, 0);
2117 + ret = request_irq(jz4740_udc->irq, jz4740_udc_irq, 0, pdev->name,
2118 + jz4740_udc);
2119 + if (ret) {
2120 + dev_err(&pdev->dev, "Failed to request irq: %d\n", ret);
2121 + goto err_iounmap;
2122 + }
2123 +
2124 + ret = usb_add_gadget_udc(&pdev->dev, &jz4740_udc->gadget);
2125 + if (ret) {
2126 + dev_err(&pdev->dev, "Failed to add gadget: %d\n", ret);
2127 + goto err_free_irq;
2128 + }
2129 +
2130 +/* udc_disable(jz4740_udc);*/
2131 + udc_reinit(jz4740_udc);
2132 +
2133 + return 0;
2134 +
2135 +err_free_irq:
2136 + free_irq(jz4740_udc->irq, pdev);
2137 +err_iounmap:
2138 + iounmap(jz4740_udc->base);
2139 +err_release_mem_region:
2140 + release_mem_region(jz4740_udc->mem->start, resource_size(jz4740_udc->mem));
2141 +err_clk_put:
2142 + clk_put(jz4740_udc->clk);
2143 +
2144 + return ret;
2145 +}
2146 +
2147 +static int jz4740_udc_remove(struct platform_device *pdev)
2148 +{
2149 + struct jz4740_udc *dev = platform_get_drvdata(pdev);
2150 +
2151 + usb_del_gadget_udc(&dev->gadget);
2152 + if (dev->driver)
2153 + return -EBUSY;
2154 +
2155 + udc_disable(dev);
2156 +
2157 + free_irq(dev->irq, dev);
2158 + iounmap(dev->base);
2159 + release_mem_region(dev->mem->start, resource_size(dev->mem));
2160 + clk_put(dev->clk);
2161 +
2162 + return 0;
2163 +}
2164 +
2165 +#ifdef CONFIG_PM
2166 +
2167 +static int jz4740_udc_suspend(struct device *dev)
2168 +{
2169 + struct jz4740_udc *jz4740_udc = dev_get_drvdata(dev);
2170 +
2171 + if (jz4740_udc->state == UDC_STATE_ENABLE)
2172 + udc_disable(jz4740_udc);
2173 +
2174 + return 0;
2175 +}
2176 +
2177 +static int jz4740_udc_resume(struct device *dev)
2178 +{
2179 + struct jz4740_udc *jz4740_udc = dev_get_drvdata(dev);
2180 +
2181 + if (jz4740_udc->state == UDC_STATE_ENABLE)
2182 + udc_enable(jz4740_udc);
2183 +
2184 + return 0;
2185 +}
2186 +
2187 +static SIMPLE_DEV_PM_OPS(jz4740_udc_pm_ops, jz4740_udc_suspend, jz4740_udc_resume);
2188 +#define JZ4740_UDC_PM_OPS (&jz4740_udc_pm_ops)
2189 +
2190 +#else
2191 +#define JZ4740_UDC_PM_OPS NULL
2192 +#endif
2193 +
2194 +static struct platform_driver udc_driver = {
2195 + .probe = jz4740_udc_probe,
2196 + .remove = jz4740_udc_remove,
2197 + .driver = {
2198 + .name = "jz-udc",
2199 + .owner = THIS_MODULE,
2200 + .pm = JZ4740_UDC_PM_OPS,
2201 + },
2202 +};
2203 +
2204 +/*-------------------------------------------------------------------------*/
2205 +
2206 +static int __init udc_init (void)
2207 +{
2208 + return platform_driver_register(&udc_driver);
2209 +}
2210 +module_init(udc_init);
2211 +
2212 +static void __exit udc_exit (void)
2213 +{
2214 + platform_driver_unregister(&udc_driver);
2215 +}
2216 +module_exit(udc_exit);
2217 +
2218 +MODULE_DESCRIPTION("JZ4740 USB Device Controller");
2219 +MODULE_AUTHOR("Wei Jianli <jlwei@ingenic.cn>");
2220 +MODULE_LICENSE("GPL");
2221 diff --git a/drivers/usb/gadget/jz4740_udc.h b/drivers/usb/gadget/jz4740_udc.h
2222 new file mode 100644
2223 index 0000000..53fd1da
2224 --- /dev/null
2225 +++ b/drivers/usb/gadget/jz4740_udc.h
2226 @@ -0,0 +1,101 @@
2227 +/*
2228 + * linux/drivers/usb/gadget/jz4740_udc.h
2229 + *
2230 + * Ingenic JZ4740 on-chip high speed USB device controller
2231 + *
2232 + * Copyright (C) 2006 Ingenic Semiconductor Inc.
2233 + * Author: <jlwei@ingenic.cn>
2234 + *
2235 + * This program is free software; you can redistribute it and/or modify
2236 + * it under the terms of the GNU General Public License as published by
2237 + * the Free Software Foundation; either version 2 of the License, or
2238 + * (at your option) any later version.
2239 + */
2240 +
2241 +#ifndef __USB_GADGET_JZ4740_H__
2242 +#define __USB_GADGET_JZ4740_H__
2243 +
2244 +/*-------------------------------------------------------------------------*/
2245 +
2246 +// Max packet size
2247 +#define EP0_MAXPACKETSIZE 64
2248 +#define EPBULK_MAXPACKETSIZE 512
2249 +#define EPINTR_MAXPACKETSIZE 64
2250 +
2251 +#define UDC_MAX_ENDPOINTS 4
2252 +
2253 +/*-------------------------------------------------------------------------*/
2254 +
2255 +enum ep_type {
2256 + ep_control, ep_bulk_in, ep_bulk_out, ep_interrupt
2257 +};
2258 +
2259 +struct jz4740_ep {
2260 + struct usb_ep ep;
2261 + struct jz4740_udc *dev;
2262 +
2263 + const struct usb_endpoint_descriptor *desc;
2264 +
2265 + uint8_t stopped;
2266 + uint8_t bEndpointAddress;
2267 + uint8_t bmAttributes;
2268 +
2269 + enum ep_type type;
2270 + size_t fifo;
2271 + uint32_t csr;
2272 +
2273 + uint32_t reg_addr;
2274 + struct list_head queue;
2275 +};
2276 +
2277 +struct jz4740_request {
2278 + struct usb_request req;
2279 + struct list_head queue;
2280 +};
2281 +
2282 +enum ep0state {
2283 + WAIT_FOR_SETUP, /* between STATUS ack and SETUP report */
2284 + DATA_STATE_XMIT, /* data tx stage */
2285 + DATA_STATE_NEED_ZLP, /* data tx zlp stage */
2286 + WAIT_FOR_OUT_STATUS, /* status stages */
2287 + DATA_STATE_RECV, /* data rx stage */
2288 +};
2289 +
2290 +/* For function binding with UDC Disable - Added by River */
2291 +typedef enum {
2292 + UDC_STATE_ENABLE = 0,
2293 + UDC_STATE_DISABLE,
2294 +}udc_state_t;
2295 +
2296 +struct jz4740_udc {
2297 + struct usb_gadget gadget;
2298 + struct usb_gadget_driver *driver;
2299 + struct device *dev;
2300 + spinlock_t lock;
2301 + unsigned long lock_flags;
2302 +
2303 + enum ep0state ep0state;
2304 + struct jz4740_ep ep[UDC_MAX_ENDPOINTS];
2305 +
2306 + udc_state_t state;
2307 +
2308 + struct resource *mem;
2309 + void __iomem *base;
2310 + int irq;
2311 +
2312 + struct clk *clk;
2313 +};
2314 +
2315 +#define ep_maxpacket(EP) ((EP)->ep.maxpacket)
2316 +
2317 +static inline bool ep_is_in(const struct jz4740_ep *ep)
2318 +{
2319 + return (ep->bEndpointAddress & USB_DIR_IN) == USB_DIR_IN;
2320 +}
2321 +
2322 +static inline uint8_t ep_index(const struct jz4740_ep *ep)
2323 +{
2324 + return ep->bEndpointAddress & 0xf;
2325 +}
2326 +
2327 +#endif /* __USB_GADGET_JZ4740_H__ */
2328 --
2329 1.7.10.4
2330
Yousong Zhou staging tree